407 lines
11 KiB
C
Executable File
407 lines
11 KiB
C
Executable File
/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <arch_helpers.h>
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#include <assert.h>
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#include <cassert.h>
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#include <platform_def.h>
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#include <string.h>
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#include <xlat_tables.h>
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#include <stdio.h>
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#ifndef DEBUG_XLAT_TABLE
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#define DEBUG_XLAT_TABLE 0
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#endif
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#if DEBUG_XLAT_TABLE
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#define debug_print(...) printf(__VA_ARGS__)
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#else
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#define debug_print(...) ((void)0)
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#endif
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CASSERT(ADDR_SPACE_SIZE > 0, assert_valid_addr_space_size);
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#define UNSET_DESC ~0ul
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#define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
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static uint64_t l1_xlation_table[NUM_L1_ENTRIES]
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__aligned(NUM_L1_ENTRIES * sizeof(uint64_t));
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static uint64_t xlat_tables[MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
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__aligned(XLAT_TABLE_SIZE) __attribute__((section("xlat_table")));
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static unsigned next_xlat;
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static unsigned long max_pa;
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static unsigned long max_va;
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static unsigned long tcr_ps_bits;
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/*
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* Array of all memory regions stored in order of ascending base address.
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* The list is terminated by the first entry with size == 0.
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*/
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static mmap_region_t mmap[MAX_MMAP_REGIONS + 1];
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static void print_mmap(void)
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{
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#if DEBUG_XLAT_TABLE
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debug_print("mmap:\n");
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mmap_region_t *mm = mmap;
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while (mm->size) {
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debug_print(" %010lx %010lx %10lx %x\n", mm->base_va,
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mm->base_pa, mm->size, mm->attr);
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++mm;
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};
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debug_print("\n");
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#endif
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}
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void mmap_add_region(unsigned long base_pa, unsigned long base_va,
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unsigned long size, unsigned attr)
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{
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mmap_region_t *mm = mmap;
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mmap_region_t *mm_last = mm + sizeof(mmap) / sizeof(mmap[0]) - 1;
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unsigned long pa_end = base_pa + size - 1;
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unsigned long va_end = base_va + size - 1;
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assert(IS_PAGE_ALIGNED(base_pa));
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assert(IS_PAGE_ALIGNED(base_va));
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assert(IS_PAGE_ALIGNED(size));
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if (!size)
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return;
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/* Find correct place in mmap to insert new region */
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while (mm->base_va < base_va && mm->size)
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++mm;
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/* Make room for new region by moving other regions up by one place */
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memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm);
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/* Check we haven't lost the empty sentinal from the end of the array */
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assert(mm_last->size == 0);
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mm->base_pa = base_pa;
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mm->base_va = base_va;
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mm->size = size;
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mm->attr = attr;
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if (pa_end > max_pa)
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max_pa = pa_end;
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if (va_end > max_va)
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max_va = va_end;
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}
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void mmap_add(const mmap_region_t *mm)
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{
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while (mm->size) {
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mmap_add_region(mm->base_pa, mm->base_va, mm->size, mm->attr);
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++mm;
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}
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}
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static unsigned long mmap_desc(unsigned attr, unsigned long addr_pa,
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unsigned level)
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{
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unsigned long desc = addr_pa;
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desc |= level == 3 ? TABLE_DESC : BLOCK_DESC;
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desc |= attr & MT_NS ? LOWER_ATTRS(NS) : 0;
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desc |= attr & MT_RW ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO);
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desc |= LOWER_ATTRS(ACCESS_FLAG);
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if (attr & MT_MEMORY) {
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desc |= LOWER_ATTRS(ATTR_IWBWA_OWBWA_NTR_INDEX | ISH);
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if (attr & MT_RW)
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desc |= UPPER_ATTRS(XN);
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} else {
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desc |= LOWER_ATTRS(ATTR_DEVICE_INDEX | OSH);
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desc |= UPPER_ATTRS(XN);
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}
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debug_print(attr & MT_MEMORY ? "MEM" : "DEV");
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debug_print(attr & MT_RW ? "-RW" : "-RO");
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debug_print(attr & MT_NS ? "-NS" : "-S");
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return desc;
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}
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static int mmap_region_attr(mmap_region_t *mm, unsigned long base_va,
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unsigned long size)
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{
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int attr = mm->attr;
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for (;;) {
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++mm;
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if (!mm->size)
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return attr; /* Reached end of list */
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if (mm->base_va >= base_va + size)
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return attr; /* Next region is after area so end */
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if (mm->base_va + mm->size <= base_va)
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continue; /* Next region has already been overtaken */
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if ((mm->attr & attr) == attr)
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continue; /* Region doesn't override attribs so skip */
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attr &= mm->attr;
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if (mm->base_va > base_va ||
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mm->base_va + mm->size < base_va + size)
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return -1; /* Region doesn't fully cover our area */
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}
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}
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static mmap_region_t *init_xlation_table(mmap_region_t *mm,
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unsigned long base_va,
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unsigned long *table, unsigned level)
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{
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unsigned level_size_shift = L1_XLAT_ADDRESS_SHIFT - (level - 1) *
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XLAT_TABLE_ENTRIES_SHIFT;
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unsigned level_size = 1 << level_size_shift;
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unsigned long level_index_mask = XLAT_TABLE_ENTRIES_MASK << level_size_shift;
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assert(level <= 3);
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debug_print("New xlat table:\n");
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do {
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unsigned long desc = UNSET_DESC;
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if (mm->base_va + mm->size <= base_va) {
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/* Area now after the region so skip it */
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++mm;
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continue;
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}
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debug_print(" %010lx %8lx " + 6 - 2 * level, base_va,
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level_size);
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if (mm->base_va >= base_va + level_size) {
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/* Next region is after area so nothing to map yet */
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desc = INVALID_DESC;
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} else if (mm->base_va <= base_va && mm->base_va + mm->size >=
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base_va + level_size) {
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/* Next region covers all of area */
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int attr = mmap_region_attr(mm, base_va, level_size);
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if (attr >= 0)
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desc = mmap_desc(attr,
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base_va - mm->base_va + mm->base_pa,
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level);
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}
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/* else Next region only partially covers area, so need */
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if (desc == UNSET_DESC) {
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/* Area not covered by a region so need finer table */
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unsigned long *new_table = xlat_tables[next_xlat++];
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assert(next_xlat <= MAX_XLAT_TABLES);
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desc = TABLE_DESC | (unsigned long)new_table;
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/* Recurse to fill in new table */
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mm = init_xlation_table(mm, base_va,
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new_table, level+1);
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}
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debug_print("\n");
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*table++ = desc;
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base_va += level_size;
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} while (mm->size && (base_va & level_index_mask));
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return mm;
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}
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static unsigned int calc_physical_addr_size_bits(unsigned long max_addr)
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{
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/* Physical address can't exceed 48 bits */
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assert((max_addr & ADDR_MASK_48_TO_63) == 0);
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/* 48 bits address */
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if (max_addr & ADDR_MASK_44_TO_47)
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return TCR_PS_BITS_256TB;
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/* 44 bits address */
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if (max_addr & ADDR_MASK_42_TO_43)
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return TCR_PS_BITS_16TB;
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/* 42 bits address */
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if (max_addr & ADDR_MASK_40_TO_41)
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return TCR_PS_BITS_4TB;
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/* 40 bits address */
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if (max_addr & ADDR_MASK_36_TO_39)
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return TCR_PS_BITS_1TB;
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/* 36 bits address */
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if (max_addr & ADDR_MASK_32_TO_35)
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return TCR_PS_BITS_64GB;
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return TCR_PS_BITS_4GB;
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}
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void init_xlat_tables(void)
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{
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print_mmap();
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init_xlation_table(mmap, 0, l1_xlation_table, 1);
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tcr_ps_bits = calc_physical_addr_size_bits(max_pa);
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assert(max_va < ADDR_SPACE_SIZE);
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}
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/*******************************************************************************
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* Macro generating the code for the function enabling the MMU in the given
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* exception level, assuming that the pagetables have already been created.
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*
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* _el: Exception level at which the function will run
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* _tcr_extra: Extra bits to set in the TCR register. This mask will
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* be OR'ed with the default TCR value.
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* _tlbi_fct: Function to invalidate the TLBs at the current
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* exception level
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******************************************************************************/
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#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \
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void enable_mmu_el##_el(uint32_t flags) \
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{ \
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uint64_t mair, tcr, ttbr; \
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uint32_t sctlr; \
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\
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assert(IS_IN_EL(_el)); \
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assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \
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\
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/* Set attributes in the right indices of the MAIR */ \
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mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \
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mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \
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ATTR_IWBWA_OWBWA_NTR_INDEX); \
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write_mair_el##_el(mair); \
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\
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/* Invalidate TLBs at the current exception level */ \
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_tlbi_fct(); \
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\
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/* Set TCR bits as well. */ \
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/* Inner & outer WBWA & shareable + T0SZ = 32 */ \
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tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \
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TCR_RGN_INNER_WBA | \
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(64 - __builtin_ctzl(ADDR_SPACE_SIZE)); \
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tcr |= _tcr_extra; \
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write_tcr_el##_el(tcr); \
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\
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/* Set TTBR bits as well */ \
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ttbr = (uint64_t) l1_xlation_table; \
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write_ttbr0_el##_el(ttbr); \
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\
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/* Ensure all translation table writes have drained */ \
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/* into memory, the TLB invalidation is complete, */ \
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/* and translation register writes are committed */ \
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/* before enabling the MMU */ \
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dsb(); \
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isb(); \
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\
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sctlr = read_sctlr_el##_el(); \
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
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\
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if (flags & DISABLE_DCACHE) \
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sctlr &= ~SCTLR_C_BIT; \
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else \
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sctlr |= SCTLR_C_BIT; \
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\
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write_sctlr_el##_el(sctlr); \
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\
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/* Ensure the MMU enable takes effect immediately */ \
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isb(); \
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}
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/* Define EL1 and EL3 variants of the function enabling the MMU */
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DEFINE_ENABLE_MMU_EL(1,
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(tcr_ps_bits << TCR_EL1_IPS_SHIFT),
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tlbivmalle1)
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DEFINE_ENABLE_MMU_EL(3,
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TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT),
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tlbialle3)
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#if 0
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void enable_mmu_el3(uint32_t flags)
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{
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uint64_t mair, tcr, ttbr;
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uint32_t sctlr;
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uint32_t _tcr_extra = TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT);
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assert(IS_IN_EL(_el));
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assert((read_sctlr_el3() & SCTLR_M_BIT) == 0);
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/* Set attributes in the right indices of the MAIR */
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mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
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mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
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ATTR_IWBWA_OWBWA_NTR_INDEX);
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write_mair_el3(mair);
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/* Invalidate TLBs at the current exception level */
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tlbialle3();
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/* Set TCR bits as well. */
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/* Inner & outer WBWA & shareable + T0SZ = 32 */
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tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA |
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TCR_RGN_INNER_WBA |
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(64 - __builtin_ctzl(ADDR_SPACE_SIZE));
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tcr |= _tcr_extra;
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write_tcr_el3(tcr);
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/* Set TTBR bits as well */
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ttbr = (uint64_t) l1_xlation_table;
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write_ttbr0_el3(ttbr);
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/* Ensure all translation table writes have drained */
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/* into memory, the TLB invalidation is complete, */
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/* and translation register writes are committed */
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/* before enabling the MMU */
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dsb();
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isb();
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sctlr = read_sctlr_el3();
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sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT;
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if (flags & DISABLE_DCACHE)
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sctlr &= ~SCTLR_C_BIT;
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else
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sctlr |= SCTLR_C_BIT;
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write_sctlr_el3(sctlr);
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/* Ensure the MMU enable takes effect immediately */
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isb();
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}
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#endif
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