/*
 * arch/arm/mach-sunxi/platsmp-v1.h
 *
 * Copyright(c) 2013-2015 Allwinnertech Co., Ltd.
 *      http://www.allwinnertech.com
 *
 * Author: east_yang <yangdong@allwinnertech.com>
 *
 * sunxi smp ops header file for platform v1
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef __PLATSMP_V1_H__
#define __PLATSMP_V1_H__

static inline int sunxi_is_wfi_mode(int cpu)
{
#ifdef CONFIG_EVB_PLATFORM
	return readl(sunxi_cpucfg_base + CPUCFG_CPU_STATUS_REG(cpu)) & (1<<2);
#else
	return 1;
#endif
}

static inline void sunxi_enable_cpu(int cpu)
{
	unsigned int value;

	/*  Assert nCOREPORESET LOW and hold L1RSTDISABLE LOW.
	 *  Ensure DBGPWRDUP is held LOW to prevent any external
	 *  debug access to the processor.
	 */
	/* assert cpu core reset */
	writel(0, sunxi_cpucfg_base + CPUCFG_CPU_RST_CTRL_REG(cpu));

	/* L1RSTDISABLE hold low */
	value = readl(sunxi_cpucfg_base + CPUCFG_GEN_CTRL_REG);

	value &= ~(1<<cpu);
	writel(value, sunxi_cpucfg_base + CPUCFG_GEN_CTRL_REG);
	udelay(10);

	/* DBGPWRDUP hold low */
	value = readl(sunxi_cpucfg_base + CPUCFG_DBG_CTL1_REG);

	value &= ~(1<<cpu);
	writel(value, sunxi_cpucfg_base + CPUCFG_DBG_CTL1_REG);

#ifndef CONFIG_ARCH_SUN8IW10
	/* Release power switch */
	writel(0xFE, sunxi_cpucfg_base + CPUCFG_PWR_SWITCH_REG(cpu));
	udelay(20);
	writel(0xF8, sunxi_cpucfg_base + CPUCFG_PWR_SWITCH_REG(cpu));
	udelay(10);
	writel(0xE0, sunxi_cpucfg_base + CPUCFG_PWR_SWITCH_REG(cpu));
	udelay(10);
	writel(0x80, sunxi_cpucfg_base + CPUCFG_PWR_SWITCH_REG(cpu));
	udelay(10);
	writel(0x00, sunxi_cpucfg_base + CPUCFG_PWR_SWITCH_REG(cpu));
	udelay(20);
	while (readl(sunxi_cpucfg_base + CPUCFG_PWR_SWITCH_REG(cpu)) != 0x00)
		;

	/* Clear power-off gating */
	value = readl((void *)(sunxi_cpucfg_base + CPUCFG_PWROFF_GATING_REG));
	value &= ~(1<<cpu);
	writel(value, (void *)(sunxi_cpucfg_base + CPUCFG_PWROFF_GATING_REG));
	udelay(20);
#endif

	/* de-assert core reset */
	writel(3, sunxi_cpucfg_base + CPUCFG_CPU_RST_CTRL_REG(cpu));

	/* assert DBGPWRDUP signal */
	value = readl(sunxi_cpucfg_base + CPUCFG_DBG_CTL1_REG);
	value |= (1<<cpu);
	writel(value, sunxi_cpucfg_base + CPUCFG_DBG_CTL1_REG);
}

#ifdef CONFIG_ARCH_SUN8IW10
/*
 * The cpu of SUN8IW10 can not be powered off independently.
 */
static inline void sunxi_disable_cpu(int cpu)
{
	/* do nothing */
}
#else
static inline void sunxi_disable_cpu(int cpu)
{
	unsigned int value;

	/* assert cpu core reset */
	writel(0, sunxi_cpucfg_base + CPUCFG_CPU_RST_CTRL_REG(cpu));

	/* DBGPWRDUP hold low */
	value = readl(sunxi_cpucfg_base + CPUCFG_DBG_CTL1_REG);
	value &= ~(1<<cpu);
	writel(value, sunxi_cpucfg_base + CPUCFG_DBG_CTL1_REG);

	/* power gating off */
	value = readl(sunxi_cpucfg_base + CPUCFG_PWROFF_GATING_REG);
	value |= (1<<cpu);
	writel(value, sunxi_cpucfg_base + CPUCFG_PWROFF_GATING_REG);
	udelay(20);

	/* power switch off */
	writel(0xff, sunxi_cpucfg_base + CPUCFG_PWR_SWITCH_REG(cpu));
	udelay(30);
	while (readl(sunxi_cpucfg_base + CPUCFG_PWR_SWITCH_REG(cpu)) != 0xff)
		;
}
#endif

#endif /* __PLATSMP_V1_H__ */