/* * Allwinner sun8iw6p1 SoCs pinctrl driver. * * Copyright(c) 2016-2020 Allwinnertech Co., Ltd. * Author: WimHuang * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ #include #include #include #include #include #include "pinctrl-sunxi.h" static const struct sunxi_desc_pin sun8iw6p1_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart2"), /*TX*/ SUNXI_FUNCTION(0x3, "jtag0"), /*MS0*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart2"), /*RX*/ SUNXI_FUNCTION(0x3, "jtag0"), /*CK0*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart2"), /*RTS*/ SUNXI_FUNCTION(0x3, "jtag0"), /*DO0*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart2"), /*CTS*/ SUNXI_FUNCTION(0x3, "jtag0"), /*DI0*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s0"), /*LRCK*/ SUNXI_FUNCTION(0x3, "tdm0"), /*LRCK*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s0"), /*BCLK*/ SUNXI_FUNCTION(0x3, "tdm0"), /*BCLK*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s0"), /*DOUT*/ SUNXI_FUNCTION(0x3, "tdm0"), /*DOUT*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s0"), /*DIN*/ SUNXI_FUNCTION(0x3, "tdm0"), /*DIN*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s0"), /*MCLK*/ SUNXI_FUNCTION(0x3, "tdm0"), /*MCLK*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart0"), /*TX*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart0"), /*RX*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /*HOLE*/ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*WE*/ SUNXI_FUNCTION(0x3, "spi0"), /*MOSI*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*ALE*/ SUNXI_FUNCTION(0x3, "spi0"), /*MISO*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*CLE*/ SUNXI_FUNCTION(0x3, "spi0"), /*CLK*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*CE1*/ SUNXI_FUNCTION(0x3, "spi0"), /*CS*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*CE0*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*RE*/ SUNXI_FUNCTION(0x3, "sdc2"), /*CLK*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*RB0*/ SUNXI_FUNCTION(0x3, "sdc2"), /*CMD*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*RB1*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*DQ0*/ SUNXI_FUNCTION(0x3, "sdc2"), /*D0*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*DQ1*/ SUNXI_FUNCTION(0x3, "sdc2"), /*D1*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*DQ2*/ SUNXI_FUNCTION(0x3, "sdc2"), /*D2*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*DQ3*/ SUNXI_FUNCTION(0x3, "sdc2"), /*D3*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*DQ4*/ SUNXI_FUNCTION(0x3, "sdc2"), /*D4*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*DQ5*/ SUNXI_FUNCTION(0x3, "sdc2"), /*D5*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*DQ6*/ SUNXI_FUNCTION(0x3, "sdc2"), /*D6*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*DQ7*/ SUNXI_FUNCTION(0x3, "sdc2"), /*D7*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*DQS*/ SUNXI_FUNCTION(0x3, "sdc2"), /*RST*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*CE2*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*CE3*/ SUNXI_FUNCTION(0x7, "io_disabled")), /*HOLE*/ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D2*/ SUNXI_FUNCTION(0x4, "gmac0"), /**/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D3*/ SUNXI_FUNCTION(0x4, "gmac0"), /*grxd2*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D4*/ SUNXI_FUNCTION(0x4, "gmac0"), /*grxd1*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D5*/ SUNXI_FUNCTION(0x4, "gmac0"), /*grxd0*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D6*/ SUNXI_FUNCTION(0x4, "gmac0"), /*grxck*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D7*/ SUNXI_FUNCTION(0x4, "gmac0"), /*GRXCTL/ERXDV*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D10*/ SUNXI_FUNCTION(0x4, "gmac0"), /*GNULL/ERXERR*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D11*/ SUNXI_FUNCTION(0x4, "gmac0"), /*GTXD3*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D12*/ SUNXI_FUNCTION(0x4, "gmac0"), /*GTXD2*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D13*/ SUNXI_FUNCTION(0x4, "gmac0"), /*GTXD1*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D14*/ SUNXI_FUNCTION(0x4, "gmac0"), /*GTXD0*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D15*/ SUNXI_FUNCTION(0x4, "gmac0"), /*GNULL/ECRS*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D18*/ SUNXI_FUNCTION(0x3, "lvds0"), /*VP0*/ SUNXI_FUNCTION(0x4, "gmac0"), /*GTXCK/ETXCK*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D19*/ SUNXI_FUNCTION(0x3, "lvds0"), /*VN0*/ SUNXI_FUNCTION(0x4, "gmac0"), /*GTXCTL/ETXEN*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D20*/ SUNXI_FUNCTION(0x3, "lvds0"), /*VP1*/ SUNXI_FUNCTION(0x4, "gmac0"), /*GNULL/ETXERR*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D21*/ SUNXI_FUNCTION(0x3, "lvds0"), /*VN1*/ SUNXI_FUNCTION(0x4, "gmac0"), /*GCLKIN/ECOL*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D22*/ SUNXI_FUNCTION(0x3, "lvds0"), /*VP2*/ SUNXI_FUNCTION(0x4, "gmac0"), /*GMDC*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*D23*/ SUNXI_FUNCTION(0x3, "lvds0"), /*VN2*/ SUNXI_FUNCTION(0x4, "gmac0"), /*GMDIO*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*CLK*/ SUNXI_FUNCTION(0x3, "lvds0"), /*VPC*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*DE*/ SUNXI_FUNCTION(0x3, "lvds0"), /*VNC*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*HSYNC*/ SUNXI_FUNCTION(0x3, "lvds0"), /*VP3*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /*VSYNC*/ SUNXI_FUNCTION(0x3, "lvds0"), /*VN3*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "pwm0"), SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 29), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x7, "io_disabled")), /*HOLE*/ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /*PCLK*/ SUNXI_FUNCTION(0x4, "ccir0"), /*CLK*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /*MCLK*/ SUNXI_FUNCTION(0x4, "ccir0"), /*DE*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /*HSYNC*/ SUNXI_FUNCTION(0x4, "ccir0"), /*HSYNC*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /*VSYNC*/ SUNXI_FUNCTION(0x4, "ccir0"), /*VSYNC*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /*D0*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /*D1*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /*D2*/ SUNXI_FUNCTION(0x4, "ccir0"), /*D0*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /*D3*/ SUNXI_FUNCTION(0x4, "ccir0"), /*D1*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /*D4*/ SUNXI_FUNCTION(0x4, "ccir0"), /*D2*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /*D5*/ SUNXI_FUNCTION(0x4, "ccir0"), /*D3*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /*D6*/ SUNXI_FUNCTION(0x3, "uart4"), /*TX*/ SUNXI_FUNCTION(0x4, "ccir0"), /*D4*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /*D7*/ SUNXI_FUNCTION(0x3, "uart4"), /*RX*/ SUNXI_FUNCTION(0x4, "ccir0"), /*D5*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /*D8*/ SUNXI_FUNCTION(0x3, "uart4"), /*RTS*/ SUNXI_FUNCTION(0x4, "ccir0"), /*D6*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /*D9*/ SUNXI_FUNCTION(0x3, "uart4"), /*CTS*/ SUNXI_FUNCTION(0x4, "ccir0"), /*D7*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /*SCK*/ SUNXI_FUNCTION(0x3, "twi2"), /*SCK*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /*SDA*/ SUNXI_FUNCTION(0x3, "twi2"), /*SDA*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x3, "spdif0"), /*DOUT*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x7, "io_disabled")), /*HOLE*/ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc0"), /*D1*/ SUNXI_FUNCTION(0x3, "jtag0"), /*MS1*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc0"), /*D0*/ SUNXI_FUNCTION(0x3, "jtag0"), /*DI1*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc0"), /*CLK*/ SUNXI_FUNCTION(0x3, "uart0"), /*TX*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc0"), /*CMD*/ SUNXI_FUNCTION(0x3, "jtag0"), /*DO1*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc0"), /*D3*/ SUNXI_FUNCTION(0x3, "uart0"), /*RX*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc0"), /*D2*/ SUNXI_FUNCTION(0x3, "jtag0"), /*CK1*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x7, "io_disabled")), /*HOLE*/ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /*CLK*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /*CMD*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /*D0*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /*D1*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /*D2*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /*D3*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart1"), /*TX*/ SUNXI_FUNCTION(0x3, "spi1"), /*CS*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart1"), /*RX*/ SUNXI_FUNCTION(0x3, "spi1"), /*CLK*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart1"), /*RTS*/ SUNXI_FUNCTION(0x3, "spi1"), /*DOUT*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart1"), /*CTS*/ SUNXI_FUNCTION(0x3, "spi1"), /*DIN*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s1"), /*BCLK*/ SUNXI_FUNCTION(0x3, "uart3"), /*TX*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s1"), /*LRCK*/ SUNXI_FUNCTION(0x3, "uart3"), /*RX*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s1"), /*DOUT*/ SUNXI_FUNCTION(0x3, "uart3"), /*RTS*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "i2s1"), /*DIN*/ SUNXI_FUNCTION(0x3, "uart3"), /*CTS*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /*HOLE*/ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "twi0"), /*SCK*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "twi0"), /*SDA*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "twi1"), /*SCK*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "twi1"), /*SDA*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "twi2"), /*SCK*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "twi2"), /*SDA*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "hdmi"), SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "hdmi"), SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "hdmi"), SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x5, "Vdevice"), /* virtual */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x5, "Vdevice"), /* virtual */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), }; static const unsigned sun8iw6p1_irq_bank_base[] = {0, 0, 0}; static const struct sunxi_pinctrl_desc sun8iw6p1_pinctrl_data = { .pins = sun8iw6p1_pins, .npins = ARRAY_SIZE(sun8iw6p1_pins), .pin_base = 0, .irq_banks = 3, .irq_bank_base = sun8iw6p1_irq_bank_base, }; static int sun8iw6p1_pinctrl_probe(struct platform_device *pdev) { return sunxi_pinctrl_init(pdev, &sun8iw6p1_pinctrl_data); } static const struct of_device_id sun8iw6p1_pinctrl_match[] = { { .compatible = "allwinner,sun8iw6p1-pinctrl", }, {} }; MODULE_DEVICE_TABLE(of, sun8iw6p1_pinctrl_match); static struct platform_driver sun8iw6p1_pinctrl_driver = { .probe = sun8iw6p1_pinctrl_probe, .driver = { .name = "sun8iw6p1-pinctrl", .owner = THIS_MODULE, .of_match_table = sun8iw6p1_pinctrl_match, }, }; static int __init sun8iw6p1_pio_init(void) { int ret; ret = platform_driver_register(&sun8iw6p1_pinctrl_driver); if (IS_ERR_VALUE(ret)) { pr_err("register sun8iw6p1 pio controller failed\n"); return -EINVAL; } return 0; } postcore_initcall(sun8iw6p1_pio_init); MODULE_AUTHOR("WimHuang"); MODULE_DESCRIPTION("Allwinner sun8iw6p1 pio pinctrl driver"); MODULE_LICENSE("GPL");