/* * Driver for ADAU1761 codec * * Copyright: (C) 2017 NetEase(Hangzhou) Network Co., Ltd. * All rights reserved. * * Licensed under the GPL-2 or later. */ #define DEBUG #ifdef DEBUG #define DSP_DEBUG(...) \ do { \ printk("[ADAU1761]: "__VA_ARGS__); \ } while (0) #else #define DSP_DEBUG(...) #endif #include #include #include #include /* guess what */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* For put_user and get_user */ #include #define SIGMA_MAGIC "ADISIGM" #define ADAU1761_FIRMWARE "adau1761.bin" struct sigma_firmware_header { unsigned char magic[7]; u8 version; __le32 crc; } __packed; struct sigma_samprate_list { __le32 samplist_len; __le32 samplist_ind; __le32 zeros; __le32 sample_rate; } __packed; enum { SIGMA_ACTION_WRITEXBYTES = 0, SIGMA_ACTION_CONTROL, SIGMA_ACTION_END, }; struct sigma_action { __le32 len; // data chunk length __le32 ind; // data to load, or control address? __le32 mask; // do not care } __packed; struct sigma_firmware { const struct firmware *fw; size_t pos; void *control_data; }; #define ADAU1761_DIGMIC_JACKDETECT 0x4008 #define ADAU1761_REC_MIXER_LEFT0 0x400A #define ADAU1761_REC_MIXER_LEFT1 0x400B #define ADAU1761_REC_MIXER_RIGHT0 0x400C #define ADAU1761_REC_MIXER_RIGHT1 0x400D #define ADAU1761_LEFT_DIFF_INPUT_VOL 0x400E #define ADAU1761_RIGHT_DIFF_INPUT_VOL 0x400F #define ADAU1761_PLAY_LR_MIXER_LEFT 0x4020 #define ADAU1761_PLAY_MIXER_LEFT0 0x401C #define ADAU1761_PLAY_MIXER_LEFT1 0x401D #define ADAU1761_PLAY_MIXER_RIGHT0 0x401E #define ADAU1761_PLAY_MIXER_RIGHT1 0x401F #define ADAU1761_PLAY_LR_MIXER_RIGHT 0x4021 #define ADAU1761_PLAY_MIXER_MONO 0x4022 #define ADAU1761_PLAY_HP_LEFT_VOL 0x4023 #define ADAU1761_PLAY_HP_RIGHT_VOL 0x4024 #define ADAU1761_PLAY_LINE_LEFT_VOL 0x4025 #define ADAU1761_PLAY_LINE_RIGHT_VOL 0x4026 #define ADAU1761_PLAY_MONO_OUTPUT_VOL 0x4027 #define ADAU1761_POP_CLICK_SUPPRESS 0x4028 #define ADAU1761_JACK_DETECT_PIN 0x4031 #define ADAU1761_DEJITTER 0x4036 #define ADAU1761_CLK_ENABLE0 0x40F9 #define ADAU1761_CLK_ENABLE1 0x40FA /* 17x1 common registers */ #define ADAU17X1_CLOCK_CONTROL 0x4000 #define ADAU17X1_PLL_CONTROL 0x4002 #define ADAU17X1_REC_POWER_MGMT 0x4009 #define ADAU17X1_MICBIAS 0x4010 #define ADAU17X1_SERIAL_PORT0 0x4015 #define ADAU17X1_SERIAL_PORT1 0x4016 #define ADAU17X1_CONVERTER0 0x4017 #define ADAU17X1_CONVERTER1 0x4018 #define ADAU17X1_LEFT_INPUT_DIGITAL_VOL 0x401A #define ADAU17X1_RIGHT_INPUT_DIGITAL_VOL 0x401B #define ADAU17X1_ADC_CONTROL 0x4019 #define ADAU17X1_PLAY_POWER_MGMT 0x4029 #define ADAU17X1_DAC_CONTROL0 0x402A #define ADAU17X1_DAC_CONTROL1 0x402B #define ADAU17X1_DAC_CONTROL2 0x402C #define ADAU17X1_SERIAL_PORT_PAD 0x402D #define ADAU17X1_CONTROL_PORT_PAD0 0x402F #define ADAU17X1_CONTROL_PORT_PAD1 0x4030 #define ADAU17X1_DSP_SAMPLING_RATE 0x40EB #define ADAU17X1_SERIAL_INPUT_ROUTE 0x40F2 #define ADAU17X1_SERIAL_OUTPUT_ROUTE 0x40F3 #define ADAU17X1_DSP_ENABLE 0x40F5 #define ADAU17X1_DSP_RUN 0x40F6 #define ADAU17X1_SERIAL_SAMPLING_RATE 0x40F8 #define ADAU17X1_SERIAL_PORT0_BCLK_POL BIT(4) #define ADAU17X1_SERIAL_PORT0_LRCLK_POL BIT(3) #define ADAU17X1_SERIAL_PORT0_MASTER BIT(0) #define ADAU17X1_SERIAL_PORT1_DELAY1 0x00 #define ADAU17X1_SERIAL_PORT1_DELAY0 0x01 #define ADAU17X1_SERIAL_PORT1_DELAY8 0x02 #define ADAU17X1_SERIAL_PORT1_DELAY16 0x03 #define ADAU17X1_SERIAL_PORT1_DELAY_MASK 0x03 #define ADAU17X1_CLOCK_CONTROL_INFREQ_MASK 0x6 #define ADAU17X1_CLOCK_CONTROL_CORECLK_SRC_PLL BIT(3) #define ADAU17X1_CLOCK_CONTROL_SYSCLK_EN BIT(0) #define ADAU17X1_SERIAL_PORT1_BCLK64 (0x0 << 5) #define ADAU17X1_SERIAL_PORT1_BCLK32 (0x1 << 5) #define ADAU17X1_SERIAL_PORT1_BCLK48 (0x2 << 5) #define ADAU17X1_SERIAL_PORT1_BCLK128 (0x3 << 5) #define ADAU17X1_SERIAL_PORT1_BCLK256 (0x4 << 5) #define ADAU17X1_SERIAL_PORT1_BCLK_MASK (0x7 << 5) #define ADAU17X1_SERIAL_PORT0_STEREO (0x0 << 1) #define ADAU17X1_SERIAL_PORT0_TDM4 (0x1 << 1) #define ADAU17X1_SERIAL_PORT0_TDM8 (0x2 << 1) #define ADAU17X1_SERIAL_PORT0_TDM_MASK (0x3 << 1) #define ADAU17X1_SERIAL_PORT0_PULSE_MODE BIT(5) #define ADAU17X1_CONVERTER0_DAC_PAIR(x) (((x)-1) << 5) #define ADAU17X1_CONVERTER0_DAC_PAIR_MASK (0x3 << 5) #define ADAU17X1_CONVERTER1_ADC_PAIR(x) ((x)-1) #define ADAU17X1_CONVERTER1_ADC_PAIR_MASK 0x3 #define ADAU17X1_CONVERTER0_CONVSR_MASK 0x7 #define ADAU1761_DATA_PARAM_START_ADDR (0x0000) #define ADAU1761_DATA_PARAM_END_ADDR (0x03FF) #define ADAU1761_DATA_PARAM_WORD_LEN (4) #define ADAU1761_PROG_PARAM_START_ADDR (0x0800) #define ADAU1761_PROG_PARAM_END_ADDR (0x0BFF) #define ADAU1761_PROG_PARAM_WORD_LEN (5) #define ADAU1761_DEF_VOL_STEP (20) #define VOL_CTL_ADDR (0x0009) #define SRC_SW_ADDR (0x0008) /* safeload registers */ #define SAFE_LOAD_DATA_1_REG (0x0001) #define SAFE_LOAD_TARGET_ADDR_REG (0x0006) #define SAFE_LOAD_WORD_NUM_REG (0x0007) #define SAFE_LOAD_REG_NUM (SAFE_LOAD_WORD_NUM_REG - SAFE_LOAD_DATA_1_REG + 1) #define SAFE_LOAD_WORD_NUM_MAX (5) #define ADAU1761_DATA_COUNT (4) #define SAFE_LOAD_EQ_SWITCH_REG (0x0047) const unsigned char adau1761_init_arr_00[] = { 0x40, 0xEB, /* (0) IC 1.Sample Rate Setting */ 0x7F }; const unsigned char adau1761_init_arr_01[] = { 0x40, 0xF6, /* (1) IC 1.DSP Run Register */ 0x00, }; const unsigned char adau1761_init_arr_02[] = { 0x40, 0x00, /* (2) IC 1.Clock Control Register */ 0x0F, }; const unsigned char adau1761_init_arr_03[] = { 0x40, 0x02, /* (3) IC 1.PLL Control Register */ 0x00, 0x01, 0x00, 0x00, 0x20, 0x03, }; const unsigned char adau1761_init_arr_04[] = { // 0x00, 0x00, /* (4) IC 1.Delay */ // 0x00, 0x64, }; const unsigned char adau1761_init_arr_05[] = { 0x40, 0x15, /* (5) IC 1.Serial Port Control Registers */ 0x00, 0x00, }; const unsigned char adau1761_init_arr_06[] = { 0x40, 0x11, /* (6) IC 1.ALC Control Registers */ 0x00, 0x00, 0x00, 0x00, }; const unsigned char adau1761_init_arr_07[] = { 0x40, 0x08, /* (7) IC 1.Microphone Control Register */ 0x00, }; const unsigned char adau1761_init_arr_08[] = { 0x40, 0x09, /* (8) IC 1.Record Input Signal Path Registers */ 0x00, 0x0B, 0x00, 0x0B, 0x00, 0x00, 0x00, 0x00, }; const unsigned char adau1761_init_arr_09[] = { 0x40, 0x19, /* (9) IC 1.ADC Control Registers */ 0x13, 0x00, 0x00, }; const unsigned char adau1761_init_arr_10[] = { 0x40, 0x1C, /* (10) IC 1.Playback Output Signal Path Registers */ 0x21, 0x00, 0x41, 0x00, 0x03, 0x09, 0x00, 0xE5, 0xE5, 0xE6, 0xE6, 0xE5, 0x00, 0x03, }; const unsigned char adau1761_init_arr_11[] = { 0x40, 0x17, /* (11) IC 1.Converter Control Registers */ 0x00, 0x00, }; const unsigned char adau1761_init_arr_12[] = { 0x40, 0x2A, /* (12) IC 1.DAC Control Registers */ 0x03, 0x00, 0x00, }; const unsigned char adau1761_init_arr_13[] = { 0x40, 0x2D, /* (13) IC 1.Serial Port Pad Control Registers */ 0xAA, }; const unsigned char adau1761_init_arr_14[] = { 0x40, 0x2F, /* (14) IC 1.Communication Port Pad Control Registers */ 0xAA, 0x00, }; const unsigned char adau1761_init_arr_15[] = { 0x40, 0x31, /* (15) IC 1.Jack Detect Pad Control Register */ 0x08, }; const unsigned char adau1761_init_arr_16[] = { 0x08, 0x00, /* (16) Program Clear Block 0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; const unsigned char adau1761_init_arr_20[] = { 0x0B, 0xFC, /* (20) Program Clear Block 4 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; const unsigned char adau1761_init_arr_21[] = { 0x40, 0xF5, /* (21) IC 1.DSP ON Register */ 0x01, }; const unsigned char adau1761_init_arr_22[] = { 0x40, 0xC0, /* (22) IC 1.CRC Registers */ 0x00, 0x7F, 0x7C, 0x7F, 0x01, }; const unsigned char adau1761_init_arr_23[] = { 0x40, 0xC6, /* (23) IC 1.GPIO Registers */ 0x00, 0x00, 0x00, 0x00, }; const unsigned char adau1761_init_arr_24[] = { 0x40, 0xE9, /* (24) IC 1.Non Modulo Registers */ 0x0F, 0xFC, }; const unsigned char adau1761_init_arr_25[] = { 0x40, 0xD0, /* (25) IC 1.Watchdog Registers */ 0x00, 0x04, 0x00, 0x00, 0x00, }; const unsigned char adau1761_init_arr_26[] = { 0x40, 0xEB, /* (26) IC 1.Sampling Rate Setting Register */ 0x7F, }; const unsigned char adau1761_init_arr_27[] = { 0x40, 0xF2, /* (27) IC 1.Routing Matrix Inputs Register */ 0x00, }; const unsigned char adau1761_init_arr_28[] = { 0x40, 0xF3, /* (28) IC 1.Routing Matrix Outputs Register */ 0x00, }; const unsigned char adau1761_init_arr_29[] = { 0x40, 0xF4, /* (29) IC 1.Serial Data Configuration Register */ 0x00, }; const unsigned char adau1761_init_arr_30[] = { 0x40, 0xF7, /* (30) IC 1.DSP Slew Mode Register */ 0x00, }; const unsigned char adau1761_init_arr_31[] = { 0x40, 0xF8, /* (31) IC 1.Serial Port Sample Rate Register */ 0x00, }; const unsigned char adau1761_init_arr_32[] = { 0x40, 0xF9, /* (32) IC 1.Clock Enable Registers */ 0x7F, 0x03, }; const unsigned char adau1761_init_arr_33[] = { 0x08, 0x00, /* (33) Program Data */ 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xE0, 0x00, 0x00, 0x00, 0xFF, 0x34, 0x00, 0x00, 0x00, 0xFF, 0x2C, 0x00, 0x00, 0x00, 0xFF, 0x54, 0x00, 0x00, 0x00, 0xFF, 0x5C, 0x00, 0x00, 0x00, 0xFF, 0xF5, 0x08, 0x20, 0x00, 0xFF, 0x38, 0x00, 0x00, 0x00, 0xFF, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x99, 0x28, 0x22, 0x00, 0x09, 0xD8, 0x00, 0xE2, 0x00, 0x09, 0xF0, 0x00, 0xF2, 0x00, 0x09, 0xD9, 0x2B, 0x20, 0x00, 0x09, 0xF8, 0x00, 0xE2, 0x00, 0x09, 0x4D, 0x08, 0x20, 0x00, 0xFD, 0xB0, 0x00, 0xE2, 0x00, 0x09, 0xFD, 0x08, 0x20, 0x00, 0xFD, 0xB8, 0x00, 0xE2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xC0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; const unsigned char adau1761_init_arr_34[] = { 0x00, 0x00, /* (34) Param */ 0x00, 0x00, 0x0F, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x87, 0x95, 0xA0, 0x00, 0x00, 0x08, 0x00, 0x00, 0x80, 0x00, 0x00, 0x0F, 0x02, 0x67, 0x53, 0x00, 0x7D, 0xA0, 0xAF, 0x00, 0xFD, 0x98, 0xAD, 0x0F, 0x82, 0x5F, 0x51, 0x00, 0x80, 0x00, 0x00, 0x0F, 0x80, 0x9E, 0x3D, 0x00, 0x34, 0x25, 0x2B, 0x00, 0x7F, 0x61, 0xC3, 0x0F, 0xCB, 0xDA, 0xD5, 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0x00, 0x80, 0x1D, 0x97, 0x0F, 0x00, 0xEC, 0x9F, 0x00, 0x7E, 0xFD, 0xD9, 0x00, 0xFF, 0x13, 0x61, 0x0F, 0x80, 0xE4, 0x90, 0x00, 0x80, 0x50, 0x64, 0x0F, 0x00, 0xA5, 0x22, 0x00, 0x7F, 0x0E, 0x0F, 0x00, 0xFF, 0x5A, 0xDE, 0x0F, 0x80, 0xA1, 0x8D, 0x00, 0x80, 0x8B, 0x50, 0x0F, 0x06, 0x4F, 0x3C, 0x00, 0x79, 0xAE, 0x9C, 0x00, 0xF9, 0xB0, 0xC4, 0x0F, 0x85, 0xC6, 0x15, 0x00, 0x80, 0x7E, 0xBB, 0x0F, 0x03, 0xF8, 0x4B, 0x00, 0x7B, 0xAE, 0x5C, 0x00, 0xFC, 0x07, 0xB5, 0x0F, 0x83, 0xD2, 0xE9, 0x00, 0x99, 0x7D, 0xD0, 0x0F, 0xA2, 0x18, 0x34, 0x00, 0x3A, 0xCB, 0x2A, 0x00, 0x37, 0x9D, 0x8E, 0x0F, 0xD2, 0x01, 0x44, 0x00, 0x7D, 0x06, 0xB4, 0x0F, 0x35, 0xAB, 0x24, 0x00, 0x66, 0x0E, 0x45, 0x00, 0xCA, 0x54, 0xDC, 0x0F, 0x9C, 0xEB, 0x07, 0x00, 0x84, 0xFA, 0x80, 0x0F, 0x7B, 0x91, 0x2F, 0x00, 0x54, 0x90, 0xF6, 0x00, 0x84, 0x6E, 0xD1, 0x0F, 0xA6, 0x74, 0x89, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x94, 0xC5, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x94, 0xC5, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x74, 0xA8, 0xB6, 0x00, 0x5F, 0x3E, 0x5E, 0x00, 0x47, 0x4B, 0xE9, 0x00, 0x32, 0xF5, 0x1E, 0x00, 0x24, 0x13, 0x47, 0x00, 0x19, 0x82, 0x54, 0x00, 0x12, 0x09, 0xA3, 0x00, 0x0C, 0xC1, 0x2A, 0x00, 0x09, 0x04, 0xD2, 0x00, 0x06, 0x60, 0x95, 0x00, 0x04, 0x82, 0x69, 0x00, 0x00, 0x01, 0x6A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x51, 0xEC, 0x0F, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x74, 0xA8, 0xB6, 0x00, 0x5F, 0x3E, 0x5E, 0x00, 0x47, 0x4B, 0xE9, 0x00, 0x32, 0xF5, 0x1E, 0x00, 0x24, 0x13, 0x47, 0x00, 0x19, 0x82, 0x54, 0x00, 0x12, 0x09, 0xA3, 0x00, 0x0C, 0xC1, 0x2A, 0x00, 0x09, 0x04, 0xD2, 0x00, 0x06, 0x60, 0x95, 0x00, 0x04, 0x82, 0x69, 0x00, 0x00, 0x1B, 0x5D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9E, 0x00, 0x00, 0x51, 0xEC, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x72, 0x15, 0x9E, 0x00, 0x5D, 0x53, 0xC3, 0x00, 0x46, 0x9A, 0xB6, 0x00, 0x32, 0xEA, 0xCB, 0x00, 0x24, 0x13, 0x47, 0x00, 0x19, 0x8A, 0x13, 0x00, 0x12, 0x14, 0x9A, 0x00, 0x0C, 0xC8, 0xEB, 0x00, 0x09, 0x0A, 0x4D, 0x00, 0x06, 0x64, 0x75, 0x00, 0x04, 0x85, 0x27, 0x00, 0x03, 0x32, 0x3B, 0x00, 0x02, 0x42, 0x93, 0x00, 0x01, 0x12, 0x2E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x8B, 0x00, 0x00, 0x51, 0xEC, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, }; const unsigned char adau1761_init_arr_35[] = { 0x1F, 0xFC, /* (35) Non Modulo RAM */ 0x00, 0x7F, 0xF2, 0x59, 0x00, 0x00, 0x0D, 0xA7, 0x00, 0x7F, 0xF2, 0x59, 0x00, 0x00, 0x0D, 0xA7, }; const unsigned char adau1761_init_arr_36[] = { 0x40, 0xEB, /* (36) IC 1.Sample Rate Setting */ 0x01, }; const unsigned char adau1761_init_arr_37[] = { 0x40, 0xF6, /* (37) IC 1.DSP Run Register */ 0x01, }; const unsigned char adau1761_init_arr_38[] = { 0x40, 0x36, /* (38) IC 1.Dejitter Register Control */ 0x00, }; const unsigned char adau1761_init_arr_39[] = { 0x40, 0x36, /* (39) IC 1.Dejitter Register Control */ 0x03, }; typedef struct { const unsigned char *p_arr; unsigned int byte_len; } adau1761_init_matrix; const adau1761_init_matrix adau1761_init_matrix_arr[] = { {adau1761_init_arr_00, sizeof(adau1761_init_arr_00)}, {adau1761_init_arr_01, sizeof(adau1761_init_arr_01)}, {adau1761_init_arr_02, sizeof(adau1761_init_arr_02)}, {adau1761_init_arr_03, sizeof(adau1761_init_arr_03)}, {adau1761_init_arr_04, sizeof(adau1761_init_arr_04)}, {adau1761_init_arr_05, sizeof(adau1761_init_arr_05)}, {adau1761_init_arr_06, sizeof(adau1761_init_arr_06)}, {adau1761_init_arr_07, sizeof(adau1761_init_arr_07)}, {adau1761_init_arr_08, sizeof(adau1761_init_arr_08)}, {adau1761_init_arr_09, sizeof(adau1761_init_arr_09)}, {adau1761_init_arr_10, sizeof(adau1761_init_arr_10)}, {adau1761_init_arr_11, sizeof(adau1761_init_arr_11)}, {adau1761_init_arr_12, sizeof(adau1761_init_arr_12)}, {adau1761_init_arr_13, sizeof(adau1761_init_arr_13)}, {adau1761_init_arr_14, sizeof(adau1761_init_arr_14)}, {adau1761_init_arr_15, sizeof(adau1761_init_arr_15)}, {adau1761_init_arr_16, sizeof(adau1761_init_arr_16)}, {adau1761_init_arr_17, sizeof(adau1761_init_arr_17)}, {adau1761_init_arr_18, sizeof(adau1761_init_arr_18)}, {adau1761_init_arr_19, sizeof(adau1761_init_arr_19)}, {adau1761_init_arr_20, sizeof(adau1761_init_arr_20)}, {adau1761_init_arr_21, sizeof(adau1761_init_arr_21)}, {adau1761_init_arr_22, sizeof(adau1761_init_arr_22)}, {adau1761_init_arr_23, sizeof(adau1761_init_arr_23)}, {adau1761_init_arr_24, sizeof(adau1761_init_arr_24)}, {adau1761_init_arr_25, sizeof(adau1761_init_arr_25)}, {adau1761_init_arr_26, sizeof(adau1761_init_arr_26)}, {adau1761_init_arr_27, sizeof(adau1761_init_arr_27)}, {adau1761_init_arr_28, sizeof(adau1761_init_arr_28)}, {adau1761_init_arr_29, sizeof(adau1761_init_arr_29)}, {adau1761_init_arr_30, sizeof(adau1761_init_arr_30)}, {adau1761_init_arr_31, sizeof(adau1761_init_arr_31)}, {adau1761_init_arr_32, sizeof(adau1761_init_arr_32)}, {adau1761_init_arr_33, sizeof(adau1761_init_arr_33)}, {adau1761_init_arr_34, sizeof(adau1761_init_arr_34)}, {adau1761_init_arr_35, sizeof(adau1761_init_arr_35)}, {adau1761_init_arr_36, sizeof(adau1761_init_arr_36)}, {adau1761_init_arr_37, sizeof(adau1761_init_arr_37)}, {adau1761_init_arr_38, sizeof(adau1761_init_arr_38)}, {adau1761_init_arr_39, sizeof(adau1761_init_arr_39)}}; #define ADAU1761_INIT_ARR_COUNT \ (sizeof(adau1761_init_matrix_arr) / sizeof(adau1761_init_matrix)) struct vol_table { int vtable_step; float volgain_db; uint8_t ram_word[4]; }; /* 2dB step */ static const struct vol_table adau1761_vol_table[] = { {20, 0, {0x00, 0x80, 0x00, 0x00}}, {19, -1, {0x00, 0x72, 0x14, 0x7B}}, {18, -2, {0x00, 0x65, 0xAC, 0x8C}}, {17, -3, {0x00, 0x5A, 0x9D, 0xF8}}, {16, -4, {0x00, 0x50, 0xC3, 0x36}}, {15, -6, {0x00, 0x40, 0x26, 0xE7}}, {14, -8, {0x00, 0x32, 0xF5, 0x2D}}, {13, -10, {0x00, 0x28, 0x7A, 0x27}}, {12, -12, {0x00, 0x20, 0x26, 0xF3}}, {11, -14, {0x00, 0x19, 0x8A, 0x13}}, {10, -16, {0x00, 0x14, 0x49, 0x61}}, {9, -20, {0x00, 0x0C, 0xCC, 0xCD}}, {8, -24, {0x00, 0x08, 0x13, 0x85}}, {7, -28, {0x00, 0x05, 0x5E, 0x7F}}, {6, -32, {0x00, 0x03, 0x37, 0x18}}, {5, -36, {0x00, 0x02, 0x07, 0x56}}, {4, -40, {0x00, 0x01, 0x47, 0xAE}}, {3, -44, {0x00, 0x00, 0xCE, 0xC1}}, {2, -52, {0x00, 0x00, 0x52, 0x4F}}, {1, -60, {0x00, 0x00, 0x20, 0xC5}}, {0, -80, {0x00, 0x00, 0x03, 0x47}}, }; #define VOL_STEP_NUM (sizeof(adau1761_vol_table) / sizeof(struct vol_table)) #define MAX_VOL_STEP (VOL_STEP_NUM - 1) const u8 src_analog_arr[] = {0x00, 0x00, 0x00, 0x00}; const u8 src_dig_arr[] = {0x00, 0x00, 0x00, 0x01}; const unsigned char adau1761_eq1_normal[] = {0x00, 0x00, 0x00, 0x00}; const unsigned char adau1761_eq1_decrease[] = {0x00, 0x00, 0x00, 0x01}; const unsigned char adau1761_eq2_improve[] = {0x00, 0x00, 0x00, 0x02}; // io commands #define MAGIC_NUM 'A' #define ADAU1761_CMD_VOL_SET _IOW(MAGIC_NUM, 0, int) #define ADAU1761_CMD_VOL_GET _IOR(MAGIC_NUM, 1, int) #define ADAU1761_CMD_AMP_MUTE_SET _IOW(MAGIC_NUM, 2, int) #define ADAU1761_CMD_AMP_MUTE_GET _IOR(MAGIC_NUM, 3, int) #define ADAU1761_CMD_SRC_SET _IOW(MAGIC_NUM, 4, int) #define ADAU1761_CMD_SRC_GET _IOR(MAGIC_NUM, 5, int) #define ADAU1761_CMD_FW_LOAD _IOW(MAGIC_NUM, 6, int) #define ADAU1761_CMD_EQ_SET _IOW(MAGIC_NUM, 7, int) #define ADAU1761_CMD_MAX (7) struct adau1761_priv_data { struct i2c_client *i2c_client; u8 i2c_ch; u8 vol; u8 is_mute; u8 src; // 0-analog, 1-i2s }; static int default_pwm_freq = 24576000; // 24.576 default static struct pwm_device *pwm_dev[2]; static int duty_ns; static int period_ns; static int polarity = 0; /*for pa sdz gpio ctrl*/ static int pa_sdz_item; /*for pa mute gpio ctrl*/ static int pa_mute_item; static DEFINE_MUTEX(adau1761_mutex); static struct adau1761_priv_data adau1761_priv; static inline u32 sigma_action_len(struct sigma_action *sa) { return (le32_to_cpu(sa->len)); } static size_t sigma_action_size(struct sigma_action *sa) { size_t payload = 0; switch (le32_to_cpu(sa->ind)) { case SIGMA_ACTION_WRITEXBYTES: case SIGMA_ACTION_CONTROL: payload = sigma_action_len(sa); break; default: break; } return payload; } /* * Returns a negative error value in case of an error, 0 if processing of * the firmware should be stopped after this action, 1 otherwise. */ static int process_sigma_action(struct sigma_firmware *ssfw, struct sigma_action *sa) { size_t len = sigma_action_len(sa); u16 addr; int ret; DSP_DEBUG("%s: len:%d ind:%#x\n", __func__, len, le32_to_cpu(sa->ind)); switch (le32_to_cpu(sa->ind)) { case SIGMA_ACTION_WRITEXBYTES: if (len <= sizeof(struct sigma_action) + 2) { pr_debug("%s: short length in SIGMA_ACTION_WRITEXBYTES!\n", __func__); return -EINVAL; } len = len - sizeof(struct sigma_action); addr = *(const u16 *)(ssfw->fw->data + ssfw->pos + sizeof(struct sigma_action)); DSP_DEBUG("%s: addr:%#x\n", __func__, addr); if ((addr == 0) && (len == 4)) { msleep(100); } else { ret = i2c_master_send(adau1761_priv.i2c_client, (const char *)(ssfw->fw->data + ssfw->pos + sizeof(struct sigma_action)), len); if (ret < 0) return -EINVAL; } break; case SIGMA_ACTION_CONTROL: return 0; default: return -EINVAL; } return 1; } static int process_sigma_actions(struct sigma_firmware *ssfw) { struct sigma_action *sa; size_t size; int ret; while (ssfw->pos < ssfw->fw->size) { sa = (struct sigma_action *)(ssfw->fw->data + ssfw->pos); size = sigma_action_size(sa); if (size == 0) break; ret = process_sigma_action(ssfw, sa); DSP_DEBUG("%s: action returned %i\n", __func__, ret); if (ret <= 0) return ret; size = ALIGN(size, 4); ssfw->pos += size; } return 0; } static int _process_sigma_firmware(struct device *dev, struct sigma_firmware *ssfw, const char *name) { int ret; struct sigma_firmware_header *ssfw_head; const struct firmware *fw; u32 crc; DSP_DEBUG("%s: loading firmware %s\n", __func__, name); /* first load the blob */ ret = request_firmware(&fw, name, dev); if (ret) { pr_debug("%s: request_firmware() failed with %i\n", __func__, ret); return ret; } ssfw->fw = fw; /* then verify the header */ ret = -EINVAL; /* * Reject too small or unreasonable large files. The upper limit has been * chosen a bit arbitrarily, but it should be enough for all practical * purposes and having the limit makes it easier to avoid integer * overflows later in the loading process. */ if (fw->size < sizeof(*ssfw_head) || fw->size >= 0x4000000) { dev_err(dev, "Failed to load firmware: Invalid size\n"); goto done; } ssfw_head = (void *)fw->data; if (memcmp(ssfw_head->magic, SIGMA_MAGIC, ARRAY_SIZE(ssfw_head->magic))) { dev_err(dev, "Failed to load firmware: Invalid magic\n"); goto done; } crc = crc32(0, fw->data + sizeof(*ssfw_head), fw->size - sizeof(*ssfw_head)); DSP_DEBUG("%s: crc=%x\n", __func__, crc); if (crc != le32_to_cpu(ssfw_head->crc)) { dev_err( dev, "Failed to load firmware: Wrong crc checksum: expected %x got %x\n", le32_to_cpu(ssfw_head->crc), crc); goto done; } ssfw->pos = sizeof(*ssfw_head) + sizeof(struct sigma_samprate_list); /* finally process all of the actions */ ret = process_sigma_actions(ssfw); done: release_firmware(fw); DSP_DEBUG("%s: loaded %s\n", __func__, name); return ret; } int process_sigma_firmware(struct i2c_client *client, const char *name) { struct sigma_firmware ssfw; ssfw.control_data = client; return _process_sigma_firmware(&client->dev, &ssfw, name); } static void pwm_init(int pwm_ch) { char pwm_name[10]; sprintf(pwm_name, "pwm_%d", pwm_ch); pwm_dev[pwm_ch] = pwm_request(pwm_ch, pwm_name); if (NULL == pwm_dev[pwm_ch] || IS_ERR(pwm_dev[pwm_ch])) { DSP_DEBUG("OSAL_Pwm_request pwm fail!\n"); } pwm_set_polarity(pwm_dev[pwm_ch], polarity); period_ns = 1000000000 / default_pwm_freq; duty_ns = (128 * period_ns) / 256; pwm_config(pwm_dev[pwm_ch], duty_ns, period_ns); } static int adau1761_safe_load(uint8_t *word_arr, unsigned int word_num, unsigned int target_addr) { uint8_t temp_arr[SAFE_LOAD_REG_NUM * 4 + 2]; int cnt, ret = 0; if (word_num > SAFE_LOAD_WORD_NUM_MAX) { DSP_DEBUG("safe_load: > 5 words!\n"); ret = -1; return ret; } if (word_arr == NULL) { DSP_DEBUG("safe_load: word_arr == NULL!\n"); ret = -1; return ret; } if (target_addr < 1) { DSP_DEBUG("safe_load: target_addr < 1!\n"); ret = -1; return ret; } /* fill with zero */ memset(temp_arr, 0, sizeof(temp_arr)); /* safeload register */ temp_arr[0] = (uint8_t)((SAFE_LOAD_DATA_1_REG >> 8) & 0xFF); temp_arr[1] = (uint8_t)(SAFE_LOAD_DATA_1_REG & 0xFF); /* fill with data */ for (cnt = 0; cnt < word_num * 4; cnt++) { temp_arr[cnt + 2] = word_arr[cnt]; } /* target addr */ cnt = (SAFE_LOAD_TARGET_ADDR_REG - SAFE_LOAD_DATA_1_REG) * 4 + 4; target_addr = target_addr - 1; temp_arr[cnt] = (unsigned char)((target_addr >> 8) & 0xFF); cnt++; temp_arr[cnt] = (unsigned char)(target_addr & 0xFF); /* word number */ cnt = (SAFE_LOAD_WORD_NUM_REG - SAFE_LOAD_DATA_1_REG) * 4 + 5; temp_arr[cnt] = (unsigned char)(word_num & 0xFF); /* burst transfer */ cnt = SAFE_LOAD_REG_NUM * 4 + 2; ret = i2c_master_send(adau1761_priv.i2c_client, (const char *)temp_arr, cnt); return ret; } /* * Change EQ when system operating * input: int arg * output: int ret */ static int adau1761_safe_load_new_eq(unsigned long arg) { unsigned int i; int ret = -1; gpio_set_value(pa_mute_item, 1); if (arg == 0) { ret = adau1761_safe_load((uint8_t *)(&adau1761_eq1_normal[0]), 1, SAFE_LOAD_EQ_SWITCH_REG); } else if (arg == 1) { ret = adau1761_safe_load((uint8_t *)(&adau1761_eq1_decrease[0]), 1, SAFE_LOAD_EQ_SWITCH_REG); } else if (arg == 2) { ret = adau1761_safe_load((uint8_t *)(&adau1761_eq2_improve[0]), 1, SAFE_LOAD_EQ_SWITCH_REG); } else { DSP_DEBUG("failed to load adau1761_new_EQ: out range\n"); } gpio_set_value(pa_mute_item, 0); return ret; } static unsigned int adau1761_register_size(unsigned int reg) { switch (reg) { case ADAU1761_DIGMIC_JACKDETECT: case ADAU1761_REC_MIXER_LEFT0: case ADAU1761_REC_MIXER_LEFT1: case ADAU1761_REC_MIXER_RIGHT0: case ADAU1761_REC_MIXER_RIGHT1: case ADAU1761_LEFT_DIFF_INPUT_VOL: case ADAU1761_RIGHT_DIFF_INPUT_VOL: case ADAU1761_PLAY_LR_MIXER_LEFT: case ADAU1761_PLAY_MIXER_LEFT0: case ADAU1761_PLAY_MIXER_LEFT1: case ADAU1761_PLAY_MIXER_RIGHT0: case ADAU1761_PLAY_MIXER_RIGHT1: case ADAU1761_PLAY_LR_MIXER_RIGHT: case ADAU1761_PLAY_MIXER_MONO: case ADAU1761_PLAY_HP_LEFT_VOL: case ADAU1761_PLAY_HP_RIGHT_VOL: case ADAU1761_PLAY_LINE_LEFT_VOL: case ADAU1761_PLAY_LINE_RIGHT_VOL: case ADAU1761_PLAY_MONO_OUTPUT_VOL: case ADAU1761_POP_CLICK_SUPPRESS: case ADAU1761_JACK_DETECT_PIN: case ADAU1761_DEJITTER: case ADAU1761_CLK_ENABLE0: case ADAU1761_CLK_ENABLE1: case ADAU17X1_CLOCK_CONTROL: case ADAU17X1_PLL_CONTROL: case ADAU17X1_REC_POWER_MGMT: case ADAU17X1_MICBIAS: case ADAU17X1_SERIAL_PORT0: case ADAU17X1_SERIAL_PORT1: case ADAU17X1_CONVERTER0: case ADAU17X1_CONVERTER1: case ADAU17X1_LEFT_INPUT_DIGITAL_VOL: case ADAU17X1_RIGHT_INPUT_DIGITAL_VOL: case ADAU17X1_ADC_CONTROL: case ADAU17X1_PLAY_POWER_MGMT: case ADAU17X1_DAC_CONTROL0: case ADAU17X1_DAC_CONTROL1: case ADAU17X1_DAC_CONTROL2: case ADAU17X1_SERIAL_PORT_PAD: case ADAU17X1_CONTROL_PORT_PAD0: case ADAU17X1_CONTROL_PORT_PAD1: case ADAU17X1_DSP_SAMPLING_RATE: case ADAU17X1_SERIAL_INPUT_ROUTE: case ADAU17X1_SERIAL_OUTPUT_ROUTE: case ADAU17X1_DSP_ENABLE: case ADAU17X1_DSP_RUN: case ADAU17X1_SERIAL_SAMPLING_RATE: return 1; default: if ((reg > ADAU1761_DATA_PARAM_START_ADDR) && (reg <= ADAU1761_DATA_PARAM_END_ADDR)) { return 4; } else { // do not support program RAM DSP_DEBUG("register_size: Unsupported register address: %d\n", reg); return 0; } } } static unsigned int adau1761_read(unsigned int reg) { unsigned int i; unsigned int size; uint8_t buf[4]; int ret; size = adau1761_register_size(reg); if (size == 0) { return 0; } buf[0] = (uint8_t)((reg >> 8) && 0xFF); buf[1] = (uint8_t)(reg && 0xFF); ret = i2c_master_send(adau1761_priv.i2c_client, buf, 2); if (ret < 0) { i = (unsigned int)ret; return i; } else if (ret != size + 2) { i = (unsigned int)(-EIO); return i; } ret = i2c_master_recv(adau1761_priv.i2c_client, buf, size); if (ret != size) { i = (unsigned int)(-EIO); return i; } else { ret = 0; for (i = 0; i < size; i++) { ret += buf[i]; ret <<= 8; } i = (uint32_t)ret; return i; } } static int adau1761_write(unsigned int reg, unsigned int value) { unsigned int i; unsigned int size; uint8_t buf[4]; int ret; size = adau1761_register_size(reg); if (size == 0) { return -EINVAL; } buf[0] = (uint8_t)((reg >> 8) && 0xFF); buf[1] = (uint8_t)(reg && 0xFF); for (i = size + 1; i > 1; --i) { buf[i] = (uint8_t)(value && 0xFF); value >>= 8; } ret = i2c_master_send(adau1761_priv.i2c_client, buf, size + 2); if (ret == size + 2) { return 0; } else if (ret < 0) { return ret; } else { return -EIO; } } int adau1761_open(struct inode *inode, struct file *filep) { int ret; DSP_DEBUG("open start\n"); mutex_lock(&adau1761_mutex); ret = nonseekable_open(inode, filep); mutex_unlock(&adau1761_mutex); return ret; } int adau1761_release(struct inode *inode, struct file *filep) { DSP_DEBUG("release start\n"); return 0; } // file operations static long adau1761_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { u8 i; int ret = 0; DSP_DEBUG("ioctl start cmd: %d arg: %lX\n", cmd, arg); if (_IOC_TYPE(cmd) != MAGIC_NUM) return -EINVAL; if (_IOC_NR(cmd) > ADAU1761_CMD_MAX) return -EINVAL; if (_IOC_DIR(cmd) & _IOC_READ) ret = !access_ok(VERIFY_WRITE, (void *)arg, _IOC_SIZE(cmd)); if (_IOC_DIR(cmd) & _IOC_WRITE) ret = !access_ok(VERIFY_READ, (void *)arg, _IOC_SIZE(cmd)); if (ret) return -EFAULT; DSP_DEBUG("ioctl start\n"); mutex_lock(&adau1761_mutex); DSP_DEBUG("ioctl lock\n"); switch (cmd) { case ADAU1761_CMD_VOL_SET: { if (arg > MAX_VOL_STEP) { ret = -EINVAL; goto failure; } for (i = 0; i < VOL_STEP_NUM; i++) { if (adau1761_vol_table[i].vtable_step == arg) { adau1761_priv.vol = arg; adau1761_safe_load((uint8_t *)(adau1761_vol_table[i].ram_word), 1, VOL_CTL_ADDR); break; } } } break; case ADAU1761_CMD_VOL_GET: { //*(unsigned long *)arg = (unsigned long)adau1761_priv.vol; put_user((unsigned long)adau1761_priv.vol, (unsigned long *)arg); } break; case ADAU1761_CMD_AMP_MUTE_SET: { if (arg > 1) { ret = -EINVAL; goto failure; } adau1761_priv.is_mute = arg; gpio_set_value(pa_mute_item, arg); } break; case ADAU1761_CMD_AMP_MUTE_GET: { *(unsigned long *)arg = (unsigned long)adau1761_priv.is_mute; } break; case ADAU1761_CMD_SRC_SET: { if (arg > 1) { ret = -EINVAL; goto failure; } adau1761_priv.src = arg; if (0 == arg) { // ana adau1761_safe_load((uint8_t *)src_analog_arr, 1, SRC_SW_ADDR); break; } else { // dig adau1761_safe_load((uint8_t *)src_dig_arr, 1, SRC_SW_ADDR); break; } } break; case ADAU1761_CMD_SRC_GET: { *(unsigned long *)arg = (unsigned long)adau1761_priv.src; } break; case ADAU1761_CMD_FW_LOAD: { process_sigma_firmware(adau1761_priv.i2c_client, ADAU1761_FIRMWARE); } break; case ADAU1761_CMD_EQ_SET: { ret = adau1761_safe_load_new_eq(arg); } break; default: break; } mutex_unlock(&adau1761_mutex); DSP_DEBUG("ioctl end\n"); return ret; failure: DSP_DEBUG("ioctl err: %d\n", ret); mutex_unlock(&adau1761_mutex); return ret; } static const struct file_operations adau1761_fops = { .owner = THIS_MODULE, .open = adau1761_open, .release = adau1761_release, .unlocked_ioctl = adau1761_ioctl, }; static struct miscdevice adau1761_misc = { .minor = MISC_DYNAMIC_MINOR, .name = "adau1761", .fops = &adau1761_fops, }; void netease_adau1761_init(void) { int i, ret = 0; mutex_lock(&adau1761_mutex); for (i = 0; i < ADAU1761_INIT_ARR_COUNT; i++) { if (adau1761_init_matrix_arr[i].byte_len) { ret = i2c_master_send(adau1761_priv.i2c_client, adau1761_init_matrix_arr[i].p_arr, adau1761_init_matrix_arr[i].byte_len); if (ret > 0) { DSP_DEBUG("Succeeded to load adau1761_init_arr_%d, transfer: " "%d bytes\n", i, ret); } else { DSP_DEBUG("Failed to load adau1761_init_arr_%d, failure: %d\n", i, ret); return -1; } } else { msleep(100); } } for (i = 0; ARRAY_SIZE(adau1761_vol_table); i++) { if (adau1761_vol_table[i].vtable_step == ADAU1761_DEF_VOL_STEP) { // use safeload ret = adau1761_safe_load( (uint8_t *)(adau1761_vol_table[i].ram_word), 1, VOL_CTL_ADDR); break; } } mutex_unlock(&adau1761_mutex); } EXPORT_SYMBOL(netease_adau1761_init); /*****************************************************/ static int adau1761_i2c_probe(struct i2c_client *client, const struct i2c_device_id *i2c_id) { int i, ret = 0; DSP_DEBUG("i2c_probe start\n"); adau1761_priv.i2c_client = client; adau1761_priv.vol = ADAU1761_DEF_VOL_STEP; adau1761_priv.src = 0; // ana for (i = 0; i < ADAU1761_INIT_ARR_COUNT; i++) { if (adau1761_init_matrix_arr[i].byte_len) { ret = i2c_master_send(adau1761_priv.i2c_client, adau1761_init_matrix_arr[i].p_arr, adau1761_init_matrix_arr[i].byte_len); if (ret > 0) { DSP_DEBUG("Succeeded to load adau1761_init_arr_%d, transfer: " "%d bytes\n", i, ret); } else { DSP_DEBUG("Failed to load adau1761_init_arr_%d, failure: %d\n", i, ret); return -1; } } else { msleep(100); } } for (i = 0; ARRAY_SIZE(adau1761_vol_table); i++) { if (adau1761_vol_table[i].vtable_step == ADAU1761_DEF_VOL_STEP) { // use safeload ret = adau1761_safe_load( (uint8_t *)(adau1761_vol_table[i].ram_word), 1, VOL_CTL_ADDR); break; } } DSP_DEBUG("i2c_probe end\n"); if (ret > 0) { ret = 0; } else { ret = -1; } return ret; } static int adau1761_i2c_remove(struct i2c_client *i2c) { return 0; } static struct i2c_board_info adau1761_i2c_board_info[] = { { I2C_BOARD_INFO("adau1761_0", 0x38), }, }; static const struct i2c_device_id adau1761_i2c_id[] = { {"adau1761_0", 0}, }; MODULE_DEVICE_TABLE(i2c, adau1761_i2c_id); static const unsigned short m_normal_i2c[2] = {0x38, I2C_CLIENT_END}; static struct i2c_driver adau1761_i2c_driver = { .driver = { .name = "adau1761_0", .owner = THIS_MODULE, }, .address_list = m_normal_i2c, .probe = adau1761_i2c_probe, .remove = adau1761_i2c_remove, .id_table = adau1761_i2c_id, }; static int __init adau1761_r311_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct device *dev = &pdev->dev; struct gpio_config config; pa_sdz_item = of_get_named_gpio_flags(np, "audio_pa_sdz", 0, (enum of_gpio_flags *)&config); if (!gpio_is_valid(pa_sdz_item)) { printk("get audio_pa_sdz failed\n"); return -EINVAL; } else { printk("Get audio_pa_sdz success,gpio:%d\n", pa_sdz_item); } devm_gpio_request(dev, pa_sdz_item, "pa_sdz_item"); gpio_direction_output(pa_sdz_item, 1); pa_mute_item = of_get_named_gpio_flags(np, "audio_pa_mute", 0, (enum of_gpio_flags *)&config); if (!gpio_is_valid(pa_mute_item)) { printk("get pa_mute_item failed\n"); return -EINVAL; } else { printk("Get pa_mute_item success,gpio:%d\n", pa_mute_item); } devm_gpio_request(dev, pa_mute_item, "pa_mute_item"); if (adau1761_priv.is_mute) { gpio_direction_output(pa_mute_item, 1); // set mute high } else { gpio_direction_output(pa_mute_item, 0); // set mute low } printk("adau1761, set pa_sdz=1, set pa_mute=%d\n", adau1761_priv.is_mute); return 0; } static const struct of_device_id adau1761_r311_ids[] = { {.compatible = "allwinner,adau1761-r311-pv1"}, {/* Sentinel */}}; static struct platform_driver adau1761_r311_driver = { .driver = { .owner = THIS_MODULE, .name = "adau1761-r311-pv1", .of_match_table = adau1761_r311_ids, }, }; static int __init adau1761_init(void) { struct i2c_adapter *adapter; struct i2c_client *client; int req_status, ret, i = 0; DSP_DEBUG("init start\n"); adau1761_priv.is_mute = 1; // mute platform_driver_probe(&adau1761_r311_driver, adau1761_r311_probe); ret = misc_register(&adau1761_misc); if (ret < 0) { DSP_DEBUG("init reg err\n"); misc_deregister(&adau1761_misc); return ret; } adau1761_priv.i2c_ch = 1; adapter = i2c_get_adapter(adau1761_priv.i2c_ch); if (!adapter) return -ENODEV; for (i = 0; i < sizeof(adau1761_i2c_board_info) / sizeof(adau1761_i2c_board_info[0]); i++) { client = NULL; client = i2c_new_device(adapter, &adau1761_i2c_board_info[i]); if (!client) return -ENODEV; } i2c_put_adapter(adapter); return i2c_add_driver(&adau1761_i2c_driver); } module_init(adau1761_init); static void __exit adau1761_exit(void) { i2c_del_driver(&adau1761_i2c_driver); } module_exit(adau1761_exit); MODULE_DESCRIPTION("ASoC codec adau1761 driver"); MODULE_AUTHOR("Netease IHW"); MODULE_LICENSE("GPL");