/* * Copyright (C) 2016 Allwinnertech, czy * * Copyright (C) 2013 Allwinnertech, kevin.z.m * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include "clk-sun8iw8.h" #include "clk-sun8iw8_tbl.c" #include #include"clk_factor.h" #include"clk_periph.h" #include #include #define FACTOR_SIZEOF(name) (sizeof(factor_pll##name##_tbl)/ \ sizeof(struct sunxi_clk_factor_freq)) #define FACTOR_SEARCH(name) (sunxi_clk_com_ftr_sr( \ &sunxi_clk_factor_pll_##name, factor, \ factor_pll##name##_tbl, index, \ FACTOR_SIZEOF(name))) #ifndef CONFIG_EVB_PLATFORM #define LOCKBIT(x) 31 #else #define LOCKBIT(x) x #endif DEFINE_SPINLOCK(clk_lock); void __iomem *sunxi_clk_base; void __iomem *sunxi_clk_cpus_base; int sunxi_clk_maxreg = SUNXI_CLK_MAX_REG; int cpus_clk_maxreg = 0; #ifdef CONFIG_SUNXI_CLK_DUMMY_DEBUG unsigned int dummy_reg[1024]; unsigned int dummy_readl(unsigned int* regaddr) { unsigned int val; val = *regaddr; printk("--%s-- dummy_readl to read reg 0x%x with val 0x%x\n", __func__, ((unsigned int)regaddr - (unsigned int)&dummy_reg[0]), val); return val; } void dummy_writel(unsigned int val,unsigned int* regaddr) { *regaddr = val; printk("--%s-- dummy_writel to write reg 0x%x with val 0x%x\n", __func__, ((unsigned int)regaddr - (unsigned int)&dummy_reg[0]), val); } void dummy_reg_init(void) { memset(dummy_reg,0x0,sizeof(dummy_reg)); dummy_reg[PLL_CPU/4]=0x00001000; dummy_reg[PLL_AUDIO/4]=0x00035514; dummy_reg[PLL_VIDEO0/4]=0x03006207; dummy_reg[PLL_DDR0/4]=0x00001800; dummy_reg[PLL_PERIPH0/4]=0x00041811; dummy_reg[PLL_VIDEO1/4]=0x03006207; dummy_reg[PLL_24M/4]=0xa00c1801; dummy_reg[PLL_PERIPH1/4]=0x00041811; dummy_reg[PLL_DE/4]=0x03006207; dummy_reg[PLL_DDR1/4]=0x00001800; dummy_reg[CPU_CFG/4]=0x00010300; dummy_reg[AHB1_CFG/4]=0x00001010; dummy_reg[APB2_CFG/4]=0x01000000; dummy_reg[PLL_LOCK/4]=0x000000FF; dummy_reg[CPU_LOCK/4]=0x000000FF; } #endif // of CONFIG_SUNXI_CLK_DUMMY_DEBUG /* * ns nw ks kw ms mw ps pw * d1s d1w d2s d2w {frac out mode} en-s sdmss * sdmsw sdmpat sdmval */ SUNXI_CLK_FACTORS (pll_cpu, 8, 5, 4, 2, 0, 2, 16, 2, 0, 0, 0, 0, 0, 0, 0, 31, 24, 0, PLL_CPUPAT, 0xd1303333); SUNXI_CLK_FACTORS (pll_audio, 8, 7, 0, 0, 0, 5, 16, 4, 0, 0, 0, 0, 0, 0, 0, 31, 24, 1, PLL_AUDIOPAT, 0xc0010d84); SUNXI_CLK_FACTORS (pll_video, 8, 7, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 1, 25, 24, 31, 20, 0, PLL_VIDEOPAT, 0xd1303333); SUNXI_CLK_FACTORS (pll_ve, 8, 7, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 1, 25, 24, 31, 20, 0, PLL_VEPAT, 0xd1303333); SUNXI_CLK_FACTORS_UPDATE(pll_ddr0, 8, 5, 4, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 24, 0, PLL_DDR0PAT, 0xd1303333, 20); SUNXI_CLK_FACTORS (pll_periph0, 8, 5, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0 ); SUNXI_CLK_FACTORS (pll_isp, 8, 7, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 1, 25, 24, 31, 20, 0, PLL_ISPPAT, 0xd1303333); SUNXI_CLK_FACTORS (pll_periph1, 8, 5, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 20, 0, PLL_PERI1PAT, 0xd1303333); SUNXI_CLK_FACTORS_UPDATE(pll_ddr1, 8, 6, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 24, 0, PLL_DDR1PAT, 0xf1303333,30); static int get_factors_pll_cpu(u32 rate, u32 parent_rate,struct clk_factors_value *factor) { int index; u64 tmp_rate; if (!factor) return -1; tmp_rate = rate>pllcpu_max ? pllcpu_max : rate; do_div(tmp_rate, 1000000); index = tmp_rate; return sunxi_clk_com_ftr_sr(&sunxi_clk_factor_pll_cpu, factor, factor_pllcpu_tbl, index, sizeof(factor_pllcpu_tbl) / sizeof(struct sunxi_clk_factor_freq)); } static int get_factors_pll_isp(u32 rate, u32 parent_rate, struct clk_factors_value *factor) { u64 tmp_rate; int index; if(!factor) return -1; tmp_rate = rate>pllisp_max ? pllisp_max : rate; do_div(tmp_rate, 1000000); index = tmp_rate; if(sunxi_clk_com_ftr_sr(&sunxi_clk_factor_pll_isp,factor, factor_pllisp_tbl,index, sizeof(factor_pllisp_tbl)/sizeof(struct sunxi_clk_factor_freq))) return -1; if(rate == 297000000) { factor->frac_mode = 0; factor->frac_freq = 1; factor->factorm = 0; } else if(rate == 270000000) { factor->frac_mode = 0; factor->frac_freq = 0; factor->factorm = 0; } else { factor->frac_mode = 1; factor->frac_freq = 0; } return 0; } static int get_factors_pll_ve(u32 rate, u32 parent_rate, struct clk_factors_value *factor) { u64 tmp_rate; int index; if(!factor) return -1; tmp_rate = rate>pllve_max ? pllve_max : rate; do_div(tmp_rate, 1000000); index = tmp_rate; if(sunxi_clk_com_ftr_sr(&sunxi_clk_factor_pll_ve,factor, factor_pllve_tbl,index, sizeof(factor_pllve_tbl)/sizeof(struct sunxi_clk_factor_freq))) return -1; if(rate == 297000000) { factor->frac_mode = 0; factor->frac_freq = 1; factor->factorm = 0; } else if(rate == 270000000) { factor->frac_mode = 0; factor->frac_freq = 0; factor->factorm = 0; } else { factor->frac_mode = 1; factor->frac_freq = 0; } return 0; } static int get_factors_pll_audio(u32 rate, u32 parent_rate,struct clk_factors_value *factor) { if(rate == 22579200) { factor->factorn = 6; factor->factorm = 0; factor->factorp = 7; sunxi_clk_factor_pll_audio.sdmval = 0xc0010d84; } else if(rate == 24576000) { factor->factorn = 13; factor->factorm = 0; factor->factorp = 13; sunxi_clk_factor_pll_audio.sdmval = 0xc000ac02; } else return -1; return 0; } static int get_factors_pll_video(u32 rate, u32 parent_rate,struct clk_factors_value *factor) { u64 tmp_rate; int index; if (!factor) return -1; tmp_rate = rate>pllvideo_max ? pllvideo_max : rate; do_div(tmp_rate, 1000000); index = tmp_rate; if (sunxi_clk_com_ftr_sr(&sunxi_clk_factor_pll_video, factor,factor_pllvideo_tbl, index, sizeof(factor_pllvideo_tbl)/ sizeof(struct sunxi_clk_factor_freq))) return -1; if (rate == 297000000) { factor->frac_mode = 0; factor->frac_freq = 1; factor->factorm = 0; } else if (rate == 270000000) { factor->frac_mode = 0; factor->frac_freq = 0; factor->factorm = 0; } else { factor->frac_mode = 1; factor->frac_freq = 0; } return 0; } static int get_factors_pll_ddr0(u32 rate, u32 parent_rate,struct clk_factors_value *factor) { int index; u64 tmp_rate; if (!factor) return -1; tmp_rate = rate > pllddr0_max ? pllddr0_max : rate; do_div(tmp_rate, 1000000); index = tmp_rate; return sunxi_clk_com_ftr_sr(&sunxi_clk_factor_pll_ddr0, factor,factor_pllddr0_tbl, index, sizeof(factor_pllddr0_tbl)/ sizeof(struct sunxi_clk_factor_freq)); } static int get_factors_pll_periph0(u32 rate, u32 parent_rate,struct clk_factors_value *factor) { int index; u64 tmp_rate; if (!factor) return -1; tmp_rate = rate>pllperiph0_max ? pllperiph0_max : rate; do_div(tmp_rate, 1000000); index = tmp_rate; return sunxi_clk_com_ftr_sr(&sunxi_clk_factor_pll_periph0, factor,factor_pllperiph0_tbl, index, sizeof(factor_pllperiph0_tbl)/ sizeof(struct sunxi_clk_factor_freq)); } static int get_factors_pll_periph1(u32 rate, u32 parent_rate,struct clk_factors_value *factor) { int index; u64 tmp_rate; if(!factor) return -1; tmp_rate = (rate > pllperiph1_max) ? pllperiph1_max : rate; do_div(tmp_rate, 1000000); index = tmp_rate; return sunxi_clk_com_ftr_sr(&sunxi_clk_factor_pll_periph1, factor,factor_pllperiph1_tbl, index, sizeof(factor_pllperiph1_tbl)/ sizeof(struct sunxi_clk_factor_freq)); } static int get_factors_pll_ddr1(u32 rate, u32 parent_rate, struct clk_factors_value *factor) { int index; u64 tmp_rate; if (!factor) return -1; tmp_rate = rate > pllddr1_max ? pllddr1_max : rate; do_div(tmp_rate, 1000000); index = tmp_rate; return sunxi_clk_com_ftr_sr(&sunxi_clk_factor_pll_ddr1, factor,factor_pllddr1_tbl, index, sizeof(factor_pllddr1_tbl)/ sizeof(struct sunxi_clk_factor_freq)); } /* * pll_cpux: 24*N*K/(M*P) */ static unsigned long calc_rate_pll_cpu(u32 parent_rate, struct clk_factors_value *factor) { u64 tmp_rate = (parent_rate?parent_rate:24000000); tmp_rate = tmp_rate * (factor->factorn+1) * (factor->factork+1); do_div(tmp_rate, (factor->factorm+1) * (1 << factor->factorp)); return (unsigned long)tmp_rate; } /* * pll_audio:24*N/(M*P) */ static unsigned long calc_rate_pll_audio(u32 parent_rate, struct clk_factors_value *factor) { u64 tmp_rate = (parent_rate?parent_rate:24000000); if ((factor->factorn == 6) && (factor->factorm == 0) && (factor->factorp == 7)) return 22579200; else if ((factor->factorn == 13) && (factor->factorm == 0) && (factor->factorp == 13)) return 24576000; else { tmp_rate = tmp_rate * (factor->factorn+1); do_div(tmp_rate, (factor->factorm+1) * (factor->factorp+1)); return (unsigned long)tmp_rate; } } /* * pll_video0:24*N/M */ static unsigned long calc_rate_media(u32 parent_rate, struct clk_factors_value *factor) { u64 tmp_rate = (parent_rate ? parent_rate : 24000000); if (factor->frac_mode == 0) { if (factor->frac_freq == 1) return 297000000; else return 270000000; } else { tmp_rate = tmp_rate * (factor->factorn+1); do_div(tmp_rate, factor->factorm+1); return (unsigned long)tmp_rate; } } /* * pll_ddr0:24*N/M */ static unsigned long calc_rate_pll_ddr0(u32 parent_rate, struct clk_factors_value *factor) { u64 tmp_rate = (parent_rate?parent_rate:24000000); tmp_rate = tmp_rate * (factor->factorn + 1) * (factor->factork+1); do_div(tmp_rate, factor->factorm + 1); return (unsigned long)tmp_rate; } /* *pll_ddr1 */ static unsigned long calc_rate_pll_ddr1(u32 parent_rate, struct clk_factors_value *factor) { u64 tmp_rate = (parent_rate?parent_rate:24000000); tmp_rate = tmp_rate * (factor->factorn+1); do_div(tmp_rate,factor->factorm+1); return (unsigned long) tmp_rate; } /* * pll_periph0:24*N*K/2 */ static unsigned long calc_rate_pll_periph(u32 parent_rate, struct clk_factors_value *factor) { return (unsigned long)(parent_rate ? (parent_rate / 2) : 12000000) * (factor->factorn+1) * (factor->factork+1); } static const char *hosc_parents[] = {"hosc"}; static const char *cpu_parents[] = {"losc", "hosc", "pll_cpu", "pll_cpu"}; static const char *axi_parents[] = {"cpu"}; static const char *pll_periphahb0_parents[] = {"pll_periph0"}; static const char *ahb0_parents[] = {"losc", "hosc", "axi", "pll_periphahb0"}; static const char *apb0_parents[] = {"ahb0"}; static const char *apb1_parents[] = {"losc", "hosc", "pll_periph0", "pll_periph0"}; static const char *periph0_parents[] = {"hosc", "pll_periph0", "", ""}; static const char *periph_parents[] = {"hosc", "pll_periph0","pll_periph1",""}; static const char *i2s_parents[] = {"pll_audiox8", "pll_audiox4", "pll_audiox2", "pll_audio"}; static const char *display_parents[] = {"pll_video", "", "pll_periph0", "", "", "","",""}; static const char *csi_s_parents[] = {"pll_video", "pll_isp", "", "", "", "","",""}; static const char *csi_m_parents[] = {"hosc", "pll_video", "pll_periph1", "pll_periph0", "", "","",""}; static const char *mbus_parents[] = {"hosc", "pll_periph0x2", "pll_ddr0", ""}; static const char *mipicsi_parents[] = {"pll_video", "pll_periph0", "pll_isp",""}; static const char *adda_parents[] = {"pll_audio"}; static const char *ve_parents[] = {"pll_ve"}; static const char *lvds_parents[] = {"tcon"}; static const char *ahb0mod_parents[] = {"ahb0"}; static const char *apb0mod_parents[] = {"apb0"}; static const char *apb1mod_parents[] = {"apb1"}; static const char *ahb1_parents[] = {"ahb0" , "pll_periph0d2" , "" , ""}; static const char *losc_parents[] = {"losc"}; static const char *ahb1mod_parents[] = {"ahb1"}; struct factor_init_data sunxi_factos[] = { /* name parent parent_num, flags reg lock_reg lock_bit config get_factors calc_rate priv_ops*/ {"pll_cpu", hosc_parents, 1, CLK_GET_RATE_NOCACHE|CLK_RATE_FLAT_FACTORS|CLK_RATE_FLAT_DELAY, PLL_CPU, PLL_CPU, LOCKBIT(28), 0, 0, PLL_LOCK_NONE_MODE, &sunxi_clk_factor_pll_cpu, &get_factors_pll_cpu, &calc_rate_pll_cpu, (struct clk_ops *)NULL}, {"pll_audio", hosc_parents, 1, 0, PLL_AUDIO, PLL_AUDIO, LOCKBIT(28), 0, 1, PLL_LOCK_NONE_MODE, &sunxi_clk_factor_pll_audio, &get_factors_pll_audio, &calc_rate_pll_audio, (struct clk_ops *)NULL}, {"pll_video", hosc_parents, 1, 0, PLL_VIDEO, PLL_VIDEO, LOCKBIT(28), 0, 2, PLL_LOCK_NONE_MODE, &sunxi_clk_factor_pll_video, &get_factors_pll_video, &calc_rate_media, (struct clk_ops *)NULL}, {"pll_ddr0",hosc_parents,1, CLK_GET_RATE_NOCACHE, PLL_DDR0, PLL_DDR0, LOCKBIT(28), 0, 3, PLL_LOCK_NONE_MODE, &sunxi_clk_factor_pll_ddr0, &get_factors_pll_ddr0, &calc_rate_pll_ddr0, (struct clk_ops *)NULL}, {"pll_periph0", hosc_parents, 1, 0, PLL_PERIPH0, PLL_PERIPH0, LOCKBIT(28), 0, 4, PLL_LOCK_NONE_MODE, &sunxi_clk_factor_pll_periph0, &get_factors_pll_periph0, &calc_rate_pll_periph, (struct clk_ops *)NULL}, {"pll_periph1", hosc_parents, 1, 0, PLL_PERIPH1, PLL_PERIPH1, LOCKBIT(28), 0, 5, PLL_LOCK_NONE_MODE, &sunxi_clk_factor_pll_periph1, &get_factors_pll_periph1, &calc_rate_pll_periph, (struct clk_ops *)NULL}, {"pll_ve", hosc_parents, 1, 0, PLL_VE, PLL_VE, LOCKBIT(28), 0, 6, PLL_LOCK_NONE_MODE, &sunxi_clk_factor_pll_ve, &get_factors_pll_ve, &calc_rate_media, (struct clk_ops *)NULL}, {"pll_isp", hosc_parents, 1, 0, PLL_ISP, PLL_ISP, LOCKBIT(28), 0, 7, PLL_LOCK_NONE_MODE, &sunxi_clk_factor_pll_isp, &get_factors_pll_isp, &calc_rate_media, (struct clk_ops *)NULL}, {"pll_ddr1", hosc_parents, 1, CLK_GET_RATE_NOCACHE, PLL_DDR1, PLL_DDR1, LOCKBIT(28), 0, 8, PLL_LOCK_NONE_MODE, &sunxi_clk_factor_pll_ddr1, &get_factors_pll_ddr1, &calc_rate_pll_ddr1, (struct clk_ops *)NULL}, }; struct sunxi_clk_comgate com_gates[]={ {"csi", 0, 0x3, BUS_GATE_SHARE|RST_GATE_SHARE|MBUS_GATE_SHARE, 0}, }; /* SUNXI_CLK_PERIPH(name, mux_reg, mux_sft, mux_wid, div_reg, div_msft, div_mwid, div_nsft, div_nwid, gate_flag, en_reg, rst_reg, bus_gate_reg, drm_gate_reg, en_sft, rst_sft, bus_gate_sft, dram_gate_sft, lock, com_gate, com_gate_off) */ SUNXI_CLK_PERIPH(cpu, CPU_CFG, 16, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); SUNXI_CLK_PERIPH(axi, 0, 0, 0, CPU_CFG, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); SUNXI_CLK_PERIPH(pll_periphahb0, 0, 0, 0, AHB1_CFG, 6, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); SUNXI_CLK_PERIPH(ahb0, AHB1_CFG, 12, 2, AHB1_CFG, 0, 0, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock, NULL, 0); SUNXI_CLK_PERIPH(apb0, 0, 0, 0, AHB1_CFG, 0, 0, 8, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(apb1, APB2_CFG, 24, 2, APB2_CFG, 0, 5, 16, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(ahb1, AHB2_CFG, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(sdmmc0_mod, SD0_CFG, 24, 2, SD0_CFG, 0, 4, 16, 2, 0, SD0_CFG, 0, 0, 0, 31, 8, 8, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(sdmmc0_bus, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_GATE0, 0, 0, 0, 8, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(sdmmc0_rst, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_RST0, 0, 0, 0, 8, 0, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(sdmmc1_mod, SD1_CFG, 24, 2, SD1_CFG, 0, 4, 16, 2, 0, SD1_CFG, 0, 0, 0, 31, 9, 9, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(sdmmc1_bus, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_GATE0, 0, 0, 0, 9, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(sdmmc1_rst, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_RST0, 0, 0, 0, 9, 0, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(sdmmc2_mod, SD2_CFG, 24, 2, SD2_CFG, 30, 1, 0, 0, 0, SD2_CFG, 0, 0, 0, 0, 0, 0, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(sdmmc2_bus, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_GATE0, DRAM_GATE, 0, 0, 10, 2, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(sdmmc2_rst, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_RST0, 0, 0, 0, 10, 0, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(ss, SS_CFG, 24, 2, SS_CFG, 0, 4, 16, 2, 0, SS_CFG, BUS_RST0, BUS_GATE0, 0, 31, 5, 5, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(spi0, SPI0_CFG, 24, 2, SPI0_CFG, 0, 4, 16, 2, 0, SPI0_CFG, BUS_RST0, BUS_GATE0, 0, 31, 20, 20, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(i2s0, I2S0_CFG, 16, 2, 0, 0, 0, 0, 0, 0, I2S0_CFG, BUS_RST3, BUS_GATE2, 0, 31, 12, 12, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(usbohci0, 0, 0, 0, 0, 0, 0, 0, 0, 0, USB_CFG, BUS_RST0, BUS_GATE0, DRAM_GATE, 16, 29, 29, 18, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(usbehci0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_RST0, BUS_GATE0, DRAM_GATE, 0, 26, 26, 17, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(usbotg, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_RST0, BUS_GATE0, 0, 0, 24, 24, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(usbphy0, 0, 0, 0, 0, 0, 0, 0, 0, 0, USB_CFG, USB_CFG, 0, 0, 8, 0, 0, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(de, DE_CFG, 24, 3, DE_CFG, 0, 4, 0, 0, 0, DE_CFG, BUS_RST1, BUS_GATE1, 0, 31, 12, 12, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(tcon, TCON_CFG, 24, 3, TCON_CFG, 0, 4, 0, 0, 0, TCON_CFG, BUS_RST1, BUS_GATE1, 0, 31, 4, 4, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(csi0_s, 0, 0, 0, 0, 0, 0, 0, 0, 0, CSI0_CFG, BUS_RST1, BUS_GATE1, DRAM_GATE, 31, 8, 8, 1, &clk_lock,&com_gates[0], 0); SUNXI_CLK_PERIPH(csi0_m, CSI0_CFG, 8, 3, CSI0_CFG, 0, 5, 0, 0, 0, CSI0_CFG, BUS_RST1, BUS_GATE1, DRAM_GATE, 15, 8, 8, 1, &clk_lock,&com_gates[0], 1); SUNXI_CLK_PERIPH(csi1_s, CSI1_CFG, 24, 3, CSI1_CFG, 16, 4, 0, 0, 0, CSI1_CFG, BUS_RST1, BUS_GATE1, DRAM_GATE, 31, 8, 8, 1, &clk_lock,&com_gates[0], 2); SUNXI_CLK_PERIPH(csi1_m, CSI1_CFG, 8, 3, CSI1_CFG, 0, 5, 0, 0, 0, CSI1_CFG, BUS_RST1, BUS_GATE1, DRAM_GATE, 15, 8, 8, 1, &clk_lock,&com_gates[0], 3); SUNXI_CLK_PERIPH(csi_misc, 0, 0, 0, 0, 0, 0, 0, 0, 0, CSI_MISC, BUS_RST1, BUS_GATE1, DRAM_GATE, 31, 8, 8, 1, &clk_lock, &com_gates[0], 2); SUNXI_CLK_PERIPH(ve, 0, 0, 0, VE_CFG, 16, 3, 0, 0, 0, VE_CFG, BUS_RST1, BUS_GATE1, DRAM_GATE, 31, 0, 0, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(adda, 0, 0, 0, 0, 0, 0, 0, 0, 0, ADDA_CFG, BUS_RST3, BUS_GATE2, 0, 31, 0, 0, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(avs, 0, 0, 0, 0, 0, 0, 0, 0, 0, AVS_CFG, 0, 0, 0, 31, 0, 0, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(mbus, MBUS_CFG, 24, 2, MBUS_CFG, 0, 3, 0, 0, 0, MBUS_CFG, 0, 0, 0, 31, 0, 0, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(mipicsi, MIPI_CSI, 24, 2, MIPI_CSI, 0, 4, 0, 0, 0, MIPI_CSI, 0, 0, 0, 31, 0, 0, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(gmac, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_RST0, BUS_GATE0, 0, 0, 17, 17, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(dma, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_RST0, BUS_GATE0, 0, 0, 6, 6, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(pio, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_GATE2, 0, 0, 0, 5, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(uart0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_RST4, BUS_GATE3, 0, 0, 16, 16, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(uart1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_RST4, BUS_GATE3, 0, 0, 17, 17, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(uart2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_RST4, BUS_GATE3, 0, 0, 18, 18, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(twi0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_RST4, BUS_GATE3, 0, 0, 0, 0, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(twi1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_RST4, BUS_GATE3, 0, 0, 1, 1, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(ephy, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_RST2, BUS_GATE4, 0, 0, 2, 0, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(lvds, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, BUS_RST2, 0, 0, 0, 0, 0, 0, &clk_lock,NULL, 0); SUNXI_CLK_PERIPH(losc_out, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, LOSC_OUT_GATE, 0, 0, 0, 0, 0, &clk_lock,NULL, 0); struct periph_init_data sunxi_periphs_init[] = { {"cpu", CLK_GET_RATE_NOCACHE, cpu_parents, ARRAY_SIZE(cpu_parents), &sunxi_clk_periph_cpu}, {"axi", 0, axi_parents, ARRAY_SIZE(axi_parents), &sunxi_clk_periph_axi}, {"pll_periphahb0", CLK_IGNORE_SYNCBOOT, pll_periphahb0_parents, ARRAY_SIZE(pll_periphahb0_parents), &sunxi_clk_periph_pll_periphahb0}, {"ahb0", 0, ahb0_parents, ARRAY_SIZE(ahb0_parents), &sunxi_clk_periph_ahb0}, {"apb0", 0, apb0_parents, ARRAY_SIZE(apb0_parents), &sunxi_clk_periph_apb0}, {"apb1", 0, apb1_parents, ARRAY_SIZE(apb1_parents), &sunxi_clk_periph_apb1}, {"ahb1", 0, ahb1_parents, ARRAY_SIZE(ahb1_parents), &sunxi_clk_periph_ahb1}, {"sdmmc0_mod", 0, periph_parents, ARRAY_SIZE(periph_parents), &sunxi_clk_periph_sdmmc0_mod}, {"sdmmc0_bus", 0, periph_parents, ARRAY_SIZE(periph_parents), &sunxi_clk_periph_sdmmc0_bus}, {"sdmmc0_rst", 0, periph_parents, ARRAY_SIZE(periph_parents), &sunxi_clk_periph_sdmmc0_rst}, {"sdmmc1_mod", 0, periph_parents, ARRAY_SIZE(periph_parents), &sunxi_clk_periph_sdmmc1_mod}, {"sdmmc1_bus", 0, periph_parents, ARRAY_SIZE(periph_parents), &sunxi_clk_periph_sdmmc1_bus}, {"sdmmc1_rst", 0, periph_parents, ARRAY_SIZE(periph_parents), &sunxi_clk_periph_sdmmc1_rst}, {"sdmmc2_mod", 0, periph_parents, ARRAY_SIZE(periph_parents), &sunxi_clk_periph_sdmmc2_mod}, {"sdmmc2_bus", 0, periph_parents, ARRAY_SIZE(periph_parents), &sunxi_clk_periph_sdmmc2_bus}, {"sdmmc2_rst", 0, periph_parents, ARRAY_SIZE(periph_parents), &sunxi_clk_periph_sdmmc2_rst}, {"ss", 0, periph0_parents, ARRAY_SIZE(periph0_parents), &sunxi_clk_periph_ss}, {"spi0", 0, periph_parents, ARRAY_SIZE(periph_parents), &sunxi_clk_periph_spi0}, {"i2s0", 0, i2s_parents, ARRAY_SIZE(i2s_parents), &sunxi_clk_periph_i2s0}, {"usbohci0", 0, ahb0mod_parents, ARRAY_SIZE(ahb0mod_parents), &sunxi_clk_periph_usbohci0}, {"usbehci0", 0, ahb0mod_parents, ARRAY_SIZE(ahb0mod_parents), &sunxi_clk_periph_usbehci0}, {"usbotg", 0, ahb0mod_parents, ARRAY_SIZE(ahb0mod_parents), &sunxi_clk_periph_usbotg}, {"usbphy0", 0, hosc_parents, ARRAY_SIZE(hosc_parents), &sunxi_clk_periph_usbphy0}, {"de", 0, display_parents, ARRAY_SIZE(display_parents), &sunxi_clk_periph_de}, {"tcon", 0, display_parents, ARRAY_SIZE(display_parents), &sunxi_clk_periph_tcon}, {"csi_misc", 0, hosc_parents, ARRAY_SIZE(hosc_parents), &sunxi_clk_periph_csi_misc}, {"csi0_s", 0, hosc_parents, ARRAY_SIZE(hosc_parents), &sunxi_clk_periph_csi0_s}, {"csi0_m", 0, csi_m_parents, ARRAY_SIZE(csi_m_parents), &sunxi_clk_periph_csi0_m}, {"csi1_s", 0, csi_s_parents, ARRAY_SIZE(csi_s_parents), &sunxi_clk_periph_csi1_s}, {"csi1_m", 0, csi_m_parents, ARRAY_SIZE(csi_m_parents), &sunxi_clk_periph_csi1_m}, {"ve", 0, ve_parents, ARRAY_SIZE(ve_parents), &sunxi_clk_periph_ve}, {"lvds", 0, lvds_parents, ARRAY_SIZE(lvds_parents), &sunxi_clk_periph_lvds}, {"adda", 0, adda_parents, ARRAY_SIZE(adda_parents), &sunxi_clk_periph_adda}, {"avs", 0, hosc_parents, ARRAY_SIZE(hosc_parents), &sunxi_clk_periph_avs}, {"mbus", 0, mbus_parents, ARRAY_SIZE(mbus_parents), &sunxi_clk_periph_mbus}, {"mipicsi", 0, mipicsi_parents, ARRAY_SIZE(mipicsi_parents), &sunxi_clk_periph_mipicsi}, {"gmac", 0, ahb1mod_parents, ARRAY_SIZE(ahb1mod_parents), &sunxi_clk_periph_gmac}, {"ephy", 0, ahb0mod_parents, ARRAY_SIZE(ahb0mod_parents), &sunxi_clk_periph_ephy}, {"dma", 0, ahb0mod_parents, ARRAY_SIZE(ahb0mod_parents), &sunxi_clk_periph_dma}, {"pio", 0, apb0mod_parents, ARRAY_SIZE(apb0mod_parents), &sunxi_clk_periph_pio}, {"twi0", 0, apb1mod_parents, ARRAY_SIZE(apb1mod_parents), &sunxi_clk_periph_twi0}, {"twi1", 0, apb1mod_parents, ARRAY_SIZE(apb1mod_parents), &sunxi_clk_periph_twi1}, {"uart0", 0, apb1mod_parents, ARRAY_SIZE(apb1mod_parents), &sunxi_clk_periph_uart0}, {"uart1", 0, apb1mod_parents, ARRAY_SIZE(apb1mod_parents), &sunxi_clk_periph_uart1}, {"uart2", 0, apb1mod_parents, ARRAY_SIZE(apb1mod_parents), &sunxi_clk_periph_uart2}, {"losc_out", 0, losc_parents, ARRAY_SIZE(losc_parents), &sunxi_clk_periph_losc_out} }; void init_clocks(void) { int i; //struct clk *clk; struct factor_init_data *factor; struct periph_init_data *periph; /* get clk register base address */ sunxi_clk_base = (void*)0x01c20000; //fixed base address. sunxi_clk_factor_initlimits(); clk_register_fixed_rate(NULL, "hosc", NULL, CLK_IS_ROOT, 24000000); /* register normal factors, based on sunxi factor framework */ for(i=0; ipriv_regops = NULL; sunxi_clk_register_factors(NULL, (void*)sunxi_clk_base, (struct factor_init_data*)factor); } /* register periph clock */ for(i=0; iperiph->priv_regops = NULL; sunxi_clk_register_periph(periph, sunxi_clk_base); } printf("%s: finish init_clocks.\n",__func__); } #ifdef CONFIG_OF struct factor_init_data *sunxi_clk_get_factor_by_name(const char *name) { struct factor_init_data *factor; int i; /* get pll clk init config */ for (i = 0; i < ARRAY_SIZE(sunxi_factos); i++) { factor = &sunxi_factos[i]; if (strcmp(name, factor->name)) continue; return factor; } return NULL; } /* * sunxi_clk_get_periph_by_name() - Get periph clk init config */ struct periph_init_data *sunxi_clk_get_periph_by_name(const char *name) { struct periph_init_data *perpih; int i; for (i = 0; i < ARRAY_SIZE(sunxi_periphs_init); i++) { perpih = &sunxi_periphs_init[i]; if (strcmp(name, perpih->name)) continue; return perpih; } return NULL; } /* * sunxi_clk_get_periph_cpus_by_name() - Get periph clk init config */ struct periph_init_data *sunxi_clk_get_periph_cpus_by_name(const char *name) { return NULL; } struct periph_init_data *sunxi_cpus_clk_get_periph_by_name(const char *name) { return NULL; } void __init sunxi_clocks_init(struct device_node *node) { sunxi_clk_base = of_iomap(node, 0); /*sunxi_clk_cpus_base = of_iomap(node, 1);*/ sunxi_clk_periph_losc_out.gate.bus = of_iomap(node, 1); /*do some initialize arguments here*/ sunxi_clk_factor_initlimits(); } #endif