/* * Allwinner sun50iw1p1 SoCs pinctrl driver. * * Copyright (C) 2014 Jackie Hwang * * Jackie Hwang * * Copyright (C) 2014 Chen-Yu Tsai * * Chen-Yu Tsai * * Copyright (C) 2014 Maxime Ripard * * Maxime Ripard * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. */ #include #include #include #include #include #include "pinctrl-sunxi.h" static const struct sunxi_desc_pin sun50iw1p1_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart2"), /*TX*/ SUNXI_FUNCTION(0x3, "vdevice"), /*vdevice for test */ SUNXI_FUNCTION(0x4, "jtag0"), /*MS0*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /*PB_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart2"), /*RX*/ SUNXI_FUNCTION(0x3, "vdevice"), /*vdevice for test */ SUNXI_FUNCTION(0x4, "jtag0"), /*CK0*/ SUNXI_FUNCTION(0x5, "sim0"), /*PWREN*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /*PB_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart2"), /*RTS*/ SUNXI_FUNCTION(0x4, "jtag0"), /*DO0*/ SUNXI_FUNCTION(0x5, "sim0"), /*VPPEN*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /*PB_EINT2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart2"), /*RTS*/ SUNXI_FUNCTION(0x3, "pcm0"), /*MCLK*/ SUNXI_FUNCTION(0x4, "jtag0"), /*DO0*/ SUNXI_FUNCTION(0x5, "sim0"), /*VPPPP*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /*PB_EINT3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "aif2"), /*SYNC*/ SUNXI_FUNCTION(0x3, "pcm0"), /*SYNC*/ SUNXI_FUNCTION(0x5, "sim0"), /*CLK*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /*PB_EINT4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "aif2"), /*BCLK*/ SUNXI_FUNCTION(0x3, "pcm0"), /*BCLK*/ SUNXI_FUNCTION(0x5, "sim0"), /*DATA*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /*PB_EINT5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "aif2"), /*DOUT*/ SUNXI_FUNCTION(0x3, "pcm0"), /*DOUT*/ SUNXI_FUNCTION(0x5, "sim0"), /*RST*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /*PB_EINT6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "aif2"), /*DIN*/ SUNXI_FUNCTION(0x3, "pcm0"), /*DIN*/ SUNXI_FUNCTION(0x5, "sim0"), /*DET*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /*PB_EINT7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x4, "uart0"), /*TX*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /*PB_EINT8 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x4, "uart0"), /*RX*/ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /*PB_EINT9 */ /* HOLE */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /*WE*/ SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ SUNXI_FUNCTION(0x3, "sdc2"), /* DS */ SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ SUNXI_FUNCTION(0x4, "spi0"), /* CLK */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ SUNXI_FUNCTION(0x4, "spi0"), /* CS */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* RE */ SUNXI_FUNCTION(0x3, "sdc2"), /* CLK */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ SUNXI_FUNCTION(0x3, "sdc2"), /* CMD */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ SUNXI_FUNCTION(0x3, "sdc2"), /* D0 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ SUNXI_FUNCTION(0x3, "sdc2"), /* D1 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ SUNXI_FUNCTION(0x3, "sdc2"), /* D2 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ SUNXI_FUNCTION(0x3, "sdc2"), /* D3 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ SUNXI_FUNCTION(0x3, "sdc2"), /* D4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ SUNXI_FUNCTION(0x3, "sdc2"), /* D5 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ SUNXI_FUNCTION(0x3, "sdc2"), /* D6 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ SUNXI_FUNCTION(0x3, "sdc2"), /* D7 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ SUNXI_FUNCTION(0x3, "sdc2"), /* RST */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* CE2 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "nand0"), /* CE3 */ SUNXI_FUNCTION(0x7, "io_disabled")), #if defined(CONFIG_FPGA_V7_PLATFORM) /* HOLE */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ SUNXI_FUNCTION(0x3, "lvds0"), /* TX */ SUNXI_FUNCTION(0x4, "spi1"), /* CS */ SUNXI_FUNCTION(0x5, "ccir0"), /* CLK */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ SUNXI_FUNCTION(0x3, "lvds0"), /* RX */ SUNXI_FUNCTION(0x4, "spi1"), /* CLK */ SUNXI_FUNCTION(0x5, "ccir0"), /* DE */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ SUNXI_FUNCTION(0x3, "lvds0"), /* TX */ SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */ SUNXI_FUNCTION(0x5, "ccir0"), /* HSYNC */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ SUNXI_FUNCTION(0x3, "lvds0"), /* RX */ SUNXI_FUNCTION(0x4, "spi1"), /* CLK */ SUNXI_FUNCTION(0x5, "ccir0"), /* VSYNC */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ SUNXI_FUNCTION(0x3, "lvds0"), /* RTS */ SUNXI_FUNCTION(0x5, "ccir0"), /* D0 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ SUNXI_FUNCTION(0x3, "lvds0"), /* CTS */ SUNXI_FUNCTION(0x5, "ccir0"), /* D1 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ SUNXI_FUNCTION(0x3, "lvds0"), SUNXI_FUNCTION(0x5, "ccir0"), /* D2*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ SUNXI_FUNCTION(0x3, "lvds0"), SUNXI_FUNCTION(0x5, "ccir0"), /* D3*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ SUNXI_FUNCTION(0x3, "lvds0"), SUNXI_FUNCTION(0x4, "gmac0"), /* RXD3 */ SUNXI_FUNCTION(0x5, "ccir0"), /* D4*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ SUNXI_FUNCTION(0x3, "lvds0"), SUNXI_FUNCTION(0x4, "gmac0"), /* RXD2 */ SUNXI_FUNCTION(0x5, "ccir0"), /* D5*/ SUNXI_FUNCTION(0x7, "io_disabled")), #else /* HOLE */ SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ SUNXI_FUNCTION(0x3, "uart3"), /* TX */ SUNXI_FUNCTION(0x4, "spi1"), /* CS */ SUNXI_FUNCTION(0x5, "ccir0"), /* CLK */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ SUNXI_FUNCTION(0x3, "uart3"), /* RX */ SUNXI_FUNCTION(0x4, "spi1"), /* CLK */ SUNXI_FUNCTION(0x5, "ccir0"), /* DE */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ SUNXI_FUNCTION(0x3, "uart4"), /* TX */ SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */ SUNXI_FUNCTION(0x5, "ccir0"), /* HSYNC */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ SUNXI_FUNCTION(0x3, "uart4"), /* RX */ SUNXI_FUNCTION(0x4, "spi1"), /* CLK */ SUNXI_FUNCTION(0x5, "ccir0"), /* VSYNC */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ SUNXI_FUNCTION(0x3, "uart4"), /* RTS */ SUNXI_FUNCTION(0x5, "ccir0"), /* D0 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ SUNXI_FUNCTION(0x3, "uart4"), /* CTS */ SUNXI_FUNCTION(0x5, "ccir0"), /* D1 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ SUNXI_FUNCTION(0x5, "ccir0"), /* D2*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ SUNXI_FUNCTION(0x5, "ccir0"), /* D3*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ SUNXI_FUNCTION(0x4, "gmac0"), /* RXD3 */ SUNXI_FUNCTION(0x5, "ccir0"), /* D4*/ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ SUNXI_FUNCTION(0x4, "gmac0"), /* RXD2 */ SUNXI_FUNCTION(0x5, "ccir0"), /* D5*/ SUNXI_FUNCTION(0x7, "io_disabled")), #endif SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ SUNXI_FUNCTION(0x4, "gmac0"), /* RXD1 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ SUNXI_FUNCTION(0x4, "gmac0"), /* RXD0 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */ SUNXI_FUNCTION(0x4, "gmac0"), /* RXCK */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */ SUNXI_FUNCTION(0x4, "gmac0"), /* RXCTL */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */ SUNXI_FUNCTION(0x4, "gmac0"), /* NULL */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */ SUNXI_FUNCTION(0x4, "gmac0"), /* TXD3 */ SUNXI_FUNCTION(0x5, "ccir0"), /* D6 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */ SUNXI_FUNCTION(0x4, "gmac0"), /* TXD2 */ SUNXI_FUNCTION(0x5, "ccir0"), /* D7 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */ SUNXI_FUNCTION(0x4, "gmac0"), /* TXD1 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ SUNXI_FUNCTION(0x3, "lvds0"), /* VPC */ SUNXI_FUNCTION(0x4, "gmac0"), /* TXD0 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ SUNXI_FUNCTION(0x3, "lvds0"), /* VNC */ SUNXI_FUNCTION(0x4, "gmac0"), /* TXCK */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ SUNXI_FUNCTION(0x3, "lvds0"), /* VP3 */ SUNXI_FUNCTION(0x4, "gmac0"), /* TXCLK */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ SUNXI_FUNCTION(0x3, "lvds0"), /* VN3 */ SUNXI_FUNCTION(0x4, "gmac0"), /* CLKIN */ SUNXI_FUNCTION(0x7, "io_disabled")), #if defined(CONFIG_FPGA_V4_PLATFORM) SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), SUNXI_FUNCTION(0x4, "gmac0"), /* CLKIN */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), SUNXI_FUNCTION(0x4, "gmac0"), /* CLKIN */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "lcd0"), SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "pwm0"), SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 29), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x7, "io_disabled")), #else SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "pwm0"), SUNXI_FUNCTION(0x4, "gmac0"), /* CLKIN */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x4, "gmac0"), /* CLKIN */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x7, "io_disabled")), #endif /* HOLE */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /* PCLK */ SUNXI_FUNCTION(0x4, "ts0"), /* CLK */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /* MCLK */ SUNXI_FUNCTION(0x4, "ts0"), /* ERR */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /* HSYNC */ SUNXI_FUNCTION(0x4, "ts0"), /* SYNC */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /* VSYNC */ SUNXI_FUNCTION(0x4, "ts0"), /* DVLD */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /* D0 */ SUNXI_FUNCTION(0x4, "ts0"), /* D0 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /* D1 */ SUNXI_FUNCTION(0x4, "ts0"), /* D1 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /* D2 */ SUNXI_FUNCTION(0x4, "ts0"), /* D2 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /* D3 */ SUNXI_FUNCTION(0x4, "ts0"), /* D3 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /* D4 */ SUNXI_FUNCTION(0x4, "ts0"), /* D4 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /* D5 */ SUNXI_FUNCTION(0x4, "ts0"), /* D5 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /* D6 */ SUNXI_FUNCTION(0x4, "ts0"), /* D6 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /* D7 */ SUNXI_FUNCTION(0x4, "ts0"), /* D7 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /* SCK */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "csi0"), /* SDA */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "pll_lock_dgb"), SUNXI_FUNCTION(0x3, "twi2"), /* SCK */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "pll_lock_dgb"), SUNXI_FUNCTION(0x3, "twi2"), /* SDA */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x7, "io_disabled")), /* HOLE */ SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc0"), /* D1 */ SUNXI_FUNCTION(0x3, "jtag0"), /* MSI */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc0"), /* D0 */ SUNXI_FUNCTION(0x3, "jtag0"), /* DI1 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc0"), /* CLK */ SUNXI_FUNCTION(0x3, "uart0"), /* TX */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc0"), /* CMD */ SUNXI_FUNCTION(0x3, "jtag0"), /* DO1 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc0"), /* D3 */ SUNXI_FUNCTION(0x3, "uart0"), /* RX */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc0"), /* D2 */ SUNXI_FUNCTION(0x3, "jtag0"), /* CK1 */ SUNXI_FUNCTION(0x7, "io_disabled")), SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x7, "io_disabled")), /* HOLE */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* CLK */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* CMD */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D0 */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D1 */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D2 */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "sdc1"), /* D3 */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart1"), /* TX */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart1"), /* RX */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "aif3"), /* SYNC */ SUNXI_FUNCTION(0x3, "pcm1"), /* SYNC */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "aif3"), /* BCLK */ SUNXI_FUNCTION(0x3, "pcm1"), /* BCLK */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "aif3"), /* DOUT */ SUNXI_FUNCTION(0x3, "pcm1"), /* DOUT */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "aif3"), /* DIN */ SUNXI_FUNCTION(0x3, "pcm1"), /* DIN */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */ /* HOLE */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "twi0"), /* SCK */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PH_EINT0 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "twi0"), /* SDA */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PH_EINT1 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "twi1"), /* SCK */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PH_EINT2 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "twi1"), /* SDA */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PH_EINT3 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart3"), /* TX */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PH_EINT4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart3"), /* RX */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PH_EINT5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart3"), /* RTS */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PH_EINT6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "uart3"), /* CTS */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PH_EINT7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "spdif0"), /* OUT */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PH_EINT8 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PH_EINT9 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mic0"), /* CLK */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PH_EINT10 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mic0"), /* DATA */ SUNXI_FUNCTION(0x7, "io_disabled"), SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PH_EINT11 */ }; #define IRQ_BANK_NUM 3 static const unsigned sun50iw1p1_irq_bank_base[IRQ_BANK_NUM] = {0}; static const struct sunxi_pinctrl_desc sun50iw1p1_pinctrl_data = { .pins = sun50iw1p1_pins, .npins = ARRAY_SIZE(sun50iw1p1_pins), .irq_banks = IRQ_BANK_NUM, .irq_bank_base = sun50iw1p1_irq_bank_base, }; static int sun50iw1p1_pinctrl_probe(struct platform_device *pdev) { pr_warn("[%s][%d]\n", __func__, __LINE__); return sunxi_pinctrl_init(pdev, &sun50iw1p1_pinctrl_data); } static struct of_device_id sun50iw1p1_pinctrl_match[] = { { .compatible = "allwinner,sun50i-pinctrl", }, {} }; MODULE_DEVICE_TABLE(of, sun50iw1p1_pinctrl_match); static struct platform_driver sun50iw1p1_pinctrl_driver = { .probe = sun50iw1p1_pinctrl_probe, .driver = { .name = "sun50i-pinctrl", .owner = THIS_MODULE, .of_match_table = sun50iw1p1_pinctrl_match, }, }; static int __init sun50iw1p1_pio_init(void) { int ret; ret = platform_driver_register(&sun50iw1p1_pinctrl_driver); if (ret) { pr_err("register sun50iw1p1 pio controller failed\n"); return -EINVAL; } return 0; } postcore_initcall(sun50iw1p1_pio_init); MODULE_AUTHOR("Jackie Hwang"); MODULE_AUTHOR("Chen-Yu Tsai "); MODULE_AUTHOR("Maxime Ripard