/* * sound\soc\sunxi\sun8iw11codec.h * (C) Copyright 2014-2016 * allwinner Technology Co., Ltd. * huangxin * * some simple description for this code * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * */ #ifndef _SUN8IW17_CODEC_H #define _SUN8IW17_CODEC_H #define SUNXI_DAC_DPC 0x00 #define SUNXI_DAC_FIFO_CTR 0x10 #define SUNXI_DAC_FIFO_STA 0x14 /* left blank */ #define SUNXI_DAC_TXDATA 0X20 #define SUNXI_DAC_CNT 0x24 #define SUNXI_DAC_DG 0x28 #define SUNXI_ADC_FIFO_CTR 0x30 #define SUNXI_ADC_FIFO_STA 0x38 #define SUNXI_ADC_RXDATA 0x40 /* left blank */ #define SUNXI_ADC_CNT 0x44 #define SUNXI_ADC_DG 0x4C /*left blank */ #define SUNXI_DAC_DAP_CTR 0xf0 #define SUNXI_ADC_DAP_CTR 0xf8 #define SUNXI_ADC_DRC_HHPFC 0x200 #define SUNXI_ADC_DRC_LHPFC 0x204 /* Analog register base - Digital register base */ /*SUNXI_PR_CFG is to tear the acreg and dcreg, it is of no real meaning*/ #define SUNXI_PR_CFG 0x300 #define SUNXI_LOMIX_SRC (SUNXI_PR_CFG + 0x01) #define SUNXI_ROMIX_SRC (SUNXI_PR_CFG + 0x02) #define SUNXI_DAC_PA_SRC (SUNXI_PR_CFG + 0x03) #define SUNXI_LINEIN_GCTR (SUNXI_PR_CFG + 0x04) #define SUNXI_LINEINLR_MIC1_GCTR (SUNXI_PR_CFG + 0x05) #define SUNXI_MIC2_MIC3_GCTR (SUNXI_PR_CFG + 0x06) #define SUNXI_PHONEOUT_CTR (SUNXI_PR_CFG + 0x07) #define SUNXI_PHOMIX_MICBIAS_CTR (SUNXI_PR_CFG + 0x08) #define SUNXI_LINEOUT_VOL (SUNXI_PR_CFG + 0x09) #define SUNXI_MIC1B_LINEOUT_CTR (SUNXI_PR_CFG + 0x0A) #define SUNXI_MIC2B_MIC3B (SUNXI_PR_CFG + 0x0B) /* left blank */ #define SUNXI_LADCMIX_SRC (SUNXI_PR_CFG + 0x0C) #define SUNXI_RADCMIX_SRC (SUNXI_PR_CFG + 0x0D) #define SUNXI_XADCMIX_SRC (SUNXI_PR_CFG + 0x0E) #define SUNXI_ADC_AP_EN (SUNXI_PR_CFG + 0x0F) #define SUNXI_OP_CTR0 (SUNXI_PR_CFG + 0x10) #define SUNXI_OP_CTR1 (SUNXI_PR_CFG + 0x11) #define SUNXI_USB_BIAS_CTR (SUNXI_PR_CFG + 0x12) #define SUNXI_ADC_FUN_CTR (SUNXI_PR_CFG + 0x13) #define SUNXI_BIAS_DA16_CAL_CTR (SUNXI_PR_CFG + 0x14) #define SUNXI_DA16_CALI_DATA (SUNXI_PR_CFG + 0x15) /* left blank */ #define SUNXI_BIAS_CALI_DATA (SUNXI_PR_CFG + 0x17) #define SUNXI_BIAS_CALI_SET (SUNXI_PR_CFG + 0x18) /* SUNXI_DAC_DPC:0x00 */ #define EN_DAC 31 #define MODQU 25 #define DWA_EN 24 #define HPF_EN 18 #define DVOL 12 #define HUB_EN 0 /* SUNXI_DAC_FIFO_CTR:0x10 */ #define DAC_FS 29 #define FIR_VER 28 #define SEND_LASAT 26 #define FIFO_MODE 24 #define DAC_DRQ_CLR_CNT 21 #define TX_TRIG_LEVEL 8 #define DAC_MONO_EN 6 #define TX_SAMPLE_BITS 5 #define DAC_DRQ_EN 4 #define DAC_IRQ_EN 3 #define FIFO_UNDERRUN_IRQ_EN 2 #define FIFO_OVERRUN_IRQ_EN 1 #define FIFO_FLUSH 0 /* SUNXI_DAC_FIFO_STA:0x14 */ #define TX_EMPTY 23 #define TXE_CNT 8 #define TXE_INT 3 #define TXU_INT 2 #define TXO_INT 1 /* SUNXI_ADC_FIFO_CTR:0x30 */ #define ADC_FS 29 #define EN_AD 28 #define ADCFDT 26 #define ADCDFEN 25 #define RX_FIFO_MODE 24 #define RX_SAMPLE_BITS 16 #define ADC_CHAN_SEL 12 #define RX_FIFO_TRG_LEVEL 4 #define ADC_DRQ_EN 3 #define ADC_IRQ_EN 2 #define ADC_OVERRUN_IRQ_EN 1 #define ADC_FIFO_FLUSH 0 /* SUNXI_ADC_FIFO_STA:0x38 */ #define RXA 23 #define RXA_CNT 8 #define RXA_INT 3 #define RXO_INT 1 /* SUNXI_DAC_DAP_CTR:0xf0 */ #define DDAP_EN 31 #define DDAP_DRC_EN 29 #define DDAP_HPF_EN 28 /* SUNXI_ADC_DAP_CTR:0xf8 */ #define ADC_DAP0_EN 31 #define ADC_DRC0_EN 29 #define ADC_HPF0_EN 28 #define ADC_DAP1_EN 27 #define ADC_DRC1_EN 25 #define ADC_HPF1_EN 24 /*SUNXI_ADC_DRC_HHPFC : 0x200*/ #define ADC_HHPF_CONF 0 /*SUNXI_ADC_DRC_LHPFC : 0x204*/ #define ADC_LHPF_CONF 0 /* SUNXI_PR_CFG:0x07010280 */ #define AC_PR_RST 28 #define AC_PR_RW 24 #define AC_PR_ADDR 16 #define ADDA_PR_WDAT 8 #define ADDA_PR_RDAT 0 /* SUNXI_LOMIX_SRC:0x01 */ #define LMIXMUTE 0 #define LMIX_MIC1_BST 6 #define LMIX_MIC2_BST 5 #define LMIX_MIC3_BST 4 #define LMIX_LINEINLR 3 #define LMIX_LINEINL 2 #define LMIX_LDAC 1 #define LMIX_RDAC 0 /* SUNXI_ROMIX_SRC:0x02 */ #define RMIXMUTE 0 #define RMIX_MIC1_BST 6 #define RMIX_MIC2_BST 5 #define RMIX_MIC3_BST 4 #define RMIX_LINEINLR 3 #define RMIX_LINEINR 2 #define RMIX_RDAC 1 #define RMIX_LDAC 0 /* SUNXI_DAC_PA_SRC:0x03 */ #define DACAREN 7 #define DACALEN 6 #define RMIXEN 5 #define LMIXEN 4 /* SUNXI_LINEIN_GCTR:0x04 */ #define LINEINLG 4 #define LINEINRG 0 /* SUNXI_LINEINLR_MIC1_GCTR:0x05 */ #define LINEING 4 #define MIC1_GAIN 0 /* SUNXI_MIC2_MIC3_GCTR:0x06 */ #define MIC2_GAIN 4 #define MIC3_GAIN 0 /* SUNXI_PHONEOUT_CTR:0x07 */ #define PHONEOUTEN 3 #define PHONEOUTG 0 /* SUNXI_PHOMIX_MICBIAS_CTR:0x08 */ #define MMICBIASEN 6 #define PHOMIXMUTE 0 #define PH0MIX_LINEINLR 5 #define PHOMIX_MIC3_BST 4 #define PHOMIX_MIC1_BST 3 #define PHOMIX_MIC2_BST 2 #define PHOMIX_ROUT_MIX 1 #define PHOMIX_LOUT_MIX 0 /* SUNXI_LINEOUT_VOL:0x09 */ #define LINEOUT_VOL 3 #define LINEIN_BOOST 0 /* SUNXI_MIC1B_LINEOUT_CTR:0x0A*/ #define LINEOUTL_EN 7 #define LINEOUTR_EN 6 #define LINEOUTL_SRC 5 #define LINEOUTR_SRC 4 #define MIC1AMPEN 3 #define MIC1BOOST 0 /* SUNXI_MIC2B_MIC3B:0x0B*/ #define MIC2AMPEN 7 #define MIC2BOOST 4 #define MIC3AMPEN 3 #define MIC3BOOST 0 /* SUNXI_LADCMIX_SRC:0x0C */ #define LADCMIXMUTE 0 #define LADC_MIC1_BST 6 #define LADC_MIC2_BST 5 #define LADC_MIC3_BST 4 #define LADC_LINEINLR 3 #define LADC_LINEINL 2 #define LADC_LOUT_MIX 1 #define LADC_ROUT_MIX 0 /* SUNXI_RADCMIX_SRC:0x0D */ #define RADCMIXMUTE 0 #define RADC_MIC1_BST 6 #define RADC_MIC2_BST 5 #define RADC_MIC3_BST 4 #define RADC_LINEINLR 3 #define RADC_LINEINR 2 #define RADC_ROUT_MIX 1 #define RADC_LOUT_MIX 0 /* SUNXI_XADCMIX_SRC:0x0E */ #define XADCMIXMUTE 0 #define XADC_MIC1_BST 6 #define XADC_MIC2_BST 5 #define XADC_MIC3_BST 4 #define XADC_LINEINLR 3 #define XADC_ROUT_MIX 1 #define XADC_LOUT_MIX 0 /* SUNXI_ADC_AP_EN:0x0F */ #define ADCREN 7 #define ADCLEN 6 #define ADCXEN 5 #define ADCG 0 /* SUNXI_OP_CTR0:0x10 */ #define OPADC1_BIAS_CUR 4 #define OPADC2_BIAS_CUR 2 #define OPAAF_BIAS_CUR 0 /* SUNXI_OP_CTR1:0x11 */ #define OPMIC_BIAS_CUR 6 #define OPVR_BIAS_CUR 4 #define OPDAC_BIAS_CUR 2 #define OPMIX_BIAS_CUR 0 /* SUNXI_USB_BIAS_CTR:0x12 */ #define USB_BIAS_CUR 0 /* SUNXI_ADC_FUN_CTR:0x13 */ #define MMIC_BIAS_CHOP_EN 7 #define MMIC_BIAS_CHOP_SRC 5 #define DITHER 4 #define DITHER_CLK_SEL 2 #define BIHE_CTRL 0 /* SUNXI_BIAS_DA16_CAL_CTR:0x14*/ #define PA_SPEED_SELECT 7 #define CUR_TEST_SEL 6 #define BIAS_DA16_CLK_SEL 4 #define BIAS_CAL_MODE_SEL 3 #define BIAS_DA16_CAL_CTRL 2 #define BIAS_CAL_VER 1 /* SUNXI_BIAS_CALI_DATA:0x17*/ #define BIAS_CALI 0 /* SUNXI_BIAS_CALI_SET:0x18*/ #define BIAS_VERIFY 0 #endif /* __SUN8IW17_CODEC_H */