/* Allwinner SoCs display driver. * * Copyright (c) 2017 Allwinnertech Co., Ltd. * * Header fle for Display driver on sunxi platform * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef __DRV_DISPLAY_H__ #define __DRV_DISPLAY_H__ typedef struct { unsigned char alpha; unsigned char red; unsigned char green; unsigned char blue; } disp_color_info; typedef struct { int x; int y; unsigned int width; unsigned int height; } disp_window; typedef struct { unsigned int width; unsigned int height; } disp_size; typedef struct { int x; int y; } disp_position; typedef enum { DISP_FORMAT_ARGB_8888 = 0x00, /* MSB A-R-G-B LSB */ DISP_FORMAT_ABGR_8888 = 0x01, DISP_FORMAT_RGBA_8888 = 0x02, DISP_FORMAT_BGRA_8888 = 0x03, DISP_FORMAT_XRGB_8888 = 0x04, DISP_FORMAT_XBGR_8888 = 0x05, DISP_FORMAT_RGBX_8888 = 0x06, DISP_FORMAT_BGRX_8888 = 0x07, DISP_FORMAT_RGB_888 = 0x08, DISP_FORMAT_BGR_888 = 0x09, DISP_FORMAT_RGB_565 = 0x0a, DISP_FORMAT_BGR_565 = 0x0b, DISP_FORMAT_ARGB_4444 = 0x0c, DISP_FORMAT_ABGR_4444 = 0x0d, DISP_FORMAT_RGBA_4444 = 0x0e, DISP_FORMAT_BGRA_4444 = 0x0f, DISP_FORMAT_ARGB_1555 = 0x10, DISP_FORMAT_ABGR_1555 = 0x11, DISP_FORMAT_RGBA_5551 = 0x12, DISP_FORMAT_BGRA_5551 = 0x13, /* SP: semi-planar, P:planar, I:interleaved * UVUV: U in the LSBs; VUVU: V in the LSBs */ DISP_FORMAT_YUV444_I_AYUV = 0x40, /* MSB A-Y-U-V LSB */ DISP_FORMAT_YUV444_I_VUYA = 0x41, /* MSB V-U-Y-A LSB */ DISP_FORMAT_YUV422_I_YVYU = 0x42, /* MSB Y-V-Y-U LSB */ DISP_FORMAT_YUV422_I_YUYV = 0x43, /* MSB Y-U-Y-V LSB */ DISP_FORMAT_YUV422_I_UYVY = 0x44, /* MSB U-Y-V-Y LSB */ DISP_FORMAT_YUV422_I_VYUY = 0x45, /* MSB V-Y-U-Y LSB */ DISP_FORMAT_YUV444_P = 0x46, /* MSB P3-2-1-0 LSB, YYYY UUUU VVVV */ DISP_FORMAT_YUV422_P = 0x47, /* MSB P3-2-1-0 LSB YYYY UU VV */ DISP_FORMAT_YUV420_P = 0x48, /* MSB P3-2-1-0 LSB YYYY U V */ DISP_FORMAT_YUV411_P = 0x49, /* MSB P3-2-1-0 LSB YYYY U V */ DISP_FORMAT_YUV422_SP_UVUV = 0x4a, /* MSB V-U-V-U LSB */ DISP_FORMAT_YUV422_SP_VUVU = 0x4b, /* MSB U-V-U-V LSB */ DISP_FORMAT_YUV420_SP_UVUV = 0x4c, DISP_FORMAT_YUV420_SP_VUVU = 0x4d, DISP_FORMAT_YUV411_SP_UVUV = 0x4e, DISP_FORMAT_YUV411_SP_VUVU = 0x4f, DISP_FORMAT_YUV422_SP_TILE_UVUV = 0x50, DISP_FORMAT_YUV422_SP_TILE_VUVU = 0x51, DISP_FORMAT_YUV420_SP_TILE_UVUV = 0x52, DISP_FORMAT_YUV420_SP_TILE_VUVU = 0x53, DISP_FORMAT_YUV411_SP_TILE_UVUV = 0x54, DISP_FORMAT_YUV411_SP_TILE_VUVU = 0x55, DISP_FORMAT_YUV422_SP_TILE_128X32_UVUV = 0x56, DISP_FORMAT_YUV422_SP_TILE_128X32_VUVU = 0x57, DISP_FORMAT_YUV420_SP_TILE_128X32_UVUV = 0x58, DISP_FORMAT_YUV420_SP_TILE_128X32_VUVU = 0x59, DISP_FORMAT_YUV411_SP_TILE_128X32_UVUV = 0x5a, DISP_FORMAT_YUV411_SP_TILE_128X32_VUVU = 0x5b, } disp_pixel_format; typedef enum { DISP_3D_SRC_MODE_TB = 0x0, /* top bottom */ DISP_3D_SRC_MODE_FP = 0x1, /* frame packing */ DISP_3D_SRC_MODE_SSF = 0x2, /* side by side full */ DISP_3D_SRC_MODE_SSH = 0x3, /* side by side half */ DISP_3D_SRC_MODE_LI = 0x4, /* line interleaved */ } disp_3d_src_mode; typedef enum { DISP_3D_OUT_MODE_CI_1 = 0x5, /* column interlaved 1 */ DISP_3D_OUT_MODE_CI_2 = 0x6, /* column interlaved 2 */ DISP_3D_OUT_MODE_CI_3 = 0x7, /* column interlaved 3 */ DISP_3D_OUT_MODE_CI_4 = 0x8, /* column interlaved 4 */ DISP_3D_OUT_MODE_LIRGB = 0x9, /* line interleaved rgb */ DISP_3D_OUT_MODE_TB = 0x0, /* top bottom */ DISP_3D_OUT_MODE_FP = 0x1, /* frame packing */ DISP_3D_OUT_MODE_SSF = 0x2, /* side by side full */ DISP_3D_OUT_MODE_SSH = 0x3, /* side by side half */ DISP_3D_OUT_MODE_LI = 0x4, /* line interleaved */ DISP_3D_OUT_MODE_FA = 0xa, /* field alternative */ } disp_3d_out_mode; typedef enum { DISP_BT601 = 0, DISP_BT709 = 1, DISP_YCC = 2, DISP_VXYCC = 3, } disp_cs_mode; typedef enum { DISP_COLOR_RANGE_16_255 = 0, DISP_COLOR_RANGE_0_255 = 1, DISP_COLOR_RANGE_16_235 = 2, } disp_color_range; typedef enum { DISP_OUTPUT_TYPE_NONE = 0, DISP_OUTPUT_TYPE_LCD = 1, DISP_OUTPUT_TYPE_TV = 2, DISP_OUTPUT_TYPE_HDMI = 4, DISP_OUTPUT_TYPE_VGA = 8, } disp_output_type; typedef enum { DISP_TV_MOD_480I = 0, DISP_TV_MOD_576I = 1, DISP_TV_MOD_480P = 2, DISP_TV_MOD_576P = 3, DISP_TV_MOD_720P_50HZ = 4, DISP_TV_MOD_720P_60HZ = 5, DISP_TV_MOD_1080I_50HZ = 6, DISP_TV_MOD_1080I_60HZ = 7, DISP_TV_MOD_1080P_24HZ = 8, DISP_TV_MOD_1080P_50HZ = 9, DISP_TV_MOD_1080P_60HZ = 0xa, DISP_TV_MOD_1080P_24HZ_3D_FP = 0x17, DISP_TV_MOD_720P_50HZ_3D_FP = 0x18, DISP_TV_MOD_720P_60HZ_3D_FP = 0x19, DISP_TV_MOD_1080P_25HZ = 0x1a, DISP_TV_MOD_1080P_30HZ = 0x1b, DISP_TV_MOD_PAL = 0xb, DISP_TV_MOD_PAL_SVIDEO = 0xc, DISP_TV_MOD_NTSC = 0xe, DISP_TV_MOD_NTSC_SVIDEO = 0xf, DISP_TV_MOD_PAL_M = 0x11, DISP_TV_MOD_PAL_M_SVIDEO = 0x12, DISP_TV_MOD_PAL_NC = 0x14, DISP_TV_MOD_PAL_NC_SVIDEO = 0x15, DISP_TV_MOD_3840_2160P_30HZ = 0x1c, DISP_TV_MOD_3840_2160P_25HZ = 0x1d, DISP_TV_MOD_3840_2160P_24HZ = 0x1e, DISP_TV_MODE_NUM = 0x1f, } disp_tv_mode; typedef enum { DISP_LCDC_SRC_DE_CH1 = 0, DISP_LCDC_SRC_DE_CH2 = 1, DISP_LCDC_SRC_DMA888 = 2, DISP_LCDC_SRC_DMA565 = 3, DISP_LCDC_SRC_WHITE = 4, DISP_LCDC_SRC_BLACK = 5, DISP_LCDC_SRC_BLUE = 6, } disp_lcd_src; typedef enum { DISP_LAYER_WORK_MODE_NORMAL = 0, /* normal work mode */ DISP_LAYER_WORK_MODE_SCALER = 4, /* scaler work mode */ } disp_layer_mode; typedef enum { DISP_VIDEO_NATUAL = 0, DISP_VIDEO_SOFT = 1, DISP_VIDEO_VERYSOFT = 2, DISP_VIDEO_SHARP = 3, DISP_VIDEO_VERYSHARP = 4 } disp_video_smooth_level; typedef enum { DISP_EXIT_MODE_CLEAN_ALL = 0, DISP_EXIT_MODE_CLEAN_PARTLY = 1,/* only clean interrupt temply */ } disp_exit_mode; typedef enum { DISP_ENHANCE_MODE_RED = 0x0, DISP_ENHANCE_MODE_GREEN = 0x1, DISP_ENHANCE_MODE_BLUE = 0x2, DISP_ENHANCE_MODE_CYAN = 0x3, DISP_ENHANCE_MODE_MAGENTA = 0x4, DISP_ENHANCE_MODE_YELLOW = 0x5, DISP_ENHANCE_MODE_FLESH = 0x6, DISP_ENHANCE_MODE_STANDARD = 0x7, DISP_ENHANCE_MODE_VIVID = 0x8, DISP_ENHANCE_MODE_SCENERY = 0xa, } disp_enhance_mode; typedef enum { DISP_OUT_CSC_TYPE_LCD = 0, DISP_OUT_CSC_TYPE_TV = 1, DISP_OUT_CSC_TYPE_HDMI_YUV = 2, DISP_OUT_CSC_TYPE_SAT = 3, DISP_OUT_CSC_TYPE_HDMI_RGB = 4, } disp_out_csc_type; typedef enum { DISP_HWC_MOD_32X32_8BPP = 0, DISP_HWC_MOD_64X64_2BPP = 1, DISP_HWC_MOD_64X32_4BPP = 2, DISP_HWC_MOD_32X64_4BPP = 3, } disp_cursor_mode; typedef enum { DISP_MOD_DE = 0, DISP_MOD_DEVICE = 1, /* for timing controller common module */ DISP_MOD_FE0 = 3, DISP_MOD_FE1 = 4, DISP_MOD_FE2 = 5, DISP_MOD_BE0 = 6, DISP_MOD_BE1 = 7, DISP_MOD_BE2 = 8, DISP_MOD_LCD0 = 9, DISP_MOD_LCD1 = 10, DISP_MOD_LCD2 = 11, DISP_MOD_TVE0 = 12, DISP_MOD_TVE1 = 13, DISP_MOD_TVE2 = 14, DISP_MOD_DEU0 = 15, DISP_MOD_DEU1 = 16, DISP_MOD_DEU2 = 17, DISP_MOD_CMU0 = 18, DISP_MOD_CMU1 = 19, DISP_MOD_CMU2 = 20, DISP_MOD_DRC0 = 21, DISP_MOD_DRC1 = 22, DISP_MOD_DRC2 = 23, DISP_MOD_DSI0 = 24, DISP_MOD_DSI0_DPHY = 25, DISP_MOD_DSI1 = 26, DISP_MOD_DSI1_DPHY = 27, DISP_MOD_DSI2 = 28, DISP_MOD_DSI2_DPHY = 29, DISP_MOD_HDMI = 30, DISP_MOD_EDP = 31, DISP_MOD_TOP = 32, DISP_MOD_WB0 = 33, DISP_MOD_WB1 = 34, DISP_MOD_WB2 = 35, DISP_MOD_SAT0 = 35, DISP_MOD_SAT1 = 36, DISP_MOD_SAT2 = 37, DISP_MOD_NUM = 38, } disp_mod_id; typedef enum { LCD_IF_HV = 0, LCD_IF_CPU = 1, LCD_IF_LVDS = 3, LCD_IF_DSI = 4, LCD_IF_EDP = 5, LCD_IF_EXT_DSI = 6, } disp_lcd_if; typedef enum { LCD_HV_IF_PRGB_1CYC = 0, /* parallel hv */ LCD_HV_IF_SRGB_3CYC = 8, /* serial hv */ LCD_HV_IF_DRGB_4CYC = 10, /* Dummy RGB */ LCD_HV_IF_RGBD_4CYC = 11, /* RGB Dummy */ LCD_HV_IF_CCIR656_2CYC = 12, } disp_lcd_hv_if; typedef enum { LCD_HV_SRGB_SEQ_RGB_RGB = 0, LCD_HV_SRGB_SEQ_RGB_BRG = 1, LCD_HV_SRGB_SEQ_RGB_GBR = 2, LCD_HV_SRGB_SEQ_BRG_RGB = 4, LCD_HV_SRGB_SEQ_BRG_BRG = 5, LCD_HV_SRGB_SEQ_BRG_GBR = 6, LCD_HV_SRGB_SEQ_GRB_RGB = 8, LCD_HV_SRGB_SEQ_GRB_BRG = 9, LCD_HV_SRGB_SEQ_GRB_GBR = 10, } disp_lcd_hv_srgb_seq; typedef enum { LCD_HV_SYUV_SEQ_YUYV = 0, LCD_HV_SYUV_SEQ_YVYU = 1, LCD_HV_SYUV_SEQ_UYUV = 2, LCD_HV_SYUV_SEQ_VYUY = 3, } disp_lcd_hv_syuv_seq; typedef enum { LCD_HV_SYUV_FDLY_0LINE = 0, LCD_HV_SRGB_FDLY_2LINE = 1, /* ccir pal */ LCD_HV_SRGB_FDLY_3LINE = 2, /* ccir ntsc */ } disp_lcd_hv_syuv_fdly; typedef enum { LCD_CPU_IF_RGB666_18PIN = 0, LCD_CPU_IF_RGB666_9PIN = 10, LCD_CPU_IF_RGB666_6PIN = 12, LCD_CPU_IF_RGB565_16PIN = 8, LCD_CPU_IF_RGB565_8PIN = 14, } disp_lcd_cpu_if; typedef enum { LCD_TE_DISABLE = 0, LCD_TE_RISING = 1, LCD_TE_FALLING = 2, } disp_lcd_te; typedef enum { LCD_LVDS_IF_SINGLE_LINK = 0, LCD_LVDS_IF_DUAL_LINK = 1, } disp_lcd_lvds_if; typedef enum { LCD_LVDS_8bit = 0, LCD_LVDS_6bit = 1, } disp_lcd_lvds_colordepth; typedef enum { LCD_LVDS_MODE_NS = 0, LCD_LVDS_MODE_JEIDA = 1, } disp_lcd_lvds_mode; typedef enum { LCD_DSI_IF_VIDEO_MODE = 0, LCD_DSI_IF_COMMAND_MODE = 1, LCD_DSI_IF_BURST_MODE = 2, } disp_lcd_dsi_if; typedef enum { LCD_DSI_1LANE = 1, LCD_DSI_2LANE = 2, LCD_DSI_3LANE = 3, LCD_DSI_4LANE = 4, } disp_lcd_dsi_lane; typedef enum { LCD_DSI_FORMAT_RGB888 = 0, LCD_DSI_FORMAT_RGB666 = 1, LCD_DSI_FORMAT_RGB666P = 2, LCD_DSI_FORMAT_RGB565 = 3, } disp_lcd_dsi_format; typedef enum { LCD_FRM_BYPASS = 0, LCD_FRM_RGB666 = 1, LCD_FRM_RGB565 = 2, } disp_lcd_frm; typedef enum { LCD_CMAP_B0 = 0x0, LCD_CMAP_G0 = 0x1, LCD_CMAP_R0 = 0x2, LCD_CMAP_B1 = 0x4, LCD_CMAP_G1 = 0x5, LCD_CMAP_R1 = 0x6, LCD_CMAP_B2 = 0x8, LCD_CMAP_G2 = 0x9, LCD_CMAP_R2 = 0xa, LCD_CMAP_B3 = 0xc, LCD_CMAP_G3 = 0xd, LCD_CMAP_R3 = 0xe, } disp_lcd_cmap_color; /* disp_fb_info - image buffer info * * @addr: buffer address for each plane * @size: size, unit:pixels * @format: pixel format * @cs_mode: color space * @b_trd_src: if trd image buffer * @trd_mode: trd mode * @trd_right_addr: the right-eye buffer address for each plane, * valid when frame-packing 3d buffer input * @pre_multiply: indicate the pixel use premultiplied alpha * @src_win: crop rectangle for buffer to be display */ typedef struct { unsigned int addr[3]; disp_size size; disp_pixel_format format; disp_cs_mode cs_mode; bool b_trd_src; disp_3d_src_mode trd_mode; unsigned int trd_right_addr[3]; bool pre_multiply; disp_window src_win; #if defined(CONFIG_HOMLET_PLATFORM) bool interlace; bool top_field_first; #endif #if 0 bool pre_frame_valid; #endif } disp_fb_info; /* disp_layer_info - layer info * * @mode: layer mode * @pipe: layer pipe,0/1 * @zorder: the zorder of layer, 0~max-layer-number * @alpha_mode: * 0: pixel alpha; * 1: global alpha * @alpha_value: global alpha value, valid when alpha_mode is not pixel alpha * @ck_enable: enable color key function * @screen_win: the rectangle on the screen for fb to be display * @fb: the framebuffer info related width the layer, valid when in buffer mode * @b_trd_out: indicate if 3d display output * @out_trd_mode: 3d output mode, valid when b_trd_out is true * @id: frame id, the user could get the frame-id display currently by * DISP_CMD_LAYER_GET_FRAME_ID ioctl */ typedef struct { disp_layer_mode mode; unsigned char pipe; unsigned char zorder; unsigned char alpha_mode; unsigned char alpha_value; bool ck_enable; disp_window screen_win; disp_fb_info fb; bool b_trd_out; disp_3d_out_mode out_trd_mode; unsigned int id; } disp_layer_info; /* * 0/1:always match; * 2:match if min<=color<=max; * 3:match if color>max or color