fix uart rx issue
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parent
401be2fa50
commit
d9bb8986ca
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@ -286,7 +286,6 @@ static int __init cpld_r311_probe(struct platform_device *pdev) {
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if (gpio_is_valid(gpionum)) {
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gpio_request(gpionum, "3v_ldo_en");
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gpio_direction_output(gpionum, 1);
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gpio_free(gpionum);
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printk("Set 3v_ldo_en(%d) success\n", gpionum);
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} else {
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printk("Set 3v_ldo_en fail\n");
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@ -225,6 +225,8 @@ static unsigned int sw_uart_handle_rx(struct sw_uart_port *sw_uport, unsigned in
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*/
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if (uart_handle_break(&sw_uport->port))
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goto ignore_char;
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if (lsr & SUNXI_UART_LSR_RXFIFOE)
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goto ignore_char;
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} else if (lsr & SUNXI_UART_LSR_PE)
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sw_uport->port.icount.parity++;
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else if (lsr & SUNXI_UART_LSR_FE)
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@ -1150,12 +1152,22 @@ static void sw_uart_set_termios(struct uart_port *port, struct ktermios *termios
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sw_uport->fcr = SUNXI_UART_FCR_RXTRG_1_2 | SUNXI_UART_FCR_TXTRG_1_2
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| SUNXI_UART_FCR_FIFO_EN;
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serial_out(port, sw_uport->fcr, SUNXI_UART_FCR);
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/*
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* if lcr & baud are changed, reset controller to disable transfer
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*/
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if (lcr != sw_uport->lcr || dll != sw_uport->dll || dlh != sw_uport->dlh) {
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/*SERIAL_DBG("LCR & BAUD changed, reset controller...\n");*/
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sw_uart_reset(sw_uport);
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}
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sw_uport->lcr = lcr;
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sw_uport->dll = dll;
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sw_uport->dlh = dlh;
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sw_uart_force_lcr(sw_uport, 50);
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/* clear rxfifo after set lcr & baud to discard redundant data */
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serial_out(port, sw_uport->fcr|SUNXI_UART_FCR_RXFIFO_RST, SUNXI_UART_FCR);
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port->ops->set_mctrl(port, port->mctrl);
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sw_uport->ier = SUNXI_UART_IER_RLSI | SUNXI_UART_IER_RDI;
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@ -1 +1 @@
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Subproject commit d2c397aa21c5fccf9a621f893ca8441c450e893b
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Subproject commit cbf96ef8d15ebcc710d6f50c67c58484d3de9e3b
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