374 lines
14 KiB
C
374 lines
14 KiB
C
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#ifndef DTV_TSC_REGS_H
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#define DTV_TSC_REGS_H
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#include "tsc_type.h"
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// 1689
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#define TSC_BASE 0x01c04000
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#define TSC_OFFSET 0x0
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#define TSG_OFFSET 0x40
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#define TSF0_OFFSET 0x80
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#define TSD_OFFSET 0x180
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//#define TSF1_OFFSET 0x100
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//read and set register
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#define SetValue(X, value) do { \
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volatile void *p = (void *)(&(X)); \
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(*(uint32_t *)p) = (value); \
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} while(0)
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#define GetValue(X, value) do { \
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volatile void *p = (void *)(&(X)); \
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(value) = (*(uint32_t *)p); \
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} while(0)
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//**************************** tsc register define ****************************/
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//* tsc contrl register.
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typedef struct TSC00_CTRL_REG {
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volatile unsigned enable :1;
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volatile unsigned reset :1;
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volatile unsigned reserved :30;
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} tsc00_ctrl_reg_t;
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//* tsc status register.
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typedef struct TSC04_STATUS_REG {
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volatile unsigned reserved :32;
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} tsc04_status_reg_t;
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//* tsc port control register.
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typedef struct TSC10_PORT_CTRL_REG {
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volatile unsigned port0_input_ctrl :1; //* 0: spi, 1: ssi.
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//uint32_t port1_input_ctrl :1; //* 0: spi, 1: ssi.
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volatile unsigned reserved :31; //* 0: spi, 1: ssi.
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} tsc10_port_ctrl_reg_t;
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//* tsc port parameter register.
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typedef struct TSC14_PORT_PARAM_REG {
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volatile unsigned port0_psync_polarity :1; //* 0: high level active, 1: low level active;
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volatile unsigned port0_dvalid_polarity :1; //* 0: high level active, 1: low level active;
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volatile unsigned port0_error_polarity :1; //* 0: high level active, 1: low level active;
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volatile unsigned port0_clock_polarity :1; //* 0: rise edge capture, 1: fall edge capture;
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volatile unsigned port0_ssi_data_order :1; //* 0: MSB first for one byte data, 1: LSB first for one byte data;
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volatile unsigned reserved :3;
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volatile unsigned reserved1 :8;
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volatile unsigned reserved2 :16;
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} tsc14_port_param_reg_t;
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//* tsc tsf input multeplex control register.
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typedef struct TSC20_IN_MUX_CTRL_REG {
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volatile unsigned tsf0_in_mux_ctrl :4; //* 0: from tsg, 1: from port 0, others: reserved;
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volatile unsigned reserved :28;
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} tsc20_in_mux_ctrl_reg_t;
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//* tsc tsf output multiplex control register.
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typedef struct TSC28_OUT_MUX_CTRL_REG {
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volatile unsigned reserved :32;
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} tsc28_out_mux_ctrl_reg_t;
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//**************************** tsg register define ****************************/
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//* tsg control register
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typedef struct TSG00_CTRL_REG {
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volatile unsigned start :1; //* write '1' to start tsg;
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volatile unsigned stop :1; //* write '1' to stop tsg;
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volatile unsigned pause :1; //* write '1' to pause or resume tsg;
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volatile unsigned reserved0 :5; //*
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volatile unsigned check_sync_byte :1; //* 0: disable, 1: enable, it will give an interrupt and go into pause state if unsync.
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volatile unsigned loop_mode_enable :1; //* 0: disable, 1: tsg buffer in loop back mode.
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volatile unsigned reserved1 :14; //*
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volatile unsigned tsg_status :2; //* 0: idle, 1: running, 2: pause;
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volatile unsigned reserved2 :6; //*
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} tsg00_ctrl_reg_t;
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//* tsg packet parameter register
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typedef struct TSG04_PKT_PARAM_REG {
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volatile unsigned pkt_size :2; //* packet size for tsg.0:188 bytes others:reserved
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volatile unsigned reserved0 :5; //*
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volatile unsigned sync_byte_pos :1; //* 0: the first byte is 0x47, 1: the fifth byte is 0x47.
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volatile unsigned reserved1 :8; //*
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volatile unsigned sync_byte_value :8; //* 0x47.
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volatile unsigned reserved2 :8; //*
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} tsg04_pkt_param_reg_t;
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//* tsg status register
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typedef struct TSG08_STATUS_REG {
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volatile unsigned err_sync_byte :1; //* find error sync byte case, write '1' to clear.
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volatile unsigned half_finish :1; //* half finished, write '1' to clear.
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volatile unsigned full_finish :1; //* full finished, write '1' to clear.
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volatile unsigned end :1; //* tsg end, write '1' to clear.
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volatile unsigned reserved0 :12; //*
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volatile unsigned err_sync_byte_intr_en :1; //* tsg error sync byte interrupt enable bit, 0: disable, 1: enable.
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volatile unsigned half_finish_intr_en :1; //* tsg half finish interrupt enable bit, 0: disable, 1: enable.
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volatile unsigned full_finish_intr_en :1; //* tsg full finish interrupt enable bit, 0: disable, 1: enable.
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volatile unsigned end_intr_en :1; //* tsg end interrupt enable bit, 0: diable, 1: enable.
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volatile unsigned reserved1 :12; //*
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} tsg08_status_reg_t;
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//* tsg clock control register
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typedef struct TSG0c_CLK_CTRL_REG {
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//* output frequency fo = (fi*(n+1))/(16*(d+1)), fi is the special input clock to tsc.
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volatile unsigned clock_divid_factor_d :16; //* clock divid factor d.
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volatile unsigned clock_divid_factor_n :16; //* clock divid factor n.
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} tsg0c_clk_ctrl_reg_t;
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//* tsg buffer base address register
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typedef struct TSG10_BUF_ADDR_REG {
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volatile unsigned addr :32; //* buffer base address, 16 bytes aligned.
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} tsg10_buf_addr_reg_t;
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//* tsg buffer size register
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typedef struct TSG14_BUF_SIZE_REG {
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volatile unsigned size :24; //* buffer size, 16 bytes aligned.
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volatile unsigned reserved :8; //*
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} tsg14_buf_size_reg_t;
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//* tsg buffer pointer register
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typedef struct TSG18_BUF_PTR_REG {
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volatile unsigned cur_pos :24; //* tsg current sending position.
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volatile unsigned reserved :8; //*
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} tsg18_buf_ptr_reg_t;
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//**************************** tsf register define ****************************/
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//* tsf control register
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typedef struct TSF00_CTRL_REG {
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volatile unsigned reset :1; //* tsf global soft reset.
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volatile unsigned mode :1; //* no use currently.
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volatile unsigned enable :1; //* tsf enable control.
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volatile unsigned reserve :29;
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} tsf00_ctrl_reg_t;
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//* tsf packet parameter register
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typedef struct TSF04_PKT_PARAM_REG {
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volatile unsigned pkt_size :2; //* packet size, 0:188, 1:192, 2:204;
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volatile unsigned reserved0 :5; //*
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volatile unsigned sync_byte_pos :1; //* 0: the first byte, 1: the fifth byte.
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volatile unsigned sync_method :2; //* 0: byte psync signal, 1: by sync byte, 2: by both psync and sync byte.
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volatile unsigned reserved1 :6; //*
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volatile unsigned sync_byte_value :8; //* 0x47
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volatile unsigned sync_pkt_threshold :4; //*
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volatile unsigned lost_sync_pkt_threshold :4; //*
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} tsf04_pkt_param_reg_t;
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//* tsf status register
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typedef struct TSF08_STATUS_REG {
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volatile unsigned dma_status :1; //* it is a global status of all 32 channels
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volatile unsigned overlap_status :1; //* it is a global status of all 32 channels
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volatile unsigned pcr_found :1; //* a PCR packet is found, write '1' to clear
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volatile unsigned fifo_overrun :1; //* tsf internal fifo overrun
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volatile unsigned reserved0 :12; //*
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volatile unsigned dma_intr_en :1; //* 0: disable, 1: enable
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volatile unsigned overlap_intr_en :1; //* 0: disable, 1: enable
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volatile unsigned pcr_intr_en :1; //* 0: disable, 1: enable
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volatile unsigned fifo_overrun_intr_en :1; //* 0: disable, 1: enable
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volatile unsigned reserved1 :12; //*
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} tsf08_status_reg_t;
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//* tsf dma interrupt enable register
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typedef struct TSF10_DMA_INTR_EN_REG {
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volatile unsigned en_ctrl_bits; //* dma intrrupt enable control bits, bits 0~31 for channel 0~31.
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} tsf10_dma_intr_en_reg_t;
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//* tsf overlap interrupt enable register
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typedef struct TSF14_OVERLAP_INTR_EN_REG {
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volatile unsigned en_ctrl_bits; //* overlap interrupt enable control bits, bits 0~31 for channel 0~31.
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} tsf14_overlap_intr_en_reg_t;
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//* tsf dma interrupt status register
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typedef struct TSF18_DMA_STATUS_REG {
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volatile unsigned dma_status; //* dma interrupt status, bits 0~31 for channel 0~31, write 1 to clear.
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} tsf18_dma_status_reg_t;
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//* tsf overlap interrupt status register
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typedef struct TSF1c_OVERLAP_STATUS_REG {
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volatile unsigned overlap_status; //* overlap interrupt status, bits 0~31 for channel 0~31, write 1 to clear.
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} tsf1c_overlap_stauts_reg_t;
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//* tsf pcr control register
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typedef struct TSF20_PCR_CTRL_REG {
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volatile unsigned pcr_lsb_bit :1; //* pcr contest LSB 1 bit.
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volatile unsigned reserved0 :7; //*
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volatile unsigned pcr_chan_idx :5; //* channel index for detecting PCR packet.
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volatile unsigned reserved1 :3; //*
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volatile unsigned pcr_detect_en :1; //* pcr detecting enable
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volatile unsigned reserved2 :15; //*
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} tsf20_pcr_ctrl_reg_t;
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//* tsf pcr data register
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typedef struct TSF24_PCR_DATA_REG {
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volatile unsigned pcr_value; //* pcr bit 32~1
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} tsf24_pcr_data_reg_t;
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//* tsf channel enable register
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typedef struct TSF30_CHAN_EN_REG {
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volatile unsigned filter_en_ctrl_bits; //* 0: disable, 1: enable, bit 0~31 for channel 0~31.
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} tsf30_chan_en_reg_t;
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//* tsf channel pes enable register
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typedef struct TSF34_CHAN_PES_EN_REG {
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volatile unsigned pes_en_ctrl_bits; //* 0: disable, 1: enable, bit 0~31 for channel 0~31.
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} tsf34_chan_pes_en_reg_t;
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//* tsf channel descramble enable register
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typedef struct TSF38_CHAN_DESCRAMBLE_EN_REG {
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volatile unsigned descramble_en_ctrl_bits;
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} tsf38_chan_descramble_en_reg_t;
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//* tsf channel index register
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typedef struct TSF3c_CHAN_IDX_REG {
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volatile unsigned chan_idx :5; //* when you are writing pid, you have to write this reg to tell which
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volatile unsigned reserved0 :27; //* channel you are setting.
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} tsf3c_chan_idx_reg_t;
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//* tsf channel control register
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typedef struct TSF40_CHAN_CTRL_REG {
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volatile unsigned reserved0;
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} tsf40_chan_ctrl_reg_t;
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//* tsf channel status register
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typedef struct TSF44_CHAN_STATUS_REG {
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volatile unsigned reserved0;
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} tsf44_chan_status_reg_t;
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//* tsf channel CW index register
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typedef struct TSF48_CHAN_CW_IDX_REG {
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volatile unsigned related_ctrl_word_idx :3; //*
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volatile unsigned reserved :29; //*
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} tsf48_chan_cw_idx_reg_t;
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//* tsf channel pid register
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typedef struct TSF4c_CHAN_PID_REG {
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volatile unsigned pid :16; //* channel pid.
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volatile unsigned mask :16; //* pid mask.
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} tsf4c_chan_pid_reg_t;
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//* tsf channel buffer base address register
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typedef struct TSF50_CHAN_BUF_ADDR_REG {
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volatile unsigned addr :32; //* data buffer base address for channel
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} tsf50_chan_buf_addr_reg_t;
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//* tsf channel buffer size register
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typedef struct TSF54_CHAN_BUF_SIZE_REG {
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volatile unsigned size :21; //* the exact buffer size is N+16 bytes.
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volatile unsigned reserved0 :3; //* the size should be 16 bytes aligned.
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volatile unsigned dma_intr_threshold :2; //* 0: 1/2, 1: 1/4, 2: 1/8, 3: 1/16.
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volatile unsigned reserved1 :6; //*
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} tsf54_chan_buf_size_reg_t;
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//* tsf channel buffer write pointer register
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typedef struct TSF58_CHAN_WRITE_POS_REG {
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volatile unsigned wt_pos :21; //* data buffer write pos.
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volatile unsigned reserved0 :11; //*
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} tsf58_chan_wt_pos_reg_t;
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//* tsf channel buffer read pointer register
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typedef struct TSF5c_CHAN_READ_POS_REG {
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volatile unsigned rd_pos :21; //* data buffer read pos.
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volatile unsigned reserved0 :11; //*
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} tsf5c_chan_rd_pos_reg_t;
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//**************************** tsd register define ****************************/
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//* tsdcontrol register
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typedef struct TSD00_CTRL_REG {
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volatile unsigned descramble_method :2; //* descramble arithmetic 0: DVD CSA V1.1 others: reserved;
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volatile unsigned reserved :30;
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} tsd00_ctrl_reg_t;
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//* tsd status register
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typedef struct TSD04_STATUS_REG {
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volatile unsigned reserved :32; //*
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} tsd04_status_reg_t;
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//* tsd control Word Index register
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typedef struct TSD1c_CW_INDEX_REG {
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volatile unsigned cw_internal_idx :2; //*
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volatile unsigned reserved0 :2; //*
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volatile unsigned cw_idx :3; //*
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volatile unsigned reserved1 :25; //*
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} tsd1c_cw_index_reg_t;
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//* tsd Control Word register
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typedef struct TSD20_CW_REG {
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volatile unsigned cw_content :32; //*
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} tsd20_cw_reg_t;
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//************************ ts controller register list ************************/
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typedef struct TSC_TSC_REG_LIST {
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volatile tsc00_ctrl_reg_t _00_ctrl;
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volatile tsc04_status_reg_t _04_status;
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volatile uint32_t _reserved0[2];
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volatile tsc10_port_ctrl_reg_t _10_port_ctrl;
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volatile tsc14_port_param_reg_t _14_port_param;
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volatile uint32_t _reserved1[2];
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volatile tsc20_in_mux_ctrl_reg_t _20_in_mux_ctrl;
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volatile uint32_t _reserved2[1];
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volatile tsc28_out_mux_ctrl_reg_t _28_out_mux_ctrl;
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volatile uint32_t _reserved3[5];
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} tsc_tsc_reg_list_t;
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typedef struct TSC_TSG_REG_LIST {
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volatile tsg00_ctrl_reg_t _00_ctrl;
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volatile tsg04_pkt_param_reg_t _04_pkt_param;
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volatile tsg08_status_reg_t _08_status;
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volatile tsg0c_clk_ctrl_reg_t _0c_clk_ctrl;
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volatile tsg10_buf_addr_reg_t _10_buf_addr;
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volatile tsg14_buf_size_reg_t _14_buf_size;
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volatile tsg18_buf_ptr_reg_t _18_buf_pos;
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volatile uint32_t _reserved0[9];
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} tsc_tsg_reg_list_t;
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typedef struct TSC_TSF_REG_LIST {
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volatile tsf00_ctrl_reg_t _00_ctrl;
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volatile tsf04_pkt_param_reg_t _04_pkt_param;
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volatile tsf08_status_reg_t _08_status;
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volatile uint32_t _reserved0[1];
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volatile tsf10_dma_intr_en_reg_t _10_dma_intr_en;
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volatile tsf14_overlap_intr_en_reg_t _14_overlap_intr_en;
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volatile tsf18_dma_status_reg_t _18_dma_status;
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volatile tsf1c_overlap_stauts_reg_t _1c_overlap_status;
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volatile tsf20_pcr_ctrl_reg_t _20_pcr_ctrl;
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volatile tsf24_pcr_data_reg_t _24_pcr_data;
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volatile uint32_t _reserved1[2];
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volatile tsf30_chan_en_reg_t _30_chan_en;
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volatile tsf34_chan_pes_en_reg_t _34_chan_pes_en;
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volatile tsf38_chan_descramble_en_reg_t _38_chan_descramble_en;
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volatile tsf3c_chan_idx_reg_t _3c_chan_idx;
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volatile tsf40_chan_ctrl_reg_t _40_chan_ctrl;
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volatile tsf44_chan_status_reg_t _44_chan_status;
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volatile tsf48_chan_cw_idx_reg_t _48_chan_cw_idx;
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volatile tsf4c_chan_pid_reg_t _4c_chan_pid;
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volatile tsf50_chan_buf_addr_reg_t _50_chan_buf_addr;
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volatile tsf54_chan_buf_size_reg_t _54_chan_buf_size;
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volatile tsf58_chan_wt_pos_reg_t _58_chan_wt_pos;
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volatile tsf5c_chan_rd_pos_reg_t _5c_chan_rd_pos;
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volatile uint32_t _reserved2[8];
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} tsc_tsf_reg_list_t;
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typedef struct TSC_TSD_REG_LIST {
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volatile tsd00_ctrl_reg_t _00_ctrl;
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volatile tsd04_status_reg_t _04_status;
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volatile uint32_t _reserved[5];
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volatile tsd1c_cw_index_reg_t _1c_cw_idx;
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volatile tsd20_cw_reg_t _20_cw;
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} tsc_tsd_reg_list_t;
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typedef struct TSC_REG_LIST {
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//* tsc registers.
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tsc_tsc_reg_list_t tsc;
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//* tsg registers.
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tsc_tsg_reg_list_t tsg;
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//* tsf0 registers.
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tsc_tsf_reg_list_t tsf;
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tsc_tsf_reg_list_t reserved;//no use, just for align
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//* tsd registers
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tsc_tsd_reg_list_t tsd;
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} tsc_reg_list_t;
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#endif
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