465 lines
12 KiB
C
465 lines
12 KiB
C
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/*
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* (C) Copyright 2012
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* tyle@allwinnertech.com
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*
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program;
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*
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*/
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#include <common.h>
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#include <asm/arch/pwm.h>
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#include <asm/arch/platform.h>
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#include <sys_config.h>
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#include <pwm.h>
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#define sys_get_wvalue(n) (*((volatile uint *)(n))) /* word input */
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#define sys_put_wvalue(n,c) (*((volatile uint *)(n)) = (c)) /* word output */
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#ifndef abs
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#define abs(x) (((x)&0x80000000)? (0-(x)):(x))
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#endif
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uint pwm_active_sta[4] = {1, 0, 0, 0};
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uint pwm_pin_count[4] = {0};
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user_gpio_set_t pwm_gpio_info[PWM_NUM][2];
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#define sunxi_pwm_debug 0
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#undef sunxi_pwm_debug
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#ifdef sunxi_pwm_debug
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#define pwm_debug(fmt,args...) printf(fmt ,##args)
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#else
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#define pwm_debug(fmt,args...)
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#endif
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#if defined(CONFIG_A67_FPGA) || CONFIG_FPGA_V4_PLATFORM
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#define PWM_FPGA
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#endif
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uint sunxi_pwm_read_reg(uint offset)
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{
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uint value = 0;
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value = sys_get_wvalue(PWM03_BASE + offset);
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return value;
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}
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uint sunxi_pwm_write_reg(uint offset, uint value)
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{
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sys_put_wvalue(PWM03_BASE + offset, value);
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return 0;
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}
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void sunxi_pwm_get_sys_config(int pwm)
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{
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int ret, val;
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char primary_key[25];
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user_gpio_set_t gpio_info[1];
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sprintf(primary_key, "pwm%d_para", pwm);
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ret = script_parser_fetch(primary_key, "pwm_used", &val, 1);
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if(ret < 0) {
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pwm_debug("fetch script data fail\n");
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} else {
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if(val == 1) {
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ret = script_parser_fetch(primary_key, "pwm_positive", (int *)&gpio_info, sizeof(user_gpio_set_t) / sizeof(int));
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if(ret < 0) {
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pwm_debug("fetch script data fail\n");
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} else {
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pwm_pin_count[pwm]++;
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memcpy(&pwm_gpio_info[pwm][0], gpio_info, sizeof(user_gpio_set_t));
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}
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ret = script_parser_fetch(primary_key, "pwm_negative", (int *)&gpio_info, sizeof(user_gpio_set_t) / sizeof(int));
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if(ret < 0) {
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pwm_debug("fetch script data fail\n");
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} else {
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pwm_pin_count[pwm]++;
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memcpy(&pwm_gpio_info[pwm][1], gpio_info, sizeof(user_gpio_set_t));
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}
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}
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}
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}
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int sunxi_pwm_set_polarity(int pwm, enum pwm_polarity polarity)
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{
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uint temp;
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#if ((defined CONFIG_ARCH_SUN8IW1P1) || (defined CONFIG_ARCH_SUN9IW1P1) )
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temp = sunxi_pwm_read_reg(pwm * 0x10);
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if(polarity == PWM_POLARITY_NORMAL) {
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pwm_active_sta[pwm] = 1;
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temp |= 1 << 5;
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} else {
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pwm_active_sta[pwm] = 0;
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temp &= ~(1 << 5);
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}
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sunxi_pwm_write_reg(pwm * 0x10, temp);
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#elif ((defined CONFIG_ARCH_SUN8IW3P1) || (defined CONFIG_ARCH_SUN8IW5P1) || (defined CONFIG_ARCH_SUN8IW6P1) || (defined CONFIG_ARCH_SUN8IW7P1) || (defined CONFIG_ARCH_SUN8IW8P1) ||(defined CONFIG_ARCH_SUN8IW9P1))
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temp = sunxi_pwm_read_reg(0);
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if(polarity == PWM_POLARITY_NORMAL) {
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pwm_active_sta[pwm] = 1;
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if(pwm == 0)
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temp |= 1 << 5;
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else
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temp |= 1 << 20;
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}else {
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pwm_active_sta[pwm] = 0;
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if(pwm == 0)
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temp &= ~(1 << 5);
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else
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temp &= ~(1 << 20);
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}
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sunxi_pwm_write_reg(0, temp);
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#elif (defined CONFIG_ARCH_SUN7I) || (defined CONFIG_ARCH_SUN5I)
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temp = sunxi_pwm_read_reg(0x200);
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if(polarity == PWM_POLARITY_NORMAL) {
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pwm_active_sta[pwm] = 1;
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if(pwm == 0)
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temp |= 1 << 5;
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else
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temp |= 1 << 20;
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}else {
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pwm_active_sta[pwm] = 0;
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if(pwm == 0)
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temp &= ~(1 << 5);
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else
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temp &= ~(1 << 20);
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}
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sunxi_pwm_write_reg(0x200,temp);
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#endif
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return 0;
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}
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int sunxi_pwm_config(int pwm, int duty_ns, int period_ns)
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{
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#if ((defined CONFIG_ARCH_SUN8IW1P1) || (defined CONFIG_ARCH_SUN9IW1P1))
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uint pre_scal[7] = {1, 2, 4, 8, 16, 32, 64};
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uint freq;
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uint pre_scal_id = 0;
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uint entire_cycles = 256;
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uint active_cycles = 192;
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uint entire_cycles_max = 65536;
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uint temp;
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uint calc;
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if(period_ns < 10667)
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freq = 93747;
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else if(period_ns > 174762666) {
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freq = 6;
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calc = period_ns / duty_ns;
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duty_ns = 174762666 / calc;
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period_ns = 174762666;
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}
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else
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freq = 1000000000 / period_ns;
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entire_cycles = 24000000 / freq /pre_scal[pre_scal_id];
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while(entire_cycles > entire_cycles_max) {
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pre_scal_id++;
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if(pre_scal_id > 6)
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break;
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entire_cycles = 24000000 / freq / pre_scal[pre_scal_id];
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}
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if(period_ns < 5*100*1000)
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active_cycles = (duty_ns * entire_cycles + (period_ns/2)) /period_ns;
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else if(period_ns >= 5*100*1000 && period_ns < 6553500)
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active_cycles = ((duty_ns / 100) * entire_cycles + (period_ns /2 / 100)) / (period_ns/100);
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else
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active_cycles = ((duty_ns / 10000) * entire_cycles + (period_ns /2 / 10000)) / (period_ns/10000);
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temp = sunxi_pwm_read_reg(pwm * 0x10);
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temp = (temp & 0xfffffff0) | pre_scal_id;
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sunxi_pwm_write_reg(pwm * 0x10, temp);
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printf("[PWM]temp = %d,entire_cycles = %d, active_cycles = %d\n", pwm * 0x10,entire_cycles, active_cycles);
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sunxi_pwm_write_reg(pwm * 0x10 + 0x04, ((entire_cycles - 1)<< 16) | active_cycles);
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pwm_debug("PWM _TEST: duty_ns=%d, period_ns=%d, freq=%d, per_scal=%d, period_reg=0x%x\n", duty_ns, period_ns, freq, pre_scal_id, temp);
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#elif (defined CONFIG_ARCH_SUN8IW3P1 || (defined CONFIG_ARCH_SUN8IW5P1) || (defined CONFIG_ARCH_SUN8IW6P1) || (defined CONFIG_ARCH_SUN8IW8P1))
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uint pre_scal[11][2] = {{15, 1}, {0, 120}, {1, 180}, {2, 240}, {3, 360}, {4, 480}, {8, 12000}, {9, 24000}, {10, 36000}, {11, 48000}, {12, 72000}};
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uint freq;
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uint pre_scal_id = 0;
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uint entire_cycles = 256;
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uint active_cycles = 192;
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uint entire_cycles_max = 65536;
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uint temp;
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if(period_ns < 42) {
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/* if freq lt 24M, then direct output 24M clock */
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temp = sunxi_pwm_read_reg(pwm);
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temp |= (0x1 << 9);//pwm bypass
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sunxi_pwm_write_reg(pwm, temp);
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return 0;
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}
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if(period_ns < 10667)
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freq = 93747;
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else if(period_ns > 1000000000)
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freq = 1;
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else
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freq = 1000000000 / period_ns;
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entire_cycles = 24000000 / freq / pre_scal[pre_scal_id][1];
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while(entire_cycles > entire_cycles_max) {
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pre_scal_id++;
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if(pre_scal_id > 10)
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break;
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entire_cycles = 24000000 / freq / pre_scal[pre_scal_id][1];
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}
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if(period_ns < 5*100*1000)
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active_cycles = (duty_ns * entire_cycles + (period_ns/2)) /period_ns;
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else if(period_ns >= 5*100*1000 && period_ns < 6553500)
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active_cycles = ((duty_ns / 100) * entire_cycles + (period_ns /2 / 100)) / (period_ns/100);
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else
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active_cycles = ((duty_ns / 10000) * entire_cycles + (period_ns /2 / 10000)) / (period_ns/10000);
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temp = sunxi_pwm_read_reg(0);
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if(pwm == 0)
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temp = (temp & 0xfffffff0) |pre_scal[pre_scal_id][0];
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else
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temp = (temp & 0xfff87fff) |pre_scal[pre_scal_id][0];
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sunxi_pwm_write_reg(0, temp);
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sunxi_pwm_write_reg((pwm + 1) * 0x04, ((entire_cycles - 1)<< 16) | active_cycles);
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pwm_debug("PWM _TEST: duty_ns=%d, period_ns=%d, freq=%d, per_scal=%d, period_reg=0x%x\n", duty_ns, period_ns, freq, pre_scal_id, temp);
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#elif (defined CONFIG_ARCH_SUN7I) || (defined CONFIG_ARCH_SUN5I)
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__u32 pre_scal[10] = {120, 180, 240, 360, 480, 12000, 24000, 36000, 48000, 72000};
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__u32 pre_scal_id = 0, entire_cycle = 256, active_cycle = 192;
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__u32 i=0, tmp=0;
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__u32 freq;
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freq = 1000000000 /period_ns;
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if(freq > 200000)
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{
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pwm_debug("pwm preq is large then 200khz, fix to 200khz\n");
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freq = 200000;
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}
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if(freq > 781)
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{
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pre_scal_id = 0;
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entire_cycle = (24000000 / pre_scal[pre_scal_id] + (freq/2)) / freq;
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pwm_debug("pre_scal:%d, entire_cycle:%d, pwm_freq:%d\n", pre_scal[i], entire_cycle, 24000000 / pre_scal[pre_scal_id] / entire_cycle );
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}
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else
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{
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for(i=0; i<10; i++)
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{
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__u32 pwm_freq = 0;
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pwm_freq = 24000000 / (pre_scal[i] * 256);
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if((abs((pwm_freq) - (freq))) < (abs((tmp) - (freq))))
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{
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tmp = pwm_freq;
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pre_scal_id = i;
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entire_cycle = 256;
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pwm_debug("pre_scal:%d, entire_cycle:%d, pwm_freq:%d\n", pre_scal[i], 256, pwm_freq);
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pwm_debug("----%d\n", tmp);
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}
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}
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}
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active_cycle = (duty_ns * entire_cycle + (period_ns/2)) /period_ns;
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if(pre_scal_id >= 5)
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{
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pre_scal_id += 3;
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}
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if(pwm == 0)
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{
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sunxi_pwm_write_reg(0x204, ((entire_cycle - 1)<< 16) | active_cycle);
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tmp = sunxi_pwm_read_reg(0x200) & 0xfffffff0;
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tmp |= pre_scal_id;//bit6:gatting the special clock for pwm0; bit5:pwm0 active state is high level
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sunxi_pwm_write_reg(0x200,tmp);
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}
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else
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{
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sunxi_pwm_write_reg(0x208, ((entire_cycle - 1)<< 16) | active_cycle);
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tmp = sunxi_pwm_read_reg(0x200) & 0xfff87fff;
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tmp |= (pre_scal_id<<15);//bit21:gatting the special clock for pwm1; bit20:pwm1 active state is high level
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sunxi_pwm_write_reg(0x200,tmp);
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}
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pwm_debug("PWM _TEST: duty_ns=%d, period_ns=%d, freq=%d, per_scal=%d, period_reg=0x%x\n", duty_ns, period_ns, freq, pre_scal_id, temp);
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#endif
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return 0;
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}
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int sunxi_pwm_enable(int pwm)
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{
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uint temp;
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#ifndef PWM_FPGA
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int i;
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uint ret = 0;
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for(i = 0; i < pwm_pin_count[pwm]; i++) {
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ret = gpio_request_early(&pwm_gpio_info[pwm][i], 1,1);
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if(ret == 0) {
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pwm_debug("pwm gpio request failed!\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
//gpio_release(ret, 2);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if ((defined CONFIG_ARCH_SUN8IW1P1) || (defined CONFIG_ARCH_SUN9IW1P1))
|
||
|
|
|
||
|
|
temp = sunxi_pwm_read_reg(pwm * 0x10);
|
||
|
|
|
||
|
|
temp |= 1 << 4;
|
||
|
|
temp |= 1 << 6;
|
||
|
|
|
||
|
|
sunxi_pwm_write_reg(pwm * 0x10, temp);
|
||
|
|
|
||
|
|
#elif (defined CONFIG_ARCH_SUN8IW3P1 || (defined CONFIG_ARCH_SUN8IW5P1)|| (defined CONFIG_ARCH_SUN8IW6P1) || (defined CONFIG_ARCH_SUN8IW7P1) || (defined CONFIG_ARCH_SUN8IW8P1) || (defined(CONFIG_ARCH_SUN8IW9P1)))
|
||
|
|
|
||
|
|
temp = sunxi_pwm_read_reg(0);
|
||
|
|
|
||
|
|
if(pwm == 0) {
|
||
|
|
temp |= 1 << 4;
|
||
|
|
temp |= 1 << 6;
|
||
|
|
} else {
|
||
|
|
temp |= 1 << 19;
|
||
|
|
temp |= 1 << 21;
|
||
|
|
}
|
||
|
|
|
||
|
|
sunxi_pwm_write_reg(0, temp);
|
||
|
|
|
||
|
|
#elif (defined CONFIG_ARCH_SUN7I) || (defined CONFIG_ARCH_SUN5I)
|
||
|
|
|
||
|
|
temp = sunxi_pwm_read_reg(0x200);
|
||
|
|
|
||
|
|
if(pwm == 0) {
|
||
|
|
temp |= 1 << 4;
|
||
|
|
temp |= 1 << 6;
|
||
|
|
} else {
|
||
|
|
temp |= 1 << 19;
|
||
|
|
temp |= 1 << 21;
|
||
|
|
}
|
||
|
|
|
||
|
|
sunxi_pwm_write_reg(0x200, temp);
|
||
|
|
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void sunxi_pwm_disable(int pwm)
|
||
|
|
{
|
||
|
|
uint temp;
|
||
|
|
|
||
|
|
#ifndef PWM_FPGA
|
||
|
|
|
||
|
|
int i;
|
||
|
|
uint ret = 0;
|
||
|
|
|
||
|
|
for(i = 0; i < pwm_pin_count[pwm]; i++) {
|
||
|
|
ret = gpio_request(&pwm_gpio_info[pwm][i], 1);
|
||
|
|
if(ret == 0) {
|
||
|
|
pwm_debug("pwm gpio request failed!\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
gpio_release(ret, 2);
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if ((defined CONFIG_ARCH_SUN8IW1P1) || (defined CONFIG_ARCH_SUN9IW1P1))
|
||
|
|
|
||
|
|
temp = sunxi_pwm_read_reg(pwm * 0x10);
|
||
|
|
|
||
|
|
temp &= ~(1 << 4);
|
||
|
|
temp &= ~(1 << 6);
|
||
|
|
|
||
|
|
sunxi_pwm_write_reg(pwm * 0x10, temp);
|
||
|
|
|
||
|
|
#elif (defined CONFIG_ARCH_SUN8IW3P1 || (defined CONFIG_ARCH_SUN8IW5P1) || (defined CONFIG_ARCH_SUN8IW6P1) || (defined CONFIG_ARCH_SUN8IW7P1) || (defined CONFIG_ARCH_SUN8IW8P1)||(defined CONFIG_ARCH_SUN8IW9P1))
|
||
|
|
|
||
|
|
temp = sunxi_pwm_read_reg(0);
|
||
|
|
|
||
|
|
if(pwm == 0) {
|
||
|
|
temp &= ~(1 << 4);
|
||
|
|
temp &= ~(1 << 6);
|
||
|
|
} else {
|
||
|
|
temp &= ~(1 << 19);
|
||
|
|
temp &= ~(1 << 21);
|
||
|
|
}
|
||
|
|
|
||
|
|
#elif (defined CONFIG_ARCH_SUN7I) || (defined CONFIG_ARCH_SUN5I)
|
||
|
|
|
||
|
|
temp = sunxi_pwm_read_reg(0x200);
|
||
|
|
|
||
|
|
if(pwm == 0) {
|
||
|
|
temp &= ~(1 << 4);
|
||
|
|
temp &= ~(1 << 6);
|
||
|
|
} else {
|
||
|
|
temp &= ~(1 << 19);
|
||
|
|
temp &= ~(1 << 21);
|
||
|
|
}
|
||
|
|
|
||
|
|
sunxi_pwm_write_reg(0x200, temp);
|
||
|
|
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
void sunxi_pwm_init(void)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
for(i = 0; i < PWM_NUM; i++)
|
||
|
|
sunxi_pwm_get_sys_config(i);
|
||
|
|
}
|