228 lines
8.3 KiB
C
228 lines
8.3 KiB
C
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/*
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* drivers/i2c/busses/i2c-sunxi.h
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*
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* Copyright (C) 2013 Allwinner.
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* Pan Nan <pannan@reuuimllatech.com>
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*
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* SUNXI TWI Register Definition
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* 2013.5.3 Mintow <duanmintao@allwinnertech.com>
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* Adapt to all the new chip of Allwinner. Support sun8i/sun9i.
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*/
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#ifndef _SUNXI_I2C_H_
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#define _SUNXI_I2C_H_
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#include <linux/regulator/consumer.h>
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#define TWI_MODULE_NUM (5)
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#define AUTOSUSPEND_TIMEOUT 5000
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/* TWI Register Offset */
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#define TWI_ADDR_REG (0x00) /* 31:8bit reserved,7-1bit for slave addr,0 bit for GCE */
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#define TWI_XADDR_REG (0x04) /* 31:8bit reserved,7-0bit for second addr in 10bit addr */
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#define TWI_DATA_REG (0x08) /* 31:8bit reserved, 7-0bit send or receive data byte */
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#define TWI_CTL_REG (0x0C) /* INT_EN,BUS_EN,M_STA,INT_FLAG,A_ACK */
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#define TWI_STAT_REG (0x10) /* 28 interrupt types + 0xF8 normal type = 29 */
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#define TWI_CLK_REG (0x14) /* 31:7bit reserved,6-3bit,CLK_M,2-0bit CLK_N */
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#define TWI_SRST_REG (0x18) /* 31:1bit reserved;0bit,write 1 to clear 0. */
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#define TWI_EFR_REG (0x1C) /* 31:2bit reserved,1:0 bit data byte follow read command */
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#define TWI_LCR_REG (0x20) /* 31:6bits reserved 5:0bit for sda&scl control*/
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#define TWI_DVFS_REG (0x24) /* 31:3bits reserved 2:0bit for dvfs control. only A10 support. */
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/* TWI address register */
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/* general call address enable for slave mode */
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#define TWI_GCE_EN (0x1<<0)
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#define TWI_ADDR_MASK (0x7f<<1) /* 7:1bits */
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/* 31:8bits reserved */
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/* TWI extend address register */
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/* 7:0bits for extend slave address */
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#define TWI_XADDR_MASK (0xff)
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/* 31:8bits reserved */
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/* TWI Data register default is 0x0000_0000 */
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/* 7:0bits for send or received */
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#define TWI_DATA_MASK (0xff)
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/* TWI Control Register Bit Fields & Masks, default value: 0x0000_0000*/
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/* 1:0 bits reserved */
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/* set 1 to send A_ACK,then low level on SDA */
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#define TWI_CTL_ACK (0x1<<2)
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/* INT_FLAG,interrupt status flag: set '1' when interrupt coming */
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#define TWI_CTL_INTFLG (0x1<<3)
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#define TWI_CTL_STP (0x1<<4) /* M_STP,Automatic clear 0 */
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#define TWI_CTL_STA (0x1<<5) /* M_STA,atutomatic clear 0 */
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/* BUS_EN, master mode should be set 1.*/
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#define TWI_CTL_BUSEN (0x1<<6)
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#define TWI_CTL_INTEN (0x1<<7) /* INT_EN */
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/* 31:8 bit reserved */
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/* TWI Clock Register Bit Fields & Masks,default value:0x0000_0000 */
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/*
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* Fin is APB CLOCK INPUT;
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* Fsample = F0 = Fin/2^CLK_N;
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* F1 = F0/(CLK_M+1);
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*
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* Foscl = F1/10 = Fin/(2^CLK_N * (CLK_M+1)*10);
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* Foscl is clock SCL;standard mode:100KHz or fast mode:400KHz
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*/
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#define TWI_CLK_DIV_M (0xF<<3) /* 6:3bit */
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#define TWI_CLK_DIV_N (0x7<<0) /* 2:0bit */
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/* TWI Soft Reset Register Bit Fields & Masks */
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/* write 1 to clear 0, when complete soft reset clear 0 */
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#define TWI_SRST_SRST (0x1<<0)
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/* TWI Enhance Feature Register Bit Fields & Masks */
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/* default -- 0x0 */
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/* 00:no,01: 1byte, 10:2 bytes, 11: 3bytes */
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#define TWI_EFR_MASK (0x3<<0)
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#define TWI_EFR_WARC_0 (0x0<<0)
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#define TWI_EFR_WARC_1 (0x1<<0)
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#define TWI_EFR_WARC_2 (0x2<<0)
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#define TWI_EFR_WARC_3 (0x3<<0)
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/* twi line control register -default value: 0x0000_003a */
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/* SDA line state control enable ,1:enable;0:disable */
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#define TWI_LCR_SDA_EN (0x01<<0)
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/* SDA line state control bit, 1:high level;0:low level */
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#define TWI_LCR_SDA_CTL (0x01<<1)
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/* SCL line state control enable ,1:enable;0:disable */
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#define TWI_LCR_SCL_EN (0x01<<2)
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/* SCL line state control bit, 1:high level;0:low level */
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#define TWI_LCR_SCL_CTL (0x01<<3)
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/* current state of SDA,readonly bit */
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#define TWI_LCR_SDA_STATE_MASK (0x01<<4)
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/* current state of SCL,readonly bit */
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#define TWI_LCR_SCL_STATE_MASK (0x01<<5)
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/* 31:6bits reserved */
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#define TWI_LCR_IDLE_STATUS (0x3a)
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#define TWI_LCR_NORM_STATUS (0x30) /* normal status */
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/* TWI Status Register Bit Fields & Masks */
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#define TWI_STAT_MASK (0xff)
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/* 7:0 bits use only,default is 0xF8 */
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#define TWI_STAT_BUS_ERR (0x00) /* BUS ERROR */
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/* Master mode use only */
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#define TWI_STAT_TX_STA (0x08) /* START condition transmitted */
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/* Repeated START condition transmitted */
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#define TWI_STAT_TX_RESTA (0x10)
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/* Address+Write bit transmitted, ACK received */
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#define TWI_STAT_TX_AW_ACK (0x18)
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/* Address+Write bit transmitted, ACK not received */
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#define TWI_STAT_TX_AW_NAK (0x20)
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/* data byte transmitted in master mode,ack received */
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#define TWI_STAT_TXD_ACK (0x28)
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/* data byte transmitted in master mode ,ack not received */
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#define TWI_STAT_TXD_NAK (0x30)
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/* arbitration lost in address or data byte */
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#define TWI_STAT_ARBLOST (0x38)
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/* Address+Read bit transmitted, ACK received */
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#define TWI_STAT_TX_AR_ACK (0x40)
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/* Address+Read bit transmitted, ACK not received */
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#define TWI_STAT_TX_AR_NAK (0x48)
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/* data byte received in master mode ,ack transmitted */
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#define TWI_STAT_RXD_ACK (0x50)
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/* date byte received in master mode,not ack transmitted */
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#define TWI_STAT_RXD_NAK (0x58)
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/* Slave mode use only */
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/* Slave address+Write bit received, ACK transmitted */
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#define TWI_STAT_RXWS_ACK (0x60)
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#define TWI_STAT_ARBLOST_RXWS_ACK (0x68)
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/* General Call address received, ACK transmitted */
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#define TWI_STAT_RXGCAS_ACK (0x70)
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#define TWI_STAT_ARBLOST_RXGCAS_ACK (0x78)
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#define TWI_STAT_RXDS_ACK (0x80)
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#define TWI_STAT_RXDS_NAK (0x88)
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#define TWI_STAT_RXDGCAS_ACK (0x90)
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#define TWI_STAT_RXDGCAS_NAK (0x98)
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#define TWI_STAT_RXSTPS_RXRESTAS (0xA0)
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#define TWI_STAT_RXRS_ACK (0xA8)
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#define TWI_STAT_ARBLOST_SLAR_ACK (0xB0)
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/* 10bit Address, second part of address */
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/* Second Address byte+Write bit transmitted,ACK received */
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#define TWI_STAT_TX_SAW_ACK (0xD0)
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/* Second Address byte+Write bit transmitted,ACK not received */
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#define TWI_STAT_TX_SAW_NAK (0xD8)
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/* No relevant status information,INT_FLAG = 0 */
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#define TWI_STAT_IDLE (0xF8)
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/* status or interrupt source */
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/*
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* -------------------------------------------------------------------
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* Code Status
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* 00h Bus error
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* 08h START condition transmitted
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* 10h Repeated START condition transmitted
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* 18h Address + Write bit transmitted, ACK received
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* 20h Address + Write bit transmitted, ACK not received
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* 28h Data byte transmitted in master mode, ACK received
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* 30h Data byte transmitted in master mode, ACK not received
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* 38h Arbitration lost in address or data byte
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* 40h Address + Read bit transmitted, ACK received
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* 48h Address + Read bit transmitted, ACK not received
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* 50h Data byte received in master mode, ACK transmitted
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* 58h Data byte received in master mode, not ACK transmitted
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* 60h Slave address + Write bit received, ACK transmitted
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* 68h Arbitration lost in address as master,
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* slave address + Write bit received, ACK transmitted
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* 70h General Call address received, ACK transmitted
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* 78h Arbitration lost in address as master,
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* General Call address received, ACK transmitted
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* 80h Data byte received after slave address received, ACK transmitted
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* 88h Data byte received after slave address received, not ACK transmitted
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* 90h Data byte received after General Call received, ACK transmitted
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* 98h Data byte received after General Call received, not ACK transmitted
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* A0h STOP or repeated START condition received in slave mode
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* A8h Slave address + Read bit received, ACK transmitted
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* B0h Arbitration lost in address as master,
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* slave address + Read bit received, ACK transmitted
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* B8h Data byte transmitted in slave mode, ACK received
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* C0h Data byte transmitted in slave mode, ACK not received
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* C8h Last byte transmitted in slave mode, ACK received
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* D0h Second Address byte + Write bit transmitted, ACK received
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* D8h Second Address byte + Write bit transmitted, ACK not received
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* F8h No relevant status information or no interrupt
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*--------------------------------------------------------------------------
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*/
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/* TWI mode select */
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#define TWI_MASTER_MODE (1)
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#define TWI_SLAVE_MODE (0) /* seldom use */
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/* The global infor of TWI channel. */
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#define SUNXI_TWI_DEV_NAME "twi"
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#define SUNXI_TWI_CHAN_MASK(ch) (1<<ch)
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struct sunxi_i2c_platform_data {
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int bus_num;
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unsigned int frequency;
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char regulator_id[16];
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struct regulator *regulator;
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};
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#endif /* end of _SUNXI_I2C_H_ */
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