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SmartAudio/lichee/linux-4.9/arch/arm64/boot/dts/sunxi/sun50iw8p1.dtsi

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init
2018-07-13 01:31:50 +00:00
/*
* Allwinner Technology CO., Ltd. sun50iw8p1 platform
*
* modify base on juno.dts
*/
/* kernel used */
/memreserve/ 0x40020000 0x00000800; /* super standby range : [0x40020000~0x41020800], size = 2K */
/memreserve/ 0x48000000 0x01000000; /* atf : [0x48000000~0x49000000], size = 16M */
/* tf used */
/memreserve/ 0x48100000 0x00004000; /* arisc dram code space range: [0x48100000~0x48104000], size = 16K */
/memreserve/ 0x48104000 0x00001000; /* arisc para cfg range : [0x48104000~0x48105000], size = 4K */
/memreserve/ 0x48105000 0x00001000; /* arisc message pool range : [0x48105000~0x48106000], size = 4K */
/* ramoops used */
/memreserve/ 0x48106000 0x00060000; /* ramoops range : [0x48106000~0x48166000], size = 384K */
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include "sun50iw8p1-clk.dtsi"
#include "sun50iw8p1-pinctrl.dtsi"
/ {
model = "sun50iw8";
compatible = "arm,sun50iw8p1";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
twi0 = &twi0;
twi1 = &twi1;
twi2 = &twi2;
spi0 = &spi0;
spi1 = &spi1;
global_timer0 = &soc_timer0;
mmc0 = &sdc0;
mmc2 = &sdc2;
nand0 =&nand0;
disp = &disp;
lcd0 = &lcd0;
pwm = &pwm;
pwm0 = &pwm0;
pwm1 = &pwm1;
s_pwm = &s_pwm;
spwm0 = &spwm0;
boot_disp = &boot_disp;
charger0 = &charger0;
regulator0 = &regulator0;
};
chosen {
bootargs = "earlyprintk=sunxi-uart,0x05000000 loglevel=8 initcall_debug=0 console=ttyS0,115200 init=/init";
linux,initrd-start = <0x0 0x0>;
linux,initrd-end = <0x0 0x0>;
};
firmware {
android {
compatible = "android,firmware";
name = "android";
fstab {
compatible = "android,fstab";
name = "fstab";
vendor {
compatible = "android,vendor";
dev = "/dev/block/by-name/vendor";
fsmgr_flags = "wait";
mnt_flags = "ro,barrier=1";
name = "vendor";
status = "ok";
type = "ext4";
};
system {
compatible = "android,system";
dev = "/dev/block/by-name/system";
fsmgr_flags = "wait";
mnt_flags = "ro,barrier=1";
name = "system";
status = "ok";
type = "ext4";
};
};
};
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&clk_pll_cpu>;
clock-latency = <2000000>;
clock-frequency = <1008000000>;
operating-points-v2 = <&cpu_opp_l_table0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
};
/*For FPGA stage*/
/*
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&clk_pll_cpu>;
clock-frequency = <1008000000>;
operating-points-v2 = <&cpu_opp_l_table0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&clk_pll_cpu>;
clock-frequency = <1008000000>;
operating-points-v2 = <&cpu_opp_l_table0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&clk_pll_cpu>;
clock-frequency = <1008000000>;
operating-points-v2 = <&cpu_opp_l_table0>;
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0 &SYS_SLEEP_0>;
};
*/
idle-states {
entry-method = "arm,psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <40>;
exit-latency-us = <100>;
min-residency-us = <150>;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010000>;
entry-latency-us = <500>;
exit-latency-us = <1000>;
min-residency-us = <2500>;
};
SYS_SLEEP_0: sys-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x2010000>;
entry-latency-us = <1000>;
exit-latency-us = <2000>;
min-residency-us = <4500>;
};
};
};
opp_dvfs_table:opp_dvfs_table {
cluster_num = <1>;
opp_table_count = <1>;
cpu_opp_l_table0: opp_l_table0 {
/* compatible = "operating-points-v2"; */
compatible = "allwinner,opp_l_table0";
opp_count = <5>;
opp-shared;
opp00 {
opp-hz = /bits/ 64 <648000000>;
opp-microvolt = <800000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
opp01 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <840000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
opp02 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <900000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
opp03 {
opp-hz = /bits/ 64 <1416000000>;
opp-microvolt = <960000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
opp04 {
opp-hz = /bits/ 64 <1512000000>;
opp-microvolt = <1000000>;
axi-bus-divide-ratio = <3>;
clock-latency-ns = <2000000>;
};
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
dvfs_table: dvfs_table {
compatible = "allwinner,dvfs_table";
};
n_brom {
compatible = "allwinner,n-brom";
reg = <0x0 0x0 0x0 0xc000>;
};
s_brom {
compatible = "allwinner,s-brom";
reg = <0x0 0x0 0x0 0x10000>;
};
sram_ctrl {
device_type = "sram_ctrl";
compatible = "allwinner,sram_ctrl";
reg = <0x0 0x03000000 0x0 0x100>;
};
sram_a1 {
compatible = "allwinner,sram_a1";
reg = <0x0 0x00010000 0x0 0x10000>;
};
sram_a2 {
compatible = "allwinner,sram_a2";
reg = <0x0 0x00040000 0x0 0x14000>;
};
prcm {
compatible = "allwinner,prcm";
reg = <0x0 0x01f01400 0x0 0x400>;
};
cpuscfg {
compatible = "allwinner,cpuscfg";
reg = <0x0 0x01f01c00 0x0 0x400>;
};
ion {
compatible = "allwinner,sunxi-ion";
/*
*types list here:
ION_HEAP_TYPE_SYSTEM = 0,
ION_HEAP_TYPE_SYSTEM_CONTIG = 1,
ION_HEAP_TYPE_CARVEOUT = 2,
ION_HEAP_TYPE_CHUNK = 3,
ION_HEAP_TYPE_DMA = 4,
ION_HEAP_TYPE_SECURE = 5,
**/
heap_sys_user@0{
compatible = "allwinner,sys_user";
heap-name = "sys_user";
heap-id = <0x0>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_system";
};
heap_sys_contig@0{
compatible = "allwinner,sys_contig";
heap-name = "sys_contig";
heap-id = <0x1>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_contig";
};
heap_cma@0{
compatible = "allwinner,cma";
heap-name = "cma";
heap-id = <0x4>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_cma";
};
heap_secure@0{
compatible = "allwinner,secure";
heap-name = "secure";
heap-id = <0x5>;
heap-base = <0x0>;
heap-size = <0x0>;
heap-type = "ion_secure";
};
};
dram: dram {
compatible = "allwinner,dram";
/* clocks = <&clk_pll_ddr>; */
clock-names = "pll_ddr";
dram_clk = <672>;
dram_type = <3>;
dram_zq = <0x003F3FDD>;
dram_odt_en = <1>;
dram_para1 = <0x10f41000>;
dram_para2 = <0x00001200>;
dram_mr0 = <0x1A50>;
dram_mr1 = <0x40>;
dram_mr2 = <0x10>;
dram_mr3 = <0>;
dram_tpr0 = <0x04E214EA>;
dram_tpr1 = <0x004214AD>;
dram_tpr2 = <0x10A75030>;
dram_tpr3 = <0>;
dram_tpr4 = <0>;
dram_tpr5 = <0>;
dram_tpr6 = <0>;
dram_tpr7 = <0>;
dram_tpr8 = <0>;
dram_tpr9 = <0>;
dram_tpr10 = <0>;
dram_tpr11 = <0>;
dram_tpr12 = <168>;
dram_tpr13 = <0x823>;
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0x00000000 0x20000000>;
};
gic: interrupt-controller@03020000 {
compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
device_type = "gic";
interrupt-controller;
reg = <0x0 0x03021000 0 0x1000>, /* GIC Dist */
<0x0 0x03022000 0 0x2000>, /* GIC CPU */
<0x0 0x03024000 0 0x2000>, /* GIC VCPU Control */
<0x0 0x03026000 0 0x2000>; /* GIC VCPU */
interrupts = <GIC_PPI 9 0xf04>; /* GIC Maintenence IRQ */
};
sid: sunxi-sid@03006000 {
compatible = "allwinner,sunxi-sid";
device_type = "sid";
reg = <0x0 0x03006000 0 0x200>;
};
chipid: sunxi-chipid@03006200 {
compatible = "allwinner,sunxi-chipid";
device_type = "chipid";
reg = <0x0 0x03006200 0 0x140>;
};
timer_arch {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <24000000>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 138 4>,
<GIC_SPI 139 4>,
<GIC_SPI 140 4>,
<GIC_SPI 141 4>;
};
dvfs_table: dvfs_table {
compatible = "allwinner,dvfs_table";
max_freq = <1200000000>;
min_freq = <480000000>;
lv_count = <8>;
lv1_freq = <1200000000>;
lv1_volt = <1300>;
lv2_freq = <1008000000>;
lv2_volt = <1200>;
lv3_freq = <816000000>;
lv3_volt = <1100>;
lv4_freq = <648000000>;
lv4_volt = <1040>;
lv5_freq = <0>;
lv5_volt = <1040>;
lv6_freq = <0>;
lv6_volt = <1040>;
lv7_freq = <0>;
lv7_volt = <1040>;
lv8_freq = <0>;
lv8_volt = <1040>;
};
dramfreq {
compatible = "allwinner,sunxi-dramfreq";
reg = <0x0 0x01c62000 0x0 0x1000>,
<0x0 0x01c63000 0x0 0x1000>,
<0x0 0x01c20000 0x0 0x800>;
interrupts = <GIC_SPI 69 0x4>;
/* clocks = <&clk_pll_ddr>, <&clk_pll_periph0>, <&clk_ahb1>; */
status = "okay";
};
uboot: uboot {
};
soc: soc@03000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
device_type = "soc";
dma0:dma-controller@03002000 {
compatible = "allwinner,sun50i-dma";
reg = <0x0 0x03002000 0x0 0x1000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_dma>;
#dma-cells = <1>;
};
mbus0:mbus-controller@04002000 {
compatible = "allwinner,sun50i-mbus";
reg = <0x0 0x04002000 0x0 0x1000>;
#mbus-cells = <1>;
};
arisc {
compatible = "allwinner,sunxi-arisc";
#address-cells = <2>;
#size-cells = <2>;
clocks = <&clk_losc>, <&clk_iosc>, <&clk_hosc>, <&clk_pll_periph0>;
clock-names = "losc", "iosc", "hosc", "pll_periph0";
powchk_used = <0x0>;
power_reg = <0x02309621>;
system_power = <50>;
};
arisc_space {
compatible = "allwinner,arisc_space";
/* num dst offset size */
space1 = <0x00100000 0x00000000 0x00014000>; /* srama2 code space */
space2 = <0x48100000 0x00018000 0x00004000>; /* dram code space */
space3 = <0x48104000 0x00000000 0x00001000>; /* para space */
space4 = <0x48105000 0x00000000 0x00001000>; /* msgpool space */
};
standby_space {
compatible = "allwinner,sun50iw8-superstandby";
/* num dst offset size */
space1 = <0x40020000 0x00000000 0x00000800>; /* super standby para space */
};
msgbox: msgbox@3003000 {
compatible = "allwinner,msgbox";
clocks = <&clk_msgbox>;
clock-names = "clk_msgbox";
reg = <0x0 0x03003000 0x0 0x1000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>;
status = "okay";
};
hwspinlock: hwspinlock@3004000 {
compatible = "allwinner,sunxi-hwspinlock";
clocks = <&clk_hwspinlock_rst>, <&clk_hwspinlock_bus>;
clock-names = "clk_hwspinlock_rst", "clk_hwspinlock_bus";
reg = <0x0 0x03004000 0x0 0x1000>;
num-locks = <8>; /* the number hwspinlock we needed, max 32 */
status = "okay";
};
s_cir0: s_cir@07040000 {
compatible = "allwinner,s_cir";
reg = <0x0 0x07040000 0x0 0x400>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&s_cir0_pins_a>;
clocks = <&clk_hosc>;
supply = "";
supply_vol = "";
status = "okay";
};
s_uart0: s_uart@7080000 {
compatible = "allwinner,s_uart";
reg = <0x0 0x07080000 0x0 0x400>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&s_uart0_pins_a>;
status = "okay";
};
s_rsb: s_rsb@7083000 {
compatible = "allwinner,s_rsb";
reg = <0x0 0x07083000 0x0 0x300>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&s_rsb0_pins_a>;
status = "okay";
};
s_twi0: s_twi@7081400 {
compatible = "allwinner,s_twi";
reg = <0x0 0x07081400 0x0 0x400>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&s_twi0_pins_a>;
status = "okay";
};
s_twi1: s_twi@7081800 {
compatible = "allwinner,s_twi";
reg = <0x0 0x07081800 0x0 0x400>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&s_twi0_pins_a>;
status = "okay";
};
s_jtag0: s_jtag0 {
compatible = "allwinner,s_jtag";
pinctrl-names = "default";
pinctrl-0 = <&s_jtag0_pins_a>;
status = "disable";
};
s_cpuscfg: s_cpuscfg@0x7000400 {
compatible = "allwinner,s_cpuscfg";
reg = <0x0 0x07000400 0x0 0x800>;
status = "okay";
};
box_start_os: box_start_os0 {
compatible = "allwinner,box_start_os";
start_type = <0x0>;
irkey_used = <0x0>;
pmukey_used = <0x0>;
pmukey_num = <0x0>;
led_power = <0x0>;
led_state = <0x0>;
status = "disable";
};
soc_timer0: timer@03009000 {
compatible = "allwinner,sun4i-a10-timer";
device_type = "timer";
reg = <0x0 0x03009000 0x0 0x90>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
/* On FPGA, timer can only use the losc.
* On IC, timer should use the hosc.
*/
clock-frequency = <24000000>;
timer-prescale = <16>;
/*Will not use soc timer in FPGA stage*/
/*
clocks = <&clk_losc>, <&clk_hosc>;
*/
};
rtc: rtc@07000000 {
compatible = "allwinner,sun50i-rtc", \
"allwinner,sunxi-rtc";
device_type = "rtc";
reg = <0x0 0x07000000 0x0 0x400>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
gpr_offset = <0x100>;
gpr_len = <8>;
};
wdt: watchdog@030090a0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x0 0x030090a0 0x0 0x20>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
};
uart0: uart@05000000 {
compatible = "allwinner,sun50i-uart";
device_type = "uart0";
reg = <0x0 0x05000000 0x0 0x400>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart0_pins_a>;
pinctrl-1 = <&uart0_pins_b>;
uart0_port = <0>;
uart0_type = <2>;
status = "okay";
};
uart1: uart@05000400 {
compatible = "allwinner,sun50i-uart";
device_type = "uart1";
reg = <0x0 0x05000400 0x0 0x400>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart1_pins_a>;
pinctrl-1 = <&uart1_pins_b>;
uart1_port = <1>;
uart1_type = <4>;
status = "disabled";
};
uart2: uart@05000800 {
compatible = "allwinner,sun50i-uart";
device_type = "uart2";
reg = <0x0 0x05000800 0x0 0x400>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart2>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart2_pins_a>;
pinctrl-1 = <&uart2_pins_b>;
uart2_port = <2>;
uart2_type = <4>;
status = "disabled";
};
uart3: uart@05000c00 {
compatible = "allwinner,sun50i-uart";
device_type = "uart3";
reg = <0x0 0x05000c00 0x0 0x400>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart3>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart3_pins_a>;
pinctrl-1 = <&uart3_pins_b>;
uart3_port = <3>;
uart3_type = <4>;
status = "disabled";
};
uart4: uart@05001000 {
compatible = "allwinner,sun50i-uart";
device_type = "uart4";
reg = <0x0 0x05001000 0x0 0x400>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart4>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&uart4_pins_a>;
pinctrl-1 = <&uart4_pins_b>;
uart4_port = <4>;
uart4_type = <4>;
status = "disabled";
};
twi0: twi@0x05002000{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun50i-twi";
device_type = "twi0";
reg = <0x0 0x05002000 0x0 0x400>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi0>;
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi0_pins_a>;
pinctrl-1 = <&twi0_pins_b>;
status = "disabled";
};
twi1: twi@0x05002400{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun50i-twi";
device_type = "twi1";
reg = <0x0 0x05002400 0x0 0x400>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi1>;
clock-frequency = <100000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi1_pins_a>;
pinctrl-1 = <&twi1_pins_b>;
status = "disabled";
};
twi2: twi@0x05002800{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun50i-twi";
device_type = "twi2";
reg = <0x0 0x05002800 0x0 0x400>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_twi2>;
clock-frequency = <100000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&twi2_pins_a>;
pinctrl-1 = <&twi2_pins_b>;
status = "disabled";
};
usbc0:usbc0@0 {
device_type = "usbc0";
compatible = "allwinner,sunxi-otg-manager";
usb_port_type = <2>;
usb_detect_type = <1>;
usb_id_gpio;
usb_det_vbus_gpio;
usb_drv_vbus_gpio;
usb_host_init_state = <0>;
usb_regulator_io = "nocare";
usb_wakeup_suspend = <0>;
usb_luns = <3>;
usb_serial_unique = <0>;
usb_serial_number = "20080411";
rndis_wceis = <1>;
status = "okay";
};
udc:udc-controller@0x05100000 {
compatible = "allwinner,sunxi-udc";
reg = <0x0 0x05100000 0x0 0x1000>, /*udc base*/
<0x0 0x00000000 0x0 0x100>; /*sram base*/
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbotg>;
status = "okay";
};
ehci0:ehci0-controller@0x05101000 {
compatible = "allwinner,sunxi-ehci0";
reg = <0x0 0x05101000 0x0 0xFFF>, /*hci0 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbehci0>;
hci_ctrl_no = <0>;
status = "okay";
};
ohci0:ohci0-controller@0x05101400 {
compatible = "allwinner,sunxi-ohci0";
reg = <0x0 0x05101000 0x0 0xFFF>, /*hci0 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy0>, <&clk_usbohci0>, <&clk_usbohci0_12m>, <&clk_osc48md4>, <&clk_hosc>, <&clk_losc>;
hci_ctrl_no = <0>;
status = "okay";
};
usbc1:usbc1@0 {
device_type = "usbc1";
usb_drv_vbus_gpio;
usb_host_init_state = <1>;
usb_regulator_io = "nocare";
usb_wakeup_suspend = <0>;
status = "okay";
};
ehci1:ehci1-controller@0x05200000 {
compatible = "allwinner,sunxi-ehci1";
reg = <0x0 0x05200000 0x0 0xFFF>,/*hci1 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy1>, <&clk_usbehci1>;
hci_ctrl_no = <1>;
status = "okay";
};
ohci1:ohci1-controller@0x05200400 {
compatible = "allwinner,sunxi-ohci1";
reg = <0x0 0x05200000 0x0 0xFFF>, /*hci1 base*/
<0x0 0x00000000 0x0 0x100>, /*sram base*/
<0x0 0x05100000 0x0 0x1000>; /*otg base*/
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_usbphy1>, <&clk_usbohci1>, <&clk_usbohci1_12m>, <&clk_osc48md4>, <&clk_hosc>, <&clk_losc>;
hci_ctrl_no = <1>;
status = "okay";
};
codec:codec@0x05096000 {
compatible = "allwinner,sunxi-internal-codec";
reg = <0x0 0x05096000 0x0 0x478>,/*digital baseadress*/
<0x0 0x050967c0 0x0 0x0>;/*analog baseadress*/
clocks = <&clk_pll_audio>,<&clk_codec_1x>;
gpio-spk = <&pio PH 7 1 1 1 1>;
pinctrl-names = "aif2-default","aif3-default","aif2-sleep","aif3-sleep";
pinctrl-0 = <&aif2_pins_a>;
pinctrl-1 = <&aif3_pins_a>;
pinctrl-2 = <&aif2_pins_b>;
pinctrl-3 = <&aif3_pins_b>;
headphonevol = <0x3b>;
spkervol = <0x1b>;
earpiecevol = <0x1e>;
maingain = <0x4>;
headsetmicgain = <0x4>;
adcagc_cfg = <0x0>;
adcdrc_cfg = <0x0>;
adchpf_cfg = <0x0>;
dacdrc_cfg = <0x0>;
dachpf_cfg = <0x0>;
aif1_lrlk_div = <0x40>;
aif2_lrlk_div = <0x40>;
aif2config = <0x0>;
aif3config = <0x0>;
pa_sleep_time = <0x15e>;
dac_digital_vol = <0xa0a0>;
status = "okay";
};
i2s:i2s-controller@0x05096000 {
compatible = "allwinner,sunxi-internal-i2s";
reg = <0x0 0x05096000 0x0 0x478>;/*digital baseadress*/
clocks = <&clk_pll_audio>,<&clk_codec_1x>;
status = "okay";
};
daudio0:daudio@0x05090000 {
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x05090000 0x0 0x74>;
clocks = <&clk_pll_audio>,<&clk_i2s0>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&daudio0_pins_a>;
pinctrl-1 = <&daudio0_pins_b>;
pcm_lrck_period = <0x20>;
slot_width_select = <0x20>;
daudio_master = <0x04>;
audio_format = <0x01>;
signal_inversion = <0x01>;
frametype = <0x00>;
tdm_config = <0x01>;
tdm_num = <0x0>;
mclk_div = <0x0>;
status = "disabled";
};
daudio1:daudio@0x05091000 {
compatible = "allwinner,sunxi-daudio";
reg = <0x0 0x05091000 0x0 0x74>;
clocks = <&clk_pll_audio>,<&clk_i2s1>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&daudio1_pins_a>;
pinctrl-1 = <&daudio1_pins_b>;
pcm_lrck_period = <0x20>;
slot_width_select = <0x20>;
daudio_master = <0x04>;
audio_format = <0x01>;
signal_inversion = <0x01>;
frametype = <0x00>;
tdm_config = <0x01>;
tdm_num = <0x1>;
mclk_div = <0x0>;
status = "disabled";
};
dmic:dmic-controller@0x05095000{
compatible = "allwinner,sunxi-dmic";
reg = <0x0 0x05095000 0x0 0x50>;
clocks = <&clk_pll_audio>,<&clk_dmic>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&dmic_pins_a>;
pinctrl-1 = <&dmic_pins_b>;
status = "disabled";
};
sndcodec:sound@0 {
compatible = "allwinner,sunxi-codec-machine";
interrupts = <GIC_SPI 26 4>;
sunxi,i2s-controller = <&i2s>;
sunxi,audio-codec = <&codec>;
aif2fmt = <0x3>;
aif3fmt = <0x3>;
aif2master = <0x01>;
hp_detect_case = <0x0>;
/* jack_det_gpio = <&pio PH 12 1 0 1 0>; */
/* invert: 0->high is plug_in, 1->high is plug_out */
jack_invert = <1>;
status = "disabled";
};
snddaudio0:sound@1{
compatible = "allwinner,sunxi-daudio0-machine";
sunxi,daudio-controller = <&daudio0>;
status = "disabled";
};
snddaudio1:sound@2{
compatible = "allwinner,sunxi-daudio1-machine";
sunxi,daudio-controller = <&daudio1>;
status = "disabled";
};
snddmic:sound@3{
compatible = "allwinner,sunxi-dmic-machine";
sunxi,dmic-controller = <&dmic>;
status = "disabled";
};
spi0: spi@05010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun50i-spi";
device_type = "spi0";
reg = <0x0 0x05010000 0x0 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0>, <&clk_spi0>;
clock-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi0_pins_a &spi0_pins_b>;
pinctrl-1 = <&spi0_pins_c>;
spi0_cs_number = <2>;
spi0_cs_bitmap = <3>;
status = "disabled";
};
spi1: spi@05011000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sun50i-spi";
device_type = "spi1";
reg = <0x0 0x05011000 0x0 0x1000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_pll_periph0>, <&clk_spi1>;
clock-frequency = <100000000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi1_pins_a &spi1_pins_b>;
pinctrl-1 = <&spi1_pins_c>;
spi1_cs_number = <1>;
spi1_cs_bitmap = <1>;
status = "disabled";
};
sdc2: sdmmc@04022000 {
compatible = "allwinner,sunxi-mmc-v4p6x";
device_type = "sdc2";
reg = <0x0 0x04022000 0x0 0x1000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_hosc>,
<&clk_pll_periph1x2>,
<&clk_sdmmc2_mod>,
<&clk_sdmmc2_bus>,
<&clk_sdmmc2_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc2_pins_a>;
pinctrl-1 = <&sdc2_pins_b>;
bus-width = <8>;
cap-mmc-highspeed;
cap-cmd23;
mmc-cache-ctrl;
/*mmc-ddr-1_8v;*/
/*mmc-hs200-1_8v;*/
/*mmc-hs400-1_8v;*/
non-removable;
/*max-frequency = <200000000>;*/
max-frequency = <50000000>;
cap-erase;
mmc-high-capacity-erase-size;
no-sdio;
no-sd;
/*-- speed mode --*/
/*sm0: DS26_SDR12*/
/*sm1: HSSDR52_SDR25*/
/*sm2: HSDDR52_DDR50*/
/*sm3: HS200_SDR104*/
/*sm4: HS400*/
/*-- frequency point --*/
/*f0: CLK_400K*/
/*f1: CLK_25M*/
/*f2: CLK_50M*/
/*f3: CLK_100M*/
/*f4: CLK_150M*/
/*f5: CLK_200M*/
sdc_tm4_sm0_freq0 = <0>;
sdc_tm4_sm0_freq1 = <0>;
sdc_tm4_sm1_freq0 = <0x00000000>;
sdc_tm4_sm1_freq1 = <0>;
sdc_tm4_sm2_freq0 = <0x00000000>;
sdc_tm4_sm2_freq1 = <0>;
sdc_tm4_sm3_freq0 = <0x05000000>;
sdc_tm4_sm3_freq1 = <0x00000005>;
sdc_tm4_sm4_freq0 = <0x00050000>;
sdc_tm4_sm4_freq1 = <0x00000004>;
/*vmmc-supply = <&reg_3p3v>;*/
/*vqmc-supply = <&reg_3p3v>;*/
/*vdmc-supply = <&reg_3p3v>;*/
/*vmmc = "vcc-card";*/
/*vqmc = "";*/
/*vdmc = "";*/
/*sunxi-power-save-mode;*/
/*status = "disabled";*/
status = "okay";
};
sdc0: sdmmc@04020000 {
compatible = "allwinner,sunxi-mmc-v4p1x";
device_type = "sdc0";
reg = <0x0 0x04020000 0x0 0x1000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_hosc>,
<&clk_pll_periph1x2>,
<&clk_sdmmc0_mod>,
<&clk_sdmmc0_bus>,
<&clk_sdmmc0_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc0_pins_a>;
pinctrl-1 = <&sdc0_pins_b>;
max-frequency = <50000000>;
bus-width = <4>;
/*non-removable;*/
/*broken-cd;*/
/*cd-inverted*/
/*cd-gpios = <&pio PF 6 0 1 2 0>;*/
/* vmmc-supply = <&reg_3p3v>;*/
/* vqmc-supply = <&reg_3p3v>;*/
/* vdmc-supply = <&reg_3p3v>;*/
/*vmmc = "vcc-card";*/
/*vqmc = "";*/
/*vdmc = "";*/
cap-sd-highspeed;
cap-wait-while-busy;
no-sdio;
no-mmc;
/*sd-uhs-sdr50;*/
/*sd-uhs-ddr50;*/
/*cap-sdio-irq;*/
/*keep-power-in-suspend;*/
/*ignore-pm-notify;*/
/*sunxi-power-save-mode;*/
/*sunxi-dly-400k = <1 0 0 0>; */
/*sunxi-dly-26M = <1 0 0 0>;*/
/*sunxi-dly-52M = <1 0 0 0>;*/
/*sunxi-dly-52M-ddr4 = <1 0 0 0>;*/
/*sunxi-dly-52M-ddr8 = <1 0 0 0>;*/
/*sunxi-dly-104M = <1 0 0 0>;*/
/*sunxi-dly-208M = <1 0 0 0>;*/
/*sunxi-dly-104M-ddr = <1 0 0 0>;*/
/*sunxi-dly-208M-ddr = <1 0 0 0>;*/
status = "okay";
};
sdc1: sdmmc@04021000 {
compatible = "allwinner,sunxi-mmc-v4p1x";
device_type = "sdc1";
reg = <0x0 0x04021000 0x0 0x1000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_hosc>,
<&clk_pll_periph1x2>,
<&clk_sdmmc1_mod>,
<&clk_sdmmc1_bus>,
<&clk_sdmmc1_rst>;
clock-names = "osc24m","pll_periph","mmc","ahb","rst";
pinctrl-names = "default","sleep";
pinctrl-0 = <&sdc1_pins_a>;
pinctrl-1 = <&sdc1_pins_b>;
max-frequency = <50000000>;
bus-width = <4>;
/*broken-cd;*/
/*cd-inverted*/
/*cd-gpios = <&pio PG 6 6 1 2 0>;*/
/* vmmc-supply = <&reg_3p3v>;*/
/* vqmc-supply = <&reg_3p3v>;*/
/* vdmc-supply = <&reg_3p3v>;*/
/*vmmc = "vcc-card";*/
/*vqmc = "";*/
/*vdmc = "";*/
cap-sd-highspeed;
no-mmc;
/*sd-uhs-sdr50;*/
/*sd-uhs-ddr50;*/
/*sd-uhs-sdr104;*/
/*cap-sdio-irq;*/
keep-power-in-suspend;
/*ignore-pm-notify;*/
/*sunxi-power-save-mode;*/
/*sunxi-dly-400k = <1 0 0 0 0>; */
/*sunxi-dly-26M = <1 0 0 0 0>;*/
/*sunxi-dly-52M = <1 0 0 0 0>;*/
sunxi-dly-52M-ddr4 = <1 0 0 0 2>;
/*sunxi-dly-52M-ddr8 = <1 0 0 0 0>;*/
sunxi-dly-104M = <1 0 0 0 1>;
/*sunxi-dly-208M = <1 1 0 0 0>;*/
sunxi-dly-208M = <1 0 0 0 1>;
/*sunxi-dly-104M-ddr = <1 0 0 0 0>;*/
/*sunxi-dly-208M-ddr = <1 0 0 0 0>;*/
status = "okay";
/*status = "disabled";*/
};
disp: disp@01000000 {
compatible = "allwinner,sunxi-disp";
reg = <0x0 0x01000000 0x0 0x3fffff>,/*de*/
<0x0 0x06510000 0x0 0xfff>,/*disp_if_top*/
<0x0 0x06511000 0x0 0xfff>;/*tcon_lcd0*/
interrupts = <GIC_SPI 87 0x0104>, /*tcon*/
<GIC_SPI 64 0x0104>; /*de*/
clocks = <&clk_de>,
<&clk_display_top>,
<&clk_tcon_lcd0>;
boot_disp = <0>;
fb_base = <0>;
status = "okay";
};
edma: edma@01400400 {
compatible = "allwinner,sunxi-edma";
status = "okay";
};
lcd0: lcd0@01c0c000 {
compatible = "allwinner,sunxi-lcd0";
pinctrl-names = "active","sleep";
status = "okay";
};
soc_tr: tr@01000000 {
compatible = "allwinner,sun50i-tr";
reg = <0x0 0x01000000 0x0 0x000200bc>;
interrupts = <GIC_SPI 96 0x0104>;
clocks = <&clk_de>;
status = "okay";
};
pwm: pwm@0300a000 {
compatible = "allwinner,sunxi-pwm";
reg = <0x0 0x0300a000 0x0 0x3c>;
clocks = <&clk_pwm>;
pwm-number = <2>;
pwm-base = <0x0>;
pwms = <&pwm0>, <&pwm1>;
};
pwm0: pwm0@0300a000 {
compatible = "allwinner,sunxi-pwm0";
pinctrl-names = "active", "sleep";
reg_base = <0x0300a000>;
reg_busy_offset = <0x00>;
reg_busy_shift = <28>;
reg_enable_offset = <0x00>;
reg_enable_shift = <4>;
reg_clk_gating_offset = <0x00>;
reg_clk_gating_shift = <6>;
reg_bypass_offset = <0x00>;
reg_bypass_shift = <9>;
reg_pulse_start_offset = <0x00>;
reg_pulse_start_shift = <8>;
reg_mode_offset = <0x00>;
reg_mode_shift = <7>;
reg_polarity_offset = <0x00>;
reg_polarity_shift = <5>;
reg_period_offset = <0x04>;
reg_period_shift = <16>;
reg_period_width = <16>;
reg_active_offset = <0x04>;
reg_active_shift = <0>;
reg_active_width = <16>;
reg_prescal_offset = <0x00>;
reg_prescal_shift = <0>;
reg_prescal_width = <4>;
};
pwm1: pwm1@0300a000 {
compatible = "allwinner,sunxi-pwm1";
pinctrl-names = "active", "sleep";
reg_base = <0x0300a000>;
reg_busy_offset = <0x00>;
reg_busy_shift = <29>;
reg_enable_offset = <0x00>;
reg_enable_shift = <19>;
reg_clk_gating_offset = <0x00>;
reg_clk_gating_shift = <21>;
reg_bypass_offset = <0x00>;
reg_bypass_shift = <24>;
reg_pulse_start_offset = <0x00>;
reg_pulse_start_shift = <23>;
reg_mode_offset = <0x00>;
reg_mode_shift = <22>;
reg_polarity_offset = <0x00>;
reg_polarity_shift = <20>;
reg_period_offset = <0x08>;
reg_period_shift = <16>;
reg_period_width = <16>;
reg_active_offset = <0x08>;
reg_active_shift = <0>;
reg_active_width = <16>;
reg_prescal_offset = <0x00>;
reg_prescal_shift = <15>;
reg_prescal_width = <4>;
};
s_pwm: s_pwm@07020c00 {
compatible = "allwinner,sunxi-s_pwm";
reg = <0x0 0x07020c00 0x0 0x3c>;
clocks = <&clk_spwm>;
pwm-number = <1>;
pwm-base = <0x10>;
pwms = <&spwm0>;
};
spwm0: spwm0@07020c00 {
compatible = "allwinner,sunxi-pwm16";
pinctrl-names = "active", "sleep";
reg_base = <0x07020c00>;
reg_busy_offset = <0x00>;
reg_busy_shift = <28>;
reg_enable_offset = <0x00>;
reg_enable_shift = <4>;
reg_clk_gating_offset = <0x00>;
reg_clk_gating_shift = <6>;
reg_bypass_offset = <0x00>;
reg_bypass_shift = <9>;
reg_pulse_start_offset = <0x00>;
reg_pulse_start_shift = <8>;
reg_mode_offset = <0x00>;
reg_mode_shift = <7>;
reg_polarity_offset = <0x00>;
reg_polarity_shift = <5>;
reg_period_offset = <0x04>;
reg_period_shift = <16>;
reg_period_width = <16>;
reg_active_offset = <0x04>;
reg_active_shift = <0>;
reg_active_width = <16>;
reg_prescal_offset = <0x00>;
reg_prescal_shift = <0>;
reg_prescal_width = <4>;
};
boot_disp: boot_disp {
compatible = "allwinner,boot_disp";
};
ac200: ac200 {
compatible = "allwinner,sunxi-ac200";
/* clocks = <&clk_tcon0>; */
pinctrl-names = "active","sleep";
status = "okay";
};
vind0:vind@0 {
compatible = "allwinner,sunxi-vin-media", "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
device_id = <0>;
vind0_clk = <300000000>;
reg = <0x0 0x06600000 0x0 0x1000>;
clocks = <&clk_pll_periph0>, <&clk_hosc>, <&clk_pll_periph0>;
pinctrl-names = "mclk0-default","mclk0-sleep";
status = "okay";
isp0:isp@0 {
compatible = "allwinner,sunxi-isp";
reg = <0x0 0x02100000 0x0 0x800>;
interrupts = <GIC_SPI 23 4>;
device_id = <0>;
status = "okay";
};
scaler0:scaler@0 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x02101000 0x0 0x400>;
device_id = <0>;
status = "okay";
};
scaler1:scaler@1 {
compatible = "allwinner,sunxi-scaler";
reg = <0x0 0x02101400 0x0 0x400>;
device_id = <1>;
status = "okay";
};
actuator0:actuator@0 {
device_type = "actuator0";
compatible = "allwinner,sunxi-actuator";
actuator0_name = "ad5820_act";
actuator0_slave = <0x18>;
actuator0_af_pwdn = <>;
actuator0_afvdd = "afvcc-csi";
actuator0_afvdd_vol = <2800000>;
status = "disabled";
};
flash0:flash@0 {
device_type = "flash0";
compatible = "allwinner,sunxi-flash";
flash0_type = <2>;
flash0_en = <>;
flash0_mode = <>;
flash0_flvdd = "";
flash0_flvdd_vol = <>;
device_id = <0>;
status = "disabled";
};
sensor0:sensor@0 {
device_type = "sensor0";
sensor0_mname = "ov5640";
sensor0_twi_cci_id = <0>;
sensor0_twi_addr = <0x78>;
sensor0_pos = "rear";
sensor0_isp_used = <0>;
sensor0_fmt = <0>;
sensor0_stby_mode = <0>;
sensor0_vflip = <0>;
sensor0_hflip = <0>;
sensor0_iovdd = "iovdd-csi";
sensor0_iovdd_vol = <2800000>;
sensor0_avdd_vol = <2800000>;
sensor0_dvdd = "dvdd-csi-18";
sensor0_dvdd_vol = <1500000>;
sensor0_power_en = <>;
sensor0_reset = <&pio PE 14 1 0 1 0>;
sensor0_pwdn = <&pio PE 16 1 0 1 0>;
flash_handle = <&flash0>;
act_handle = <&actuator0>;
status = "okay";
};
sensor1:sensor@1 {
device_type = "sensor1";
sensor1_mname = "ov5647";
sensor1_twi_cci_id = <1>;
sensor1_twi_addr = <0x6c>;
sensor1_pos = "front";
sensor1_isp_used = <0>;
sensor1_fmt = <0>;
sensor1_stby_mode = <0>;
sensor1_vflip = <0>;
sensor1_hflip = <0>;
sensor1_iovdd = "iovdd-csi";
sensor1_iovdd_vol = <2800000>;
sensor1_avdd = "avdd-csi";
sensor1_avdd_vol = <2800000>;
sensor1_dvdd = "dvdd-csi-18";
sensor1_dvdd_vol = <1500000>;
sensor1_power_en = <>;
sensor1_reset = <&pio PE 14 1 0 1 0>;
sensor1_pwdn = <&pio PE 15 1 0 1 0>;
flash_handle = <>;
act_handle = <>;
status = "okay";
};
vinc0:vinc@0 {
device_type = "vinc0";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x06609000 0x0 0x200>;
interrupts = <GIC_SPI 69 4>;
vinc0_csi_sel = <3>;
vinc0_isp_sel = <0>;
vinc0_rear_sensor_sel = <0>;
vinc0_front_sensor_sel = <1>;
vinc0_sensor_list = <0>;
device_id = <0>;
status = "okay";
};
vinc1:vinc@1 {
device_type = "vinc1";
compatible = "allwinner,sunxi-vin-core";
reg = <0x0 0x06609200 0x0 0x200>;
interrupts = <GIC_SPI 70 4>;
vinc1_csi_sel = <3>;
vinc1_isp_sel = <0>;
vinc1_rear_sensor_sel = <0>;
vinc1_front_sensor_sel = <1>;
vinc1_sensor_list = <0>;
device_id = <1>;
status = "okay";
};
};
Vdevice: vdevice@0 {
compatible = "allwinner,sun50i-vdevice";
device_type = "Vdevice";
pinctrl-names = "default";
pinctrl-0 = <&vdevice_pins_a>;
test-gpios = <&pio PB 3 1 2 2 1>;
status = "disable";
};
emce: emce@01905000 {
compatible = "allwinner,sunxi-emce";
device_name = "emce";
reg = <0x0 0x01905000 0 0x100>;
clock-frequency = <300000000>;
clocks = <&clk_emce>, <&clk_pll_periph0x2>;
};
cryptoengine: ce@1904000 {
compatible = "allwinner,sunxi-ce";
device_name = "ce";
reg = <0x0 0x01904000 0x0 0xa0>,
<0x0 0x01904800 0x0 0xa0>; /* Unused */
interrupts = <GIC_SPI 30 0xff01>,
<GIC_SPI 31 0xff01>; /* Unused */
clock-frequency = <300000000>; /* 300MHz */
clocks = <&clk_ce>, <&clk_pll_periph0x2>;
};
di:deinterlace@0x01e00000{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sunxi-deinterlace";
reg = <0x0 0x01e00000 0x0 0x77c>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
/* clocks = <&clk_deinterlace> ,<&clk_pll_periph0>; */
status = "okay";
};
idc:idc@0x08130000{
compatible = "allwinner,sunxi-idc";
device_name = "idc";
reg = <0x0 0x08130000 0x0 0x338>;
irq_delay_en = <0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
irq_channel_array = <
0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0
0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
channel_delay_cycle = < 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0>;
wfi_check_en = <0x0>;
status = "okay";
};
pmu0: pmu0@0{
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
powerkey0: powerkey@0{
status = "okay";
};
regulator0: regulator@0{
status = "okay";
};
axp_gpio0: axp_gpio@0{
gpio-controller;
#size-cells = <0>;
#gpio-cells = <6>;
status = "okay";
};
};
pmu1: pmu1@0{
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
device_type = "pmu1";
charger0: charger@0{
status = "okay";
};
};
nmi:nmi@0x01f00c00{
#address-cells = <1>;
#size-cells = <0>;
compatible = "allwinner,sunxi-nmi";
reg = <0x0 0x01f00c00 0x0 0x50>;
nmi_irq_ctrl = <0x0c>;
nmi_irq_en = <0x40>;
nmi_irq_status = <0x10>;
nmi_irq_mask = <0x50>;
status = "okay";
};
nand0:nand0@04011000 {
compatible = "allwinner,sun50iw8-nand";
device_type = "nand0";
reg = <0x0 0x04011000 0x0 0x1000>; /* nand0 */
interrupts = <GIC_SPI 28 0x04>;
clocks = <&clk_pll_periph1x2>,<&clk_nand0>,<&clk_nand1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&nand0_pins_a &nand0_pins_b>;
pinctrl-1 = <&nand0_pins_c>;
nand0_regulator1 = "vcc-nand";
nand0_regulator2 = "none";
nand0_cache_level = <0x55aaaa55>;
nand0_flush_cache_num = <0x55aaaa55>;
nand0_capacity_level = <0x55aaaa55>;
nand0_id_number_ctl = <0x55aaaa55>;
nand0_print_level = <0x55aaaa55>;
nand0_p0 = <0x55aaaa55>;
nand0_p1 = <0x55aaaa55>;
nand0_p2 = <0x55aaaa55>;
nand0_p3 = <0x55aaaa55>;
status = "okay";
};
sunxi_thermal_sensor:thermal_sensor{
compatible = "allwinner,thermal_sensor";
reg = <0x0 0x05070400 0x0 0x100>;
interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>;
clocks = <&clk_hosc>,<&clk_ths>;
sensor_num = <2>;
combine_num = <2>;
alarm_temp = <100>;
shut_temp= <110>;
status = "okay";
ths_combine0:ths_combine0{
compatible = "allwinner,ths_combine0";
#thermal-sensor-cells = <1>;
combine_sensor_num = <1>;
combine_sensor_type = "CPU";
combine_sensor_temp_type = "max";
combine_sensor_id = <0>;
};
ths_combine1:ths_combine1{
compatible = "allwinner,ths_combine1";
#thermal-sensor-cells = <1>;
combine_sensor_num = <1>;
combine_sensor_type = "GPU";
combine_sensor_temp_type = "max";
combine_sensor_id = <1>;
};
};
cpu_budget_cooling:cpu_budget_cool{
compatible = "allwinner,budget_cooling";
#cooling-cells = <2>;
status = "okay";
state_cnt = <7>;
cluster_num = <1>;
state0 = <1008000 4>;
state1 = <912000 4>;
state2 = <816000 4>;
state3 = <720000 4>;
state4 = <648000 4>;
state5 = <648000 2>;
state6 = <648000 1>;
};
thermal-zones{
cpu_thermal_zone{
polling-delay-passive = <1000>;
polling-delay = <10000>;
thermal-sensors = <&ths_combine0 0>;
trips{
cpu_trip0:t0{
temperature = <65>;
type = "passive";
hysteresis = <0>;
};
cpu_trip1:t1{
temperature = <75>;
type = "passive";
hysteresis = <0>;
};
cpu_trip2:t2{
temperature = <85>;
type = "passive";
hysteresis = <0>;
};
cpu_trip3:t3{
temperature = <95>;
type = "passive";
hysteresis = <0>;
};
cpu_trip4:t4{
temperature = <105>;
type = "passive";
hysteresis = <0>;
};
crt_trip:t8{
temperature = <110>;
type = "critical";
hysteresis = <0>;
};
};
cooling-maps{
bind0{
contribution = <0>;
trip = <&cpu_trip0>;
cooling-device
= <&cpu_budget_cooling 1 1>;
};
bind1{
contribution = <0>;
trip = <&cpu_trip1>;
cooling-device
= <&cpu_budget_cooling 2 2>;
};
bind2{
contribution = <0>;
trip = <&cpu_trip2>;
cooling-device
= <&cpu_budget_cooling 3 4>;
};
bind3{
contribution = <0>;
trip = <&cpu_trip3>;
cooling-device
= <&cpu_budget_cooling 5 5>;
};
bind4{
contribution = <0>;
trip = <&cpu_trip4>;
cooling-device
= <&cpu_budget_cooling 6 6>;
};
};
};
};
gpadc:gpadc{
compatible = "allwinner,sunxi-gpadc";
reg = <0x0 0x05070000 0x0 0x400>;
interrupts = <GIC_SPI 0 IRQ_TYPE_NONE>;
clocks = <&clk_gpadc>;
status = "disable";
};
keyboard0:keyboard{
compatible = "allwinner,keyboard_1200mv";
reg = <0x0 0x05070800 0x0 0x400>;
interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>;
status = "okay";
key_cnt = <5>;
key0 = <115 115>;
key1 = <235 114>;
key2 = <330 139>;
key3 = <420 28>;
key4 = <520 102>;
};
gmac0: eth@01c30000 {
compatible = "allwinner,sunxi-gmac";
reg = <0x0 0x01c30000 0x0 0x40000>,
<0x0 0x01c00030 0x0 0x1>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gmacirq";
/* clocks = <&clk_gmac>, <&clk_ephy>; */
clock-names = "gmac", "ephy";
phy-mode = "rgmii";
tx-delay = <7>;
rx-delay = <31>;
phy-rst;
gmac-power0;
gmac-power1;
gmac-power2;
status = "disable";
};
cpucfg@09010000 {
compatible = "allwinner,sunxi-cpucfg";
reg = <0x0 0x09010000 0x0 0x400>;
};
cpuscfg@07000400 {
compatible = "allwinner,sunxi-cpuscfg";
cpu-soft-entry;
reg = <0x0 0x07000400 0x0 0x800>;
};
sysctl@03000000 {
compatible = "allwinner,sunxi-sysctl";
reg = <0x0 0x03000000 0x0 0x1000>;
};
};
};