353 lines
6.9 KiB
C
353 lines
6.9 KiB
C
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/*
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* The interface function of controlling the SS register.
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*
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* Copyright (C) 2013 Allwinner.
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*
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* Mintow <duanmintao@allwinnertech.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/types.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include "../sunxi_ss.h"
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#include "sunxi_ss_reg.h"
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static int gs_ss_osc_prev_state;
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inline u32 ss_readl(u32 offset)
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{
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return readl(ss_membase() + offset);
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}
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inline void ss_writel(u32 offset, u32 val)
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{
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writel(val, ss_membase() + offset);
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}
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u32 ss_reg_rd(u32 offset)
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{
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return ss_readl(offset);
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}
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void ss_reg_wr(u32 offset, u32 val)
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{
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ss_writel(offset, val);
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}
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void ss_keyselect_set(int select)
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{
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int val = ss_readl(SS_REG_CTL);
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val &= ~SS_REG_CTL_KEY_SELECT_MASK;
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val |= select << SS_REG_CTL_KEY_SELECT_SHIFT;
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ss_writel(SS_REG_CTL, val);
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}
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void ss_keysize_set(int size)
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{
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int val = ss_readl(SS_REG_CTL);
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int type = SS_AES_KEY_SIZE_128;
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switch (size) {
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case AES_KEYSIZE_192:
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type = SS_AES_KEY_SIZE_192;
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break;
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case AES_KEYSIZE_256:
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type = SS_AES_KEY_SIZE_256;
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break;
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default:
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/* type = SS_AES_KEY_SIZE_128; */
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break;
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}
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val &= ~(SS_REG_CTL_KEY_SIZE_MASK);
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val |= (type << SS_REG_CTL_KEY_SIZE_SHIFT);
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ss_writel(SS_REG_CTL, val);
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}
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void ss_flow_enable(int flow)
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{
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int val = ss_readl(SS_REG_CTL);
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val &= ~(SS_STREM1_SELECT|SS_STREM0_SELECT);
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if (flow == 0)
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val |= SS_STREM0_SELECT;
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else
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val |= SS_STREM1_SELECT;
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ss_writel(SS_REG_CTL, val);
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}
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void ss_flow_mode_set(int mode)
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{
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int val = ss_readl(SS_REG_CTL);
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val &= ~(SS_REG_CTL_FLOW_MODE_MASK);
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val |= mode;
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ss_writel(SS_REG_CTL, val);
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}
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void ss_pending_clear(int flow)
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{
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int val = ss_readl(SS_REG_ISR);
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val &= ~(SS_REG_ICR_FLOW0_PENDING_MASK|SS_REG_ICR_FLOW1_PENDING_MASK);
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val |= SS_FLOW_PENDING << flow;
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ss_writel(SS_REG_ISR, val);
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}
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int ss_pending_get(void)
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{
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return ss_readl(SS_REG_ISR);
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}
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void ss_irq_enable(int flow)
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{
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int val = ss_readl(SS_REG_ICR);
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val |= SS_FLOW_END_INT_ENABLE << flow;
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ss_writel(SS_REG_ICR, val);
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}
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void ss_irq_disable(int flow)
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{
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int val = ss_readl(SS_REG_ICR);
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val &= ~(SS_FLOW_END_INT_ENABLE << flow);
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ss_writel(SS_REG_ICR, val);
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}
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/* key: phsical address. */
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void ss_key_set(char *key, int size)
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{
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ss_keyselect_set(SS_KEY_SELECT_INPUT);
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ss_keysize_set(size);
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ss_writel(SS_REG_KEY_L, virt_to_phys(key));
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}
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/* iv: phsical address. */
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void ss_iv_set(char *iv, int size)
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{
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ss_writel(SS_REG_IV_L, virt_to_phys(iv));
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}
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void ss_cntsize_set(int size)
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{
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int val = ss_readl(SS_REG_CTL);
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val &= ~SS_REG_CTL_CTR_SIZE_MASK;
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val |= size << SS_REG_CTL_CTR_SIZE_SHIFT;
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ss_writel(SS_REG_CTL, val);
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}
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void ss_cnt_set(char *cnt, int size)
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{
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ss_cntsize_set(SS_CTR_SIZE_128);
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ss_writel(SS_REG_IV_L, virt_to_phys(cnt));
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}
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void ss_cnt_get(int flow, char *cnt, int size)
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{
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int i;
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int *val = (int *)cnt;
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int base = SS_REG_CNT_BASE;
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if (flow == 1)
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base = SS_REG_FLOW1_CNT_BASE;
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for (i = 0; i < size/4; i++, val++)
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*val = ss_readl(base + i*4);
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}
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void ss_md_get(char *dst, char *src, int size)
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{
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memcpy(dst, src, size);
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}
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void ss_iv_mode_set(int mode)
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{
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int val = ss_readl(SS_REG_CTL);
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val &= ~SS_REG_CTL_IV_MODE_MASK;
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val |= mode << SS_REG_CTL_IV_MODE_SHIFT;
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ss_writel(SS_REG_CTL, val);
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}
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void ss_cts_last(void)
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{
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int val = ss_readl(SS_REG_CTL);
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val |= SS_REG_CTL_AES_CTS_LAST;
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ss_writel(SS_REG_CTL, val);
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}
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void ss_method_set(int dir, int type)
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{
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int val = ss_readl(SS_REG_CTL);
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val &= ~(SS_REG_CTL_OP_DIR_MASK|SS_REG_CTL_METHOD_MASK);
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val |= dir << SS_REG_CTL_OP_DIR_SHIFT;
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val |= type << SS_REG_CTL_METHOD_SHIFT;
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ss_writel(SS_REG_CTL, val);
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}
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void ss_aes_mode_set(int mode)
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{
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int val = ss_readl(SS_REG_CTL);
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val &= ~SS_REG_CTL_OP_MODE_MASK;
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val |= mode << SS_REG_CTL_OP_MODE_SHIFT;
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ss_writel(SS_REG_CTL, val);
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}
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void ss_rng_mode_set(int mode)
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{
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int val = ss_readl(SS_REG_CTL);
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val &= ~SS_REG_CTL_PRNG_MODE_MASK;
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val |= mode << SS_REG_CTL_PRNG_MODE_SHIFT;
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ss_writel(SS_REG_CTL, val);
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}
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void ss_trng_osc_enable(void)
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{
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int val = readl(SS_TRNG_OSC_ADDR);
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gs_ss_osc_prev_state = 1;
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if (val & 1)
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return;
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val |= 1;
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writel(val, SS_TRNG_OSC_ADDR);
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}
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void ss_trng_osc_disable(void)
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{
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int val = 0;
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if (gs_ss_osc_prev_state == 1)
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return;
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val = readl(SS_TRNG_OSC_ADDR);
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val &= ~1;
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writel(val, SS_TRNG_OSC_ADDR);
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}
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void ss_sha_final(void)
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{
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/* unsupported. */
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}
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void ss_check_sha_end(void)
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{
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/* unsupported. */
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}
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void ss_rsa_width_set(int size)
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{
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int val = ss_readl(SS_REG_CTL);
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int width_type = SS_RSA_PUB_MODULUS_WIDTH_512;
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switch (size*8) {
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case 512:
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width_type = SS_RSA_PUB_MODULUS_WIDTH_512;
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break;
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case 1024:
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width_type = SS_RSA_PUB_MODULUS_WIDTH_1024;
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break;
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case 2048:
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width_type = SS_RSA_PUB_MODULUS_WIDTH_2048;
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break;
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case 3072:
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width_type = SS_RSA_PUB_MODULUS_WIDTH_3072;
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break;
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default:
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break;
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}
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val &= ~SS_REG_CTL_RSA_PM_WIDTH_MASK;
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val |= width_type<<SS_REG_CTL_RSA_PM_WIDTH_SHIFT;
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ss_writel(SS_REG_CTL, val);
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}
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void ss_ctrl_start(void)
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{
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int val = ss_readl(SS_REG_CTL);
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val |= 1<<27;
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val |= SS_CTL_START;
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ss_writel(SS_REG_CTL, val);
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}
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void ss_ctrl_stop(void)
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{
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int val = ss_readl(SS_REG_CTL);
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val &= ~SS_CTL_START;
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ss_writel(SS_REG_CTL, val);
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}
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void ss_wait_idle(void)
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{
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while ((ss_readl(SS_REG_CTL) & SS_REG_CTL_IDLE_MASK) == SS_CTL_BUSY) {
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/* SS_DBG("Need wait for the hardware.\n"); */
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msleep(20);
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}
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}
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void ss_data_src_set(int addr)
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{
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ss_writel(SS_REG_DATA_SRC_H, 0);
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ss_writel(SS_REG_DATA_SRC_L, addr);
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}
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void ss_data_dst_set(int addr)
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{
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ss_writel(SS_REG_DATA_DST_H, 0);
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ss_writel(SS_REG_DATA_DST_L, addr);
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}
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void ss_data_len_set(int len)
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{
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ss_writel(SS_REG_DATA_LEN, len);
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}
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int ss_reg_print(char *buf, int len)
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{
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return snprintf(buf, len,
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"The SS control register:\n"
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"[CTL] 0x%02x = 0x%08x\n"
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"[ICR] 0x%02x = 0x%08x, [ISR] 0x%02x = 0x%08x\n"
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"[KEY_L] 0x%02x = 0x%08x, [KEY_H] 0x%02x = 0x%08x\n"
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"[IV_L] 0x%02x = 0x%08x, [IV_H] 0x%02x = 0x%08x\n"
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"[DATA_SRC_L] 0x%02x = 0x%08x, [DATA_SRC_H] 0x%02x = 0x%08x\n"
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"[DATA_DST_L] 0x%02x = 0x%08x, [DATA_DST_H] 0x%02x = 0x%08x\n"
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"[DATA_LEN] 0x%02x = 0x%08x\n"
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"[CNT0-3] 0x%02x = 0x%08x, 0x%08x, 0x%08x, 0x%08x\n"
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"[CNT4-7] 0x%02x = 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
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SS_REG_CTL, ss_readl(SS_REG_CTL),
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SS_REG_ICR, ss_readl(SS_REG_ICR),
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SS_REG_ISR, ss_readl(SS_REG_ISR),
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SS_REG_KEY_L, ss_readl(SS_REG_KEY_L),
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SS_REG_KEY_H, ss_readl(SS_REG_KEY_H),
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SS_REG_IV_L, ss_readl(SS_REG_IV_L),
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SS_REG_IV_H, ss_readl(SS_REG_IV_H),
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SS_REG_DATA_SRC_L, ss_readl(SS_REG_DATA_SRC_L),
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SS_REG_DATA_SRC_H, ss_readl(SS_REG_DATA_SRC_H),
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SS_REG_DATA_DST_L, ss_readl(SS_REG_DATA_DST_L),
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SS_REG_DATA_DST_H, ss_readl(SS_REG_DATA_DST_H),
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SS_REG_DATA_LEN, ss_readl(SS_REG_DATA_LEN),
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SS_REG_CNT(0),
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ss_readl(SS_REG_CNT(0)), ss_readl(SS_REG_CNT(1)),
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ss_readl(SS_REG_CNT(2)), ss_readl(SS_REG_CNT(3)),
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SS_REG_FLOW1_CNT(0),
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ss_readl(SS_REG_FLOW1_CNT(0)), ss_readl(SS_REG_FLOW1_CNT(1)),
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ss_readl(SS_REG_FLOW1_CNT(2)), ss_readl(SS_REG_FLOW1_CNT(3))
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);
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}
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