760 lines
20 KiB
Plaintext
760 lines
20 KiB
Plaintext
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/{
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clocks {
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compatible = "allwinner,clk-init";
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device_type = "clocks";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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reg = <0x0 0x01c20000 0x0 0x0324>; /*cpux space*/
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/* register fixed rate clock*/
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clk_losc_ext: losc_ext {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "losc_ext";
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};
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clk_losc_rc: losc_rc{
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <2000000>;
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clock-output-names = "losc_rc";
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};
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clk_iosc: iosc {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <16000000>;
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clock-output-names = "iosc";
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};
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clk_hosc: hosc {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "hosc";
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};
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clk_ext_clk: ext_clk {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "ext_clk";
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};
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/* register allwinner,sunxi-pll-clock */
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clk_pll_cpu: pll_cpu {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_cpu";
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};
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clk_pll_audio: pll_audio {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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assigned-clock-rates = <24576000>;
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clock-output-names = "pll_audio";
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};
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clk_pll_video0: pll_video0 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_video0";
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};
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clk_pll_ve: pll_ve {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_ve";
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};
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clk_pll_ddr0: pll_ddr0 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_ddr0";
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};
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clk_pll_periph0: pll_periph0 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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assigned-clock-rates = <600000000>;
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lock-mode = "new";
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clock-output-names = "pll_periph0";
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};
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clk_pll_periph1: pll_periph1 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_periph1";
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};
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clk_pll_video1: pll_video1 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_video1";
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};
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clk_pll_sata: pll_sata {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_sata";
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};
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clk_pll_gpu: pll_gpu {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_gpu";
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};
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clk_pll_mipi: pll_mipi {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_mipi";
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};
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clk_pll_de: pll_de {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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assigned-clock-rates = <297000000>;
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assigned-clocks = <&clk_pll_de>;
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clock-output-names = "pll_de";
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};
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clk_pll_ddr1: pll_ddr1 {
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#clock-cells = <0>;
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compatible = "allwinner,pll-clock";
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lock-mode = "new";
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clock-output-names = "pll_ddr1";
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};
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/* register fixed factor clock*/
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clk_pll_audiox8: pll_audiox8 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_audio>;
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clock-mult = <8>;
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clock-div = <1>;
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clock-output-names = "pll_audiox8";
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};
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clk_pll_audiox4: pll_audiox4 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_audio>;
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clock-mult = <8>;
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clock-div = <2>;
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clock-output-names = "pll_audiox4";
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};
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clk_pll_audiox2: pll_audiox2 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_audio>;
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clock-mult = <8>;
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clock-div = <4>;
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clock-output-names = "pll_audiox2";
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};
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clk_pll_periph0x2: pll_periph0x2 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_periph0>;
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clock-mult = <2>;
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clock-div = <1>;
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clock-output-names = "pll_periph0x2";
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};
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clk_pll_periph1x2: pll_periph1x2 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_periph1>;
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clock-mult = <2>;
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clock-div = <1>;
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clock-output-names = "pll_periph1x2";
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};
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clk_pll_video0x2: pll_video0x2 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_video0>;
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clock-mult = <2>;
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clock-div = <1>;
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clock-output-names = "pll_video0x2";
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};
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clk_pll_video1x2: pll_video1x2 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_pll_video1>;
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clock-mult = <2>;
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clock-div = <1>;
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clock-output-names = "pll_video1x2";
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};
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clk_hosc_32k: hosc_32k {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_hosc>;
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clock-mult = <1>;
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clock-div = <750>;
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clock-output-names = "hosc_32k";
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};
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clk_hoscx2: hoscx2 {
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#clock-cells = <0>;
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compatible = "allwinner,fixed-factor-clock";
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clocks = <&clk_hosc>;
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clock-mult = <2>;
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clock-div = <1>;
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clock-output-names = "hoscx2";
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};
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/* register allwinner,sunxi-periph-clock */
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clk_losc: losc {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clock-parents = <&clk_losc_ext>;
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clock-output-names = "losc";
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};
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clk_cpu: cpu {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "cpu";
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};
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clk_cpuapb: cpuapb {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "cpuapb";
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};
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clk_axi: axi {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "axi";
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};
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clk_pll_periphahb0: pll_periphahb0 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "pll_periphahb0";
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};
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clk_ahb1: ahb1 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clock-parents = <&clk_pll_periphahb0>;
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assigned-clock-rates = <200000000>;
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clock-output-names = "ahb1";
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};
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clk_apb1: apb1 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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assigned-clock-rates = <100000000>;
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clock-output-names = "apb1";
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};
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clk_apb2: apb2 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "apb2";
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};
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clk_ths: ths {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "ths";
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};
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clk_nand: nand {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "nand";
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};
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clk_sdmmc0_mod: sdmmc0_mod {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc0_mod";
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};
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clk_sdmmc0_bus: sdmmc0_bus {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc0_bus";
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};
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clk_sdmmc0_rst: sdmmc0_rst {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc0_rst";
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};
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clk_sdmmc1_mod: sdmmc1_mod {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc1_mod";
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};
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clk_sdmmc1_bus: sdmmc1_bus {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc1_bus";
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};
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clk_sdmmc1_rst: sdmmc1_rst {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc1_rst";
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};
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clk_sdmmc2_mod: sdmmc2_mod {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc2_mod";
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};
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clk_sdmmc2_bus: sdmmc2_bus {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc2_bus";
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};
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clk_sdmmc2_rst: sdmmc2_rst {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc2_rst";
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};
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clk_sdmmc3_mod: sdmmc3_mod {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc3_mod";
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};
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clk_sdmmc3_bus: sdmmc3_bus {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc3_bus";
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};
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clk_sdmmc3_rst: sdmmc3_rst {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "sdmmc3_rst";
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};
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clk_ts: ts {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "ts";
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};
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clk_ce: ce {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "ce";
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};
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clk_spi0: spi0 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "spi0";
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};
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clk_spi1: spi1 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "spi1";
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};
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clk_spi2: spi2 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "spi2";
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};
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clk_spi3: spi3 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "spi3";
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};
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clk_i2s0: i2s0 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "i2s0";
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};
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clk_i2s1: i2s1 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
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clock-output-names = "i2s1";
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};
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clk_i2s2: i2s2 {
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#clock-cells = <0>;
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compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "i2s2";
|
||
|
|
};
|
||
|
|
clk_ac97: ac97 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "ac97";
|
||
|
|
};
|
||
|
|
clk_spdif: spdif {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "spdif";
|
||
|
|
};
|
||
|
|
clk_keypad: keypad {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "keypad";
|
||
|
|
};
|
||
|
|
clk_sata: sata {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "sata";
|
||
|
|
};
|
||
|
|
clk_usbphy0: usbphy0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbphy0";
|
||
|
|
};
|
||
|
|
clk_usbphy1: usbphy1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbphy1";
|
||
|
|
};
|
||
|
|
clk_usbphy2: usbphy2 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbphy2";
|
||
|
|
};
|
||
|
|
clk_usbohci0: usbohci0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbohci0";
|
||
|
|
};
|
||
|
|
clk_usbohci1: usbohci1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbohci1";
|
||
|
|
};
|
||
|
|
clk_usbohci2: usbohci2 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbohci2";
|
||
|
|
};
|
||
|
|
clk_ir0: ir0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "ir0";
|
||
|
|
};
|
||
|
|
clk_ir1: ir1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "ir1";
|
||
|
|
};
|
||
|
|
clk_de: de {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clock-parents = <&clk_pll_de>;
|
||
|
|
assigned-clocks = <&clk_de>;
|
||
|
|
assigned-clock-rates = <297000000>;
|
||
|
|
clock-output-names = "de";
|
||
|
|
};
|
||
|
|
clk_de_mp: de_mp {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clocks = <&clk_de_mp>;
|
||
|
|
assigned-clock-parents = <&clk_pll_de>;
|
||
|
|
assigned-clock-rates = <297000000>;
|
||
|
|
clock-output-names = "de_mp";
|
||
|
|
};
|
||
|
|
clk_tcon_top: tcon_top {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "tcon_top";
|
||
|
|
assigned-clocks = <&clk_tcon_top>;
|
||
|
|
};
|
||
|
|
clk_tcon0: tcon0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clock-parents = <&clk_pll_mipi>;
|
||
|
|
assigned-clocks = <&clk_tcon0>;
|
||
|
|
clock-output-names = "tcon0";
|
||
|
|
};
|
||
|
|
clk_tcon1: tcon1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clock-parents = <&clk_pll_video0>;
|
||
|
|
assigned-clocks = <&clk_tcon1>;
|
||
|
|
clock-output-names = "tcon1";
|
||
|
|
};
|
||
|
|
clk_tcon_tv0: tcon_tv0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clock-parents = <&clk_pll_video1>;
|
||
|
|
assigned-clocks = <&clk_tcon_tv0>;
|
||
|
|
clock-output-names = "tcon_tv0";
|
||
|
|
};
|
||
|
|
clk_tcon_tv1: tcon_tv1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clock-parents = <&clk_pll_video1>;
|
||
|
|
assigned-clocks = <&clk_tcon_tv1>;
|
||
|
|
clock-output-names = "tcon_tv1";
|
||
|
|
};
|
||
|
|
clk_deinterlace: deinterlace {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "deinterlace";
|
||
|
|
};
|
||
|
|
clk_csi_s: csi_s {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "csi_s";
|
||
|
|
};
|
||
|
|
clk_csi0_m: csi0_m {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "csi0_m";
|
||
|
|
};
|
||
|
|
clk_csi1_m: csi1_m {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "csi1_m";
|
||
|
|
};
|
||
|
|
clk_ve: ve {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "ve";
|
||
|
|
};
|
||
|
|
clk_adda: adda {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "adda";
|
||
|
|
};
|
||
|
|
clk_addax4: addax4 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "addax4";
|
||
|
|
};
|
||
|
|
clk_avs: avs {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "avs";
|
||
|
|
};
|
||
|
|
clk_hdmi: hdmi {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clocks = <&clk_hdmi>;
|
||
|
|
assigned-clock-parents = <&clk_pll_video1>;
|
||
|
|
clock-output-names = "hdmi";
|
||
|
|
};
|
||
|
|
clk_hdmi_slow: hdmi_slow {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "hdmi_slow";
|
||
|
|
};
|
||
|
|
clk_mbus: mbus {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clock-parents = <&clk_pll_periph0x2>;
|
||
|
|
assigned-clock-rates = <400000000>;
|
||
|
|
clock-output-names = "mbus";
|
||
|
|
};
|
||
|
|
clk_mipidsi: mipidsi {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "mipidsi";
|
||
|
|
assigned-clocks = <&clk_mipidsi>;
|
||
|
|
};
|
||
|
|
clk_tve_top: tve_top {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "tve_top";
|
||
|
|
assigned-clock-parents = <&clk_pll_video1>;
|
||
|
|
assigned-clocks = <&clk_tve_top>;
|
||
|
|
};
|
||
|
|
clk_tve0: tve0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clock-parents = <&clk_pll_video1>;
|
||
|
|
assigned-clocks = <&clk_tve0>;
|
||
|
|
clock-output-names = "tve0";
|
||
|
|
};
|
||
|
|
clk_tve1: tve1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clock-parents = <&clk_pll_video1>;
|
||
|
|
assigned-clocks = <&clk_tve1>;
|
||
|
|
clock-output-names = "tve1";
|
||
|
|
};
|
||
|
|
clk_tvd_top: tvd_top {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "tvd_top";
|
||
|
|
assigned-clock-parents = <&clk_pll_video1>;
|
||
|
|
assigned-clocks = <&clk_tvd_top>;
|
||
|
|
};
|
||
|
|
clk_tvd0: tvd0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clock-parents = <&clk_pll_video1>;
|
||
|
|
assigned-clocks = <&clk_tvd0>;
|
||
|
|
clock-output-names = "tvd0";
|
||
|
|
};
|
||
|
|
clk_tvd1: tvd1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clock-parents = <&clk_pll_video1>;
|
||
|
|
assigned-clocks = <&clk_tvd1>;
|
||
|
|
clock-output-names = "tvd1";
|
||
|
|
};
|
||
|
|
clk_tvd2: tvd2 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clock-parents = <&clk_pll_video1>;
|
||
|
|
assigned-clocks = <&clk_tvd2>;
|
||
|
|
clock-output-names = "tvd2";
|
||
|
|
};
|
||
|
|
clk_tvd3: tvd3 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clock-parents = <&clk_pll_video1>;
|
||
|
|
assigned-clocks = <&clk_tvd3>;
|
||
|
|
clock-output-names = "tvd3";
|
||
|
|
};
|
||
|
|
clk_outa: outa {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
assigned-clock-parents = <&clk_losc>;
|
||
|
|
clock-output-names = "outa";
|
||
|
|
};
|
||
|
|
clk_outb: outb {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "outb";
|
||
|
|
};
|
||
|
|
clk_gpu: gpu {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "gpu";
|
||
|
|
};
|
||
|
|
clk_usbehci0: usbehci0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbehci0";
|
||
|
|
};
|
||
|
|
clk_usbehci1: usbehci1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbehci1";
|
||
|
|
};
|
||
|
|
clk_usbehci2: usbehci2 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbehci2";
|
||
|
|
};
|
||
|
|
clk_usbohci012m: usbohci012m {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbohci012m";
|
||
|
|
};
|
||
|
|
clk_usbohci112m: usbohci112m {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbohci112m";
|
||
|
|
};
|
||
|
|
clk_usbohci212m: usbohci212m {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbohci212m";
|
||
|
|
};
|
||
|
|
clk_usbotg: usbotg {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "usbotg";
|
||
|
|
};
|
||
|
|
clk_gmac: gmac {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "gmac";
|
||
|
|
};
|
||
|
|
clk_emac: emac {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "emac";
|
||
|
|
};
|
||
|
|
clk_sdram: sdram {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "sdram";
|
||
|
|
};
|
||
|
|
clk_dma: dma {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "dma";
|
||
|
|
};
|
||
|
|
clk_lvds: lvds {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "lvds";
|
||
|
|
};
|
||
|
|
clk_uart0: uart0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "uart0";
|
||
|
|
};
|
||
|
|
clk_uart1: uart1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "uart1";
|
||
|
|
};
|
||
|
|
clk_uart2: uart2 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "uart2";
|
||
|
|
};
|
||
|
|
clk_uart3: uart3 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "uart3";
|
||
|
|
};
|
||
|
|
clk_uart4: uart4 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "uart4";
|
||
|
|
};
|
||
|
|
clk_uart5: uart5 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "uart5";
|
||
|
|
};
|
||
|
|
clk_uart6: uart6 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "uart6";
|
||
|
|
};
|
||
|
|
clk_uart7: uart7 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "uart7";
|
||
|
|
};
|
||
|
|
clk_scr0: scr0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "scr0";
|
||
|
|
};
|
||
|
|
clk_twi0: twi0 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "twi0";
|
||
|
|
};
|
||
|
|
clk_twi1: twi1 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "twi1";
|
||
|
|
};
|
||
|
|
clk_twi2: twi2 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "twi2";
|
||
|
|
};
|
||
|
|
clk_twi3: twi3 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "twi3";
|
||
|
|
};
|
||
|
|
clk_twi4: twi4 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "twi4";
|
||
|
|
};
|
||
|
|
clk_pio: pio {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "pio";
|
||
|
|
};
|
||
|
|
clk_ps20: ps20 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "ps20";
|
||
|
|
};
|
||
|
|
clk_ps21: ps21 {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "ps21";
|
||
|
|
};
|
||
|
|
clk_can: can {
|
||
|
|
#clock-cells = <0>;
|
||
|
|
compatible = "allwinner,periph-clock";
|
||
|
|
clock-output-names = "can";
|
||
|
|
};
|
||
|
|
};/*clocks end*/
|
||
|
|
};
|