466 lines
11 KiB
C
466 lines
11 KiB
C
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/*
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* (C) Copyright 20016-2020
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* wangwei <wangwei@allwinnertech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <usb/ehci-fsl.h>
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#include <sys_config.h>
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#include <asm/arch/ccmu.h>
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#include "ehci.h"
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#include "ehci-sunxi.h"
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static u32 usb_vbase = SUNXI_EHCI1_BASE;
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static u32 usb_vbus_handle = 0;
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typedef struct _ehci_config
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{
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u32 ehci_base;
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u32 bus_soft_reset_ofs;
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u32 bus_clk_gating_ofs;
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u32 phy_reset_ofs;
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u32 phy_slk_gatimg_ofs;
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u32 usb0_support;
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char name[32];
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char node[32];
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}ehci_config_t;
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#ifdef CONFIG_USB_EHCI_SUNXI
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static ehci_config_t ehci_cfg[] = {
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{SUNXI_EHCI0_BASE, USBEHCI0_RST_BIT, USBEHCI0_GATIING_BIT, USBPHY0_RST_BIT, USBPHY0_SCLK_GATING_BIT, 1, "ehci0", "/soc/usbc0"},
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#ifndef CONFIG_ARCH_SUN50IW6P1
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{SUNXI_EHCI1_BASE, USBEHCI1_RST_BIT, USBEHCI1_GATIING_BIT, USBPHY1_RST_BIT, USBPHY1_SCLK_GATING_BIT, 0, "ehci1", "/soc/usbc1"},
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#endif
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};
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#endif
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/*
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*******************************************************************************
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* pin_init
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*
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* Description:
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* void
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*
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* Parameters:
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* void
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*
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* Return value:
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* void
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*
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* note:
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* void
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*
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*******************************************************************************
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*/
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ulong config_usb_pin(char *path, char *prop)
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{
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user_gpio_set_t usbc_gpio;
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int status = -1;
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ulong pin_handle = 0;
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do{
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if(fdt_get_one_gpio(path,prop,&usbc_gpio))
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{
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break;
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}
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pin_handle = gpio_request(&usbc_gpio, 1);
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if(!pin_handle)
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{
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break;
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}
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/* set config, ouput */
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if(gpio_set_one_pin_io_status(pin_handle, 1, NULL))
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{
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break;
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}
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/* reserved is pull down */
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if(gpio_set_one_pin_pull(pin_handle, 2, NULL))
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{
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break;
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}
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status = 0;
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}while(0);
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printf("config usb pin %s\n",status?"fail":"success");
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return status ? 0 : pin_handle;
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}
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s32 __attribute__((weak)) axp_usb_vbus_output(void){ return 0;}
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int alloc_pin(int index)
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{
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if (axp_usb_vbus_output())
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return 0;
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usb_vbus_handle = config_usb_pin(ehci_cfg[index].node,
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"usb_drv_vbus_gpio");
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return usb_vbus_handle ? 0:-1;
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}
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/*
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*******************************************************************************
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* pin_exit
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*
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* Description:
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* void
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*
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* Parameters:
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* void
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*
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* Return value:
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* void
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*
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* note:
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* void
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*
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*******************************************************************************
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*/
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void free_pin(void)
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{
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if(usb_vbus_handle)
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gpio_release(usb_vbus_handle, 0);
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usb_vbus_handle = 0;
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return;
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}
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/*
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*******************************************************************************
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* open_usb_clock
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*
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* Description:
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*
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*
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* Parameters:
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* void
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*
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* Return value:
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* void
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*
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* note:
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* void
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*
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*******************************************************************************
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*/
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#if defined(SUNXI_NCAT_VERSION1)
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u32 open_usb_clock(int index)
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{
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u32 reg_value = 0;
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u32 ccmu_base = SUNXI_CCM_BASE;
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/* Bus reset and gating for ehci */
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reg_value = USBC_Readl(ccmu_base + CCMU_USB_BUS_GATING_RST);
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reg_value |= (1 << ehci_cfg[index].bus_soft_reset_ofs);
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reg_value |= (1 << ehci_cfg[index].bus_clk_gating_ofs);
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USBC_Writel(reg_value, (ccmu_base + CCMU_USB_BUS_GATING_RST));
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/* open clk for usb phy */
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if (index == 0) {
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reg_value = USBC_Readl(ccmu_base + CCMU_USB0_CLK);
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reg_value |= (1 << ehci_cfg[index].phy_slk_gatimg_ofs);
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reg_value |= (1 << ehci_cfg[index].phy_reset_ofs);
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USBC_Writel(reg_value, (ccmu_base + CCMU_USB0_CLK));
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} else if (index == 1) {
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#ifndef CONFIG_ARCH_SUN50IW6P1
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reg_value = USBC_Readl(ccmu_base + CCMU_USB1_CLK);
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reg_value |= (1 << ehci_cfg[index].phy_slk_gatimg_ofs);
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reg_value |= (1 << ehci_cfg[index].phy_reset_ofs);
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USBC_Writel(reg_value, (ccmu_base + CCMU_USB1_CLK));
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#endif
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}
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printf("config usb clk ok\n");
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return 0;
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}
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/*
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*******************************************************************************
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* close_usb_clock
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*
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* Description:
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*
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*
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* Parameters:
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* void
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*
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* Return value:
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* void
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*
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* note:
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* void
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*
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*******************************************************************************
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*/
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u32 close_usb_clock(int index)
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{
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u32 reg_value = 0;
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u32 ccmu_base = SUNXI_CCM_BASE;
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/* Bus reset and gating for ehci */
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reg_value = USBC_Readl(ccmu_base + CCMU_USB_BUS_GATING_RST);
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reg_value &= ~(1 << ehci_cfg[index].bus_soft_reset_ofs);
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reg_value &= ~(1 << ehci_cfg[index].bus_clk_gating_ofs);
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USBC_Writel(reg_value, (ccmu_base + CCMU_USB_BUS_GATING_RST));
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/* close clk for usb phy */
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if (index == 0) {
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reg_value = USBC_Readl(ccmu_base + CCMU_USB0_CLK);
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reg_value &= ~(1 << ehci_cfg[index].phy_slk_gatimg_ofs);
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reg_value &= ~(1 << ehci_cfg[index].phy_reset_ofs);
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USBC_Writel(reg_value, (ccmu_base + CCMU_USB0_CLK));
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} else if (index == 1) {
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#ifndef CONFIG_ARCH_SUN50IW6P1
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reg_value = USBC_Readl(ccmu_base + CCMU_USB1_CLK);
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reg_value &= ~(1 << ehci_cfg[index].phy_slk_gatimg_ofs);
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reg_value &= ~(1 << ehci_cfg[index].phy_reset_ofs);
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USBC_Writel(reg_value, (ccmu_base + CCMU_USB1_CLK));
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#endif
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}
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return 0;
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}
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#else
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u32 open_usb_clock(int index)
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{
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u32 reg_value = 0;
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u32 ccmu_base = SUNXI_CCM_BASE;
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/* BUS clk gating for USB EHCI */
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reg_value = USBC_Readl(ccmu_base + BUS_CLK_GATING_REG);
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reg_value |= (1 << ehci_cfg[index].bus_soft_reset_ofs);
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USBC_Writel(reg_value, (ccmu_base + BUS_CLK_GATING_REG));
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/* Bus soft reset for USB EHCI */
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reg_value = USBC_Readl(ccmu_base + BUS_SOFTWARE_RESET_REG);
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reg_value |= (1 << ehci_cfg[index].bus_clk_gating_ofs);
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USBC_Writel(reg_value, (ccmu_base + BUS_SOFTWARE_RESET_REG));
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/* open clock for USB PHY */
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reg_value = USBC_Readl(ccmu_base + USBPHY_CONFIG_REG);
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reg_value |= (1 << ehci_cfg[index].phy_slk_gatimg_ofs);
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reg_value |= (1 << ehci_cfg[index].phy_reset_ofs);
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USBC_Writel(reg_value, (ccmu_base + USBPHY_CONFIG_REG));
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printf("config usb clk ok\n");
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return 0;
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}
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/*
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*******************************************************************************
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* close_usb_clock
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*
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* Description:
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*
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*
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* Parameters:
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* void
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*
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* Return value:
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* void
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*
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* note:
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* void
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*
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*******************************************************************************
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*/
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u32 close_usb_clock(int index)
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{
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u32 reg_value = 0;
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u32 ccmu_base = SUNXI_CCM_BASE;
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/* Bus soft reset for USB EHCI */
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reg_value = USBC_Readl(ccmu_base + BUS_SOFTWARE_RESET_REG);
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reg_value &= ~(1 << ehci_cfg[index].bus_soft_reset_ofs);
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USBC_Writel(reg_value, (ccmu_base + BUS_SOFTWARE_RESET_REG));
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/* BUS clk gating for USB EHCI */
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reg_value = USBC_Readl(ccmu_base + BUS_CLK_GATING_REG);
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reg_value &= ~(1 << ehci_cfg[index].bus_clk_gating_ofs);
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USBC_Writel(reg_value, (ccmu_base + BUS_CLK_GATING_REG));
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/* close clock for USB PHY */
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reg_value = USBC_Readl(ccmu_base + USBPHY_CONFIG_REG);
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/* PHY0 */
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reg_value &= ~(1 << ehci_cfg[index].phy_slk_gatimg_ofs);
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reg_value &= ~(1 << ehci_cfg[index].phy_reset_ofs);
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USBC_Writel(reg_value, (ccmu_base + USBPHY_CONFIG_REG));
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return 0;
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}
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#endif
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/*
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*******************************************************************************
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* enable_usb_passby
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*
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* Description:
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* void
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*
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* Parameters:
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* void
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*
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* Return value:
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* void
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*
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* note:
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* void
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*
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*******************************************************************************
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*/
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void usb_passby(int index, u32 enable)
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{
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unsigned long reg_value = 0;
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u32 ehci_vbase = ehci_cfg[index].ehci_base;
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if(ehci_cfg[index].usb0_support)
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{
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/* the default mode of usb0 is OTG,so change it here. */
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reg_value = USBC_Readl(SUNXI_USBOTG_BASE + 0x420);
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reg_value &= ~(0x01);
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USBC_Writel(reg_value, (SUNXI_USBOTG_BASE + 0x420));
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}
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reg_value = USBC_Readl(ehci_vbase + 0x810);
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reg_value &= ~(0x01<<1);
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USBC_Writel(reg_value, (ehci_vbase + 0x810));
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reg_value = USBC_Readl(ehci_vbase + SUNXI_USB_PMU_IRQ_ENABLE);
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if(enable){
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reg_value |= (1 << 10); /* AHB Master interface INCR8 enable */
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reg_value |= (1 << 9); /* AHB Master interface burst type INCR4 enable */
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reg_value |= (1 << 8); /* AHB Master interface INCRX align enable */
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reg_value |= (1 << 0); /* ULPI bypass enable */
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}else if(!enable){
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reg_value &= ~(1 << 10); /* AHB Master interface INCR8 disable */
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reg_value &= ~(1 << 9); /* AHB Master interface burst type INCR4 disable */
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reg_value &= ~(1 << 8); /* AHB Master interface INCRX align disable */
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reg_value &= ~(1 << 0); /* ULPI bypass disable */
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}
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USBC_Writel(reg_value, (ehci_vbase + SUNXI_USB_PMU_IRQ_ENABLE));
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return;
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}
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void sunxi_set_vbus(int on_off)
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{
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if(usb_vbus_handle)
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gpio_write_one_pin_value(usb_vbus_handle, on_off, NULL);
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return;
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}
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|
/*
|
||
|
|
*******************************************************************************
|
||
|
|
* sunxi_start_ehci
|
||
|
|
*
|
||
|
|
* Description:
|
||
|
|
* void
|
||
|
|
*
|
||
|
|
* Parameters:
|
||
|
|
* void
|
||
|
|
*
|
||
|
|
* Return value:
|
||
|
|
* void
|
||
|
|
*
|
||
|
|
* note:
|
||
|
|
* void
|
||
|
|
*
|
||
|
|
*******************************************************************************
|
||
|
|
*/
|
||
|
|
int sunxi_start_ehci(int index)
|
||
|
|
{
|
||
|
|
if(alloc_pin(index))
|
||
|
|
return -1;
|
||
|
|
open_usb_clock(index);
|
||
|
|
usb_passby(index, 1);
|
||
|
|
sunxi_set_vbus(1);
|
||
|
|
__msdelay(800);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
*******************************************************************************
|
||
|
|
* sunxi_stop_ehci
|
||
|
|
*
|
||
|
|
* Description:
|
||
|
|
* void
|
||
|
|
*
|
||
|
|
* Parameters:
|
||
|
|
* void
|
||
|
|
*
|
||
|
|
* Return value:
|
||
|
|
* void
|
||
|
|
*
|
||
|
|
* note:
|
||
|
|
* void
|
||
|
|
*
|
||
|
|
*******************************************************************************
|
||
|
|
*/
|
||
|
|
void sunxi_stop_ehci(int index)
|
||
|
|
{
|
||
|
|
sunxi_set_vbus(0);
|
||
|
|
usb_passby(index, 0);
|
||
|
|
close_usb_clock(index);
|
||
|
|
free_pin();
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Create the appropriate control structures to manage
|
||
|
|
* a new EHCI host controller.
|
||
|
|
*/
|
||
|
|
int ehci_hcd_init(int index, enum usb_init_type init,
|
||
|
|
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
|
||
|
|
{
|
||
|
|
printf("start sunxi %s...\n", ehci_cfg[index].name);
|
||
|
|
if(index > ARRAY_SIZE(ehci_cfg))
|
||
|
|
{
|
||
|
|
printf("the index is too large\n");
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
usb_vbase = ehci_cfg[index].ehci_base;
|
||
|
|
if(sunxi_start_ehci(index))
|
||
|
|
{
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
*hccr = (struct ehci_hccr *)usb_vbase;
|
||
|
|
*hcor = (struct ehci_hcor *)((uint32_t) (*hccr) +
|
||
|
|
HC_LENGTH(ehci_readl(&((*hccr)->cr_capbase))));
|
||
|
|
|
||
|
|
printf("sunxi %s init ok...\n", ehci_cfg[index].name);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Destroy the appropriate control structures corresponding
|
||
|
|
* the the EHCI host controller.
|
||
|
|
*/
|
||
|
|
int ehci_hcd_stop(int index)
|
||
|
|
{
|
||
|
|
sunxi_stop_ehci(index);
|
||
|
|
printf("stop sunxi %s ok...\n", ehci_cfg[index].name);
|
||
|
|
return 0;
|
||
|
|
}
|