296 lines
8.7 KiB
C
296 lines
8.7 KiB
C
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/*
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*
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* Copyright(c) 2013-2015 Allwinnertech Co., Ltd.
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* http://www.allwinnertech.com
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*
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* Author: huangshr <huangshr@allwinnertech.com>
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*
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* sunxi cpuidle head file
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <asm/smp_plat.h>
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#include <linux/percpu.h>
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#include <linux/cpumask.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/cpu_pm.h>
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#include <linux/arisc/arisc.h>
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#include <asm/smp.h>
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#include <asm/io.h>
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#include <asm/cp15.h>
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#include <asm/cacheflush.h>
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#include <asm/suspend.h>
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#include <asm/cputype.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/mcpm.h>
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#include <mach/platform.h>
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#include <mach/cci.h>
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#ifndef __SUNXI_CPUIDLE_H
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#define __SUNXI_CPUIDLE_H
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#ifndef IO_ADDRESS
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#define IO_ADDRESS(x) ((x) + 0xf0000000)
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#endif
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/* for cross platform*/
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#if defined(CONFIG_ARCH_SUN9IW1P1)
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extern cpumask_t cpu_power_up_state_mask;
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#define SUN9I_IDLE_CPU_IS_WFI_MODE(cluster, cpu) (readl(IO_ADDRESS(SUNXI_R_CPUCFG_PBASE) + SUNXI_CLUSTER_CPU_STATUS(cluster)) & (1 << (16 + cpu)))
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extern int sun9i_cpu_power_set(unsigned int cluster, unsigned int cpu, bool enable);
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extern int sun9i_cluster_power_set(unsigned int cluster, bool enable);
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#endif
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#if defined(CONFIG_ARCH_SUN8IW6P1)
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#define SUN8I_IDLE_CPU_IS_WFI_MODE(cluster, cpu) (readl(IO_ADDRESS(SUNXI_R_CPUCFG_PBASE) + SUNXI_CLUSTER_CPU_STATUS(cluster)) & (1 << (16 + cpu)))
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extern int sun8i_cpu_power_set(unsigned int cluster, unsigned int cpu, bool enable);
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extern int sun8i_cluster_power_control(unsigned int cluster, bool enable);
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#endif
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#if defined(CONFIG_ARCH_SUN8IW1P1) || defined(CONFIG_ARCH_SUN8IW3P1) || defined(CONFIG_ARCH_SUN8IW5P1)
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#include <mach/sun8i/platsmp.h>
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extern void sunxi_set_cpus_boot_entry(int cpu, void *entry);
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#define IDLE_CPU_IS_WFI_MODE(cpu) (readl(IO_ADDRESS(SUNXI_R_CPUCFG_PBASE) + CPUX_STATUS(cpu)) & (1<<2))
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#endif
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static inline void sunxi_cpuidle_power_up_cpu(unsigned int cpu)
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{
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unsigned int cluster_id, cpu_id, mpidr;
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mpidr = cpu_logical_map(cpu);
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cpu_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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#if defined(CONFIG_ARCH_SUN9IW1P1)
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mcpm_set_entry_vector(cpu_id, cluster_id, NULL);
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sun9i_cpu_power_set(cluster_id, cpu_id, 1);
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mcpm_set_entry_vector(cpu_id, cluster_id, cpu_resume);
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#endif
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#if defined(CONFIG_ARCH_SUN8IW6P1)
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mcpm_set_entry_vector(cpu_id, cluster_id, NULL);
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sun8i_cpu_power_set(cluster_id, cpu_id, 1);
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mcpm_set_entry_vector(cpu_id, cluster_id, cpu_resume);
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#endif
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#if defined(CONFIG_ARCH_SUN8IW1P1) || defined(CONFIG_ARCH_SUN8IW3P1) || defined(CONFIG_ARCH_SUN8IW5P1)
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/* set resume address */
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sunxi_set_cpus_boot_entry(cpu, cpu_resume);
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enable_cpu(cpu);
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#endif
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}
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static inline void sunxi_cpuidle_power_down_cpu(unsigned int cpu)
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{
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unsigned int cluster_id, cpu_id, mpidr;
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mpidr = cpu_logical_map(cpu);
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cpu_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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#if defined(CONFIG_ARCH_SUN9IW1P1)
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sun9i_cpu_power_set(cluster_id, cpu_id, 0);
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#endif
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#if defined(CONFIG_ARCH_SUN8IW6P1)
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sun8i_cpu_power_set(cluster_id, cpu_id, 0);
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#endif
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#if defined(CONFIG_ARCH_SUN8IW1P1) || defined(CONFIG_ARCH_SUN8IW3P1) || defined(CONFIG_ARCH_SUN8IW5P1)
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disable_cpu(cpu);
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#endif
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}
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static inline bool SUNXI_CPU_IS_WFI_MODE(unsigned int cpu)
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{
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unsigned int cluster_id, cpu_id, mpidr;
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int ret = 0;
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mpidr = cpu_logical_map(cpu);
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cpu_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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#if defined(CONFIG_ARCH_SUN9IW1P1)
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return SUN9I_IDLE_CPU_IS_WFI_MODE(cluster_id, cpu_id);
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#elif defined(CONFIG_ARCH_SUN8IW6P1)
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return SUN8I_IDLE_CPU_IS_WFI_MODE(cluster_id, cpu_id);
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#elif defined(CONFIG_ARCH_SUN8IW1P1) || defined(CONFIG_ARCH_SUN8IW3P1) || defined(CONFIG_ARCH_SUN8IW5P1)
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return IDLE_CPU_IS_WFI_MODE(cpu);
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#else
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return ret;
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#endif
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return ret;
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}
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/* end for cross platform */
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#define A7_CLUSTER (0)
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#define A15_CLUSTER (1)
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#define MAX_CLUSTERS (2)
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#define MAX_CPU_IN_CLUSTER (4)
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#if defined(CONFIG_ARCH_SUN8IW6P1)
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#define MSG_VBASE IO_ADDRESS(SUNXI_SRAM_A2_PBASE)
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#define ARISC_MESSAGE_POOL_END (SUNXI_SRAM_A2_SIZE)
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#define MSG_VEND (MSG_VBASE + ARISC_MESSAGE_POOL_END)
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/* flg between cpux & cpus for synchronization */
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#define CLUSTER_CPUX_FLG(cluster, cpu) (MSG_VEND - 4 - 16*(cluster) - 4*(cpu))
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#define CLUSTER_CPUS_FLG(cluster, cpu) (MSG_VEND - 36 - 16*(cluster) - 4*(cpu))
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#define CLUSTER_CPUW_FLG(cluster, cpu) (MSG_VEND - 68 - 16*(cluster) - 4*(cpu))
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#define CLUSTER_CPUS_GICW_FLG() (MSG_VEND - 100)
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#endif
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static inline void sunxi_idle_cpu_die(void)
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{
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unsigned long actlr;
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#if defined(CONFIG_ARCH_SUN8IW6P1)
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unsigned int mpidr = read_cpuid_mpidr();
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unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
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unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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#endif
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gic_cpu_if_down(0);
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#if defined(CONFIG_ARCH_SUN8IW6P1)
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writel(0, CLUSTER_CPUW_FLG(cluster, cpu)); /* for cpus sync */
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#endif
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/* step1: disable cache */
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asm("mrc p15, 0, %0, c1, c0, 0" : "=r" (actlr));
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actlr &= ~(1<<2);
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asm("mcr p15, 0, %0, c1, c0, 0\n" : : "r" (actlr));
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/* step2: clean and ivalidate L1 cache */
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flush_cache_louis();
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/* step3: execute a CLREX instruction */
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asm("clrex" : : : "memory", "cc");
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/* step4: switch cpu from SMP mode to AMP mode, aim is to disable cache coherency */
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asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
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actlr &= ~(1<<6);
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asm("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));
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/* step5: execute an ISB instruction */
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isb();
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/* step6: execute a DSB instruction */
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dsb();
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/* step7: execute a WFI instruction */
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while (1) {
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asm("wfi" : : : "memory", "cc");
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}
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}
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extern void __mcpm_outbound_leave_critical(unsigned int cluster, int state);
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static inline void sunxi_idle_cluster_die(unsigned int cluster)
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{
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unsigned long actlr;
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#if defined(CONFIG_ARCH_SUN8IW6P1)
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unsigned int mpidr = read_cpuid_mpidr();
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unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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#endif
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gic_cpu_if_down(0);
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#if defined(CONFIG_ARCH_SUN8IW6P1)
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writel(0, CLUSTER_CPUW_FLG(cluster, cpu)); /* for cpus sync */
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#endif
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/* step1: disable cache */
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asm("mrc p15, 0, %0, c1, c0, 0" : "=r" (actlr));
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actlr &= ~(1<<2);
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asm("mcr p15, 0, %0, c1, c0, 0\n" : : "r" (actlr));
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/* step2: clean and ivalidate L1 cache */
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flush_cache_all();
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outer_flush_all();
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/* step3: execute a CLREX instruction */
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asm("clrex" : : : "memory", "cc");
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/* step4: switch cpu from SMP mode to AMP mode, aim is to disable cache coherency */
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asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
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actlr &= ~(1<<6);
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asm("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));
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#if (defined CONFIG_ARCH_SUN8IW6P1) || (defined CONFIG_ARCH_SUN9IW1P1)
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__mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
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/* disable cluster cci snoop */
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disable_cci_snoops(cluster);
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#endif
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/* step5: execute an ISB instruction */
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isb();
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/* step6: execute a DSB instruction */
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dsb();
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/* step7: execute a WFI instruction */
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while (1) {
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asm("wfi" : : : "memory", "cc");
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}
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}
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/*gic check interrupt*/
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#define SGI_MASK 0xFFFF
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static void __iomem *distbase = (void __iomem *)SUNXI_GIC_DIST_VBASE;
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static inline bool sunxi_pending_sgi(void)
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{
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u32 pending_set;
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pending_set = readl_relaxed(distbase + GIC_DIST_PENDING_SET);
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if (pending_set & SGI_MASK) {
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return true;
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}
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return false;
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}
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extern atomic_t sunxi_user_idle_driver;
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extern raw_spinlock_t sunxi_cpu_idle_c1_lock;
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extern struct cpumask sunxi_cpu_idle_mask;
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extern struct cpumask sunxi_cpu_try_enter_idle_mask;
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extern void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
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/*raise software interrupt*/
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static inline void sunxi_raise_softirq(const struct cpumask *mask, unsigned int irq)
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{
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int cpu;
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unsigned long flag;
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struct cpumask tmp_cores;
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sync_cache_r(&sunxi_user_idle_driver);
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if (atomic_read(&sunxi_user_idle_driver) == 0x00) {
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gic_raise_softirq(mask, irq);
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} else {
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/* send interupt first */
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gic_raise_softirq(mask, irq);
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/* wait every core exit temp state, except myself */
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cpu = get_logical_index(read_cpuid_mpidr()&0xFFFF);
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do {
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cpumask_and(&tmp_cores, mask, &sunxi_cpu_try_enter_idle_mask);
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cpumask_clear_cpu(cpu, &tmp_cores);
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} while (!cpumask_empty(&tmp_cores));
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/* check if need enable some core */
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cpumask_and(&tmp_cores, mask, &sunxi_cpu_idle_mask);
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if (!cpumask_empty(&tmp_cores)) {
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raw_spin_lock_irqsave(&sunxi_cpu_idle_c1_lock, flag);
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for_each_cpu(cpu, mask) {
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if (cpumask_test_cpu(cpu, &sunxi_cpu_idle_mask)) {
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sunxi_cpuidle_power_up_cpu(cpu);
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/* clear cpu idle mask, because the cpu has been enable */
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cpumask_clear_cpu(cpu, &sunxi_cpu_idle_mask);
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}
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}
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raw_spin_unlock_irqrestore(&sunxi_cpu_idle_c1_lock, flag);
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}
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}
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}
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#endif
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