429 lines
15 KiB
C
429 lines
15 KiB
C
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <linux/cdev.h>
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#include <linux/device.h>
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#include <linux/fs.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/sysfs.h>
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#include <linux/timer.h>
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#include <linux/workqueue.h>
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//#include <linux/stdlib.h>
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#include <linux/stat.h>
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#include <linux/string.h>
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// unsigned char toupad_get_key(void);
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// void tipa_set_vol(unsigned char abs_vol);
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int at_8740_write(unsigned char *pbuf, unsigned int len);
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int at_8740_read(unsigned char *pbuf, unsigned int len);
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void at_8740_wakeup(void);
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static unsigned int map_io_base;
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#define D_IO_BASE map_io_base
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#define D_IO_BASE_PHY (0x01c20800)
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#define D_IO_LEN (0x400)
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#define D_IO_A (0)
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#define D_IO_B (1)
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#define D_IO_C (2)
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#define D_IO_D (3)
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#define D_IO_E (4)
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#define D_IO_F (5)
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#define D_IO_G (6)
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#define D_IO_H (7)
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#define D_IO_I (8)
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#define D_IO_CFG0(x) (D_IO_BASE + (x * 0x24) + 0x00)
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#define D_IO_CFG1(x) (D_IO_BASE + (x * 0x24) + 0x04)
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#define D_IO_CFG2(x) (D_IO_BASE + (x * 0x24) + 0x08)
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#define D_IO_CFG3(x) (D_IO_BASE + (x * 0x24) + 0x0c)
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#define D_IO_DAT(x) (D_IO_BASE + (x * 0x24) + 0x10)
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#define D_IO_DRV0(x) (D_IO_BASE + (x * 0x24) + 0x14)
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#define D_IO_DRV1(x) (D_IO_BASE + (x * 0x24) + 0x18)
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#define D_IO_PUL0(x) (D_IO_BASE + (x * 0x24) + 0x1c)
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#define D_IO_PUL1(x) (D_IO_BASE + (x * 0x24) + 0x20)
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int cx20810_set_mode(int mode, int index);
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typedef struct {
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unsigned int opcode;
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unsigned int param[3];
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} t_data_unit;
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enum {
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eDU_RESVER = 0,
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eDU_IVW_PRESET_TIME,
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eDU_REC_TYPE,
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eDU_IVW_POS_INFO,
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eDU_MAX
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};
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t_data_unit database[eDU_MAX];
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static int major_num;
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static struct class *p_class;
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static struct device *p_fpga;
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static struct device *p_reg_debug;
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static struct device *p_dsp_settings;
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static struct device *p_au;
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static struct device *p_tk;
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static struct device *p_vol;
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static struct device *p_vol2;
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static struct device *p_8740;
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static struct device *p_8740_wakeup;
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static unsigned int param_config;
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static struct kset *kset_vendor;
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static struct kobject kobj_pa;
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static ssize_t gen_attr_show(struct kobject *kobj, struct attribute *attr,
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char *buf) {
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strcpy(buf, "wocao");
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return strlen(buf);
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}
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static ssize_t gen_attr_store(struct kobject *kobj, struct attribute *attr,
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const char *buf, size_t count) {
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int i = simple_strtol(buf, (char **)(buf + strlen(buf) - 1), 0);
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printk("vol=%ddb", i);
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// tipa_set_vol(2 * (24-i));
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return count;
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}
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struct attribute gen_vol_set = {
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.name = "vol_set",
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.mode = S_IRWXUGO,
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};
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struct attribute *gen_attr_group[] = {
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&gen_vol_set,
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NULL,
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};
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static const struct sysfs_ops gen_ops = {
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.show = gen_attr_show,
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.store = gen_attr_store,
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};
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static void gen_release(struct kobject *k) {
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// nothing to do
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}
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static struct kobj_type gen_ktype = {
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.sysfs_ops = &gen_ops,
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.default_attrs = gen_attr_group,
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.release = gen_release,
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};
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static int gp_open(struct inode *pnode, struct file *pfile) {
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int major = MAJOR(pnode->i_rdev);
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int minor = MINOR(pnode->i_rdev);
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if (minor == 0) {
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pfile->private_data = (void *)p_fpga;
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} else if (minor == 1) {
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pfile->private_data = (void *)p_reg_debug;
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} else if (minor == 2) {
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pfile->private_data = (void *)p_dsp_settings;
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} else if (minor == 3) {
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pfile->private_data = (void *)p_au;
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} else if (minor == 4) {
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pfile->private_data = (void *)p_tk;
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} else if (minor == 5) {
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pfile->private_data = (void *)p_vol;
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}
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// else if(minor == 6)
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// {
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// pfile->private_data = (void*)p_8740;
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// }
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// else if(minor == 7)
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// {
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// pfile->private_data = (void*)p_8740_wakeup;
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// }
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else {
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pfile->private_data = NULL;
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}
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return 0;
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}
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static int gp_close(struct inode *pnode, struct file *pfile) { return 0; }
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static ssize_t gp_read(struct file *pfile, char __user *puser, size_t len,
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loff_t *poff) {
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if (pfile->private_data == p_fpga) {
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return 0;
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} else if (pfile->private_data == p_reg_debug) {
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unsigned int base_addr = (unsigned int)ioremap(0x1C22400, 0x100);
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unsigned int i;
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for (i = 0; i <= 0x3C; i += 4) {
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printk("[i2s1] addr:0x%x val:0x%x\r\n", base_addr + i,
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*((unsigned int *)(base_addr + i)));
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}
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return len;
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} else if (pfile->private_data == p_au) {
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t_data_unit tmp_data;
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copy_from_user((void *)&tmp_data, puser, len);
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if (tmp_data.opcode < eDU_MAX) {
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copy_to_user(puser, &database[tmp_data.opcode],
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sizeof(t_data_unit));
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return len;
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} else {
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return 0;
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}
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}
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// else if(pfile->private_data == p_tk)
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// {
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// unsigned char tmp = toupad_get_key();
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// copy_to_user(puser, &tmp, sizeof(unsigned char));
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// return len;
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// }
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// else if(pfile->private_data == p_8740)
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// {
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// unsigned char * pbuf;
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// pbuf = kmalloc(len, GFP_KERNEL);
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// printk("8740 nread:%d\r\n", at_8740_read(pbuf, len));
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// copy_to_user(puser, pbuf, len);
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// kfree(pbuf);
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// return len;
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// }
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// else if(pfile->private_data == p_8740_wakeup)
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// {
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// return len;
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// }
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return 0;
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}
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enum {
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CX20810_NORMAL_MODE = 0,
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CX20810_NORMAL_MODE_SIMPLE,
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CX20810_NIRMAL_MODE_CODEC3,
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CX20810_NIRMAL_MODE_CODEC3_SIMPLE,
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CX20810_96K_16BIT_MODE,
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CX20810_48K_16BIT_MODE,
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};
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static ssize_t gp_write(struct file *pfile, const char __user *puser,
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size_t len, loff_t *poff) {
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if (pfile->private_data == p_fpga) {
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copy_from_user((void *)¶m_config, puser, len);
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switch (param_config) {
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case 0:
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printk("fpga_config:mode0\r\n");
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// cx20810_set_mode(CX20810_NORMAL_MODE, 0);
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// cx20810_set_mode(CX20810_NORMAL_MODE, 1);
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// cx20810_set_mode(CX20810_NORMAL_MODE, 2);
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// writel((readl(D_IO_CFG0(D_IO_D)) & ~0x7000000) |
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// 0x1000000, D_IO_CFG0(D_IO_D));
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// writel((readl(D_IO_DAT(D_IO_D)) & ~(1 << 6)),
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// D_IO_DAT(D_IO_D));
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// writel((readl(D_IO_CFG0(D_IO_D)) & ~0x7000) |
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// 0x1000, D_IO_CFG0(D_IO_D));
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// writel((readl(D_IO_DAT(D_IO_D)) & ~(1 << 3)),
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// D_IO_DAT(D_IO_D));
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// writel((readl(D_IO_CFG0(D_IO_D)) & ~0x70000) |
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// 0x10000, D_IO_CFG0(D_IO_D));
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// writel((readl(D_IO_DAT(D_IO_D)) & ~(1 << 4)),
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// D_IO_DAT(D_IO_D));
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writel((readl(D_IO_CFG0(D_IO_E)) & ~0x70000) | 0x10000,
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D_IO_CFG0(D_IO_E));
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writel((readl(D_IO_DAT(D_IO_E)) & ~(1 << 4)), D_IO_DAT(D_IO_E));
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writel((readl(D_IO_CFG0(D_IO_H)) & ~0x70000000) | 0x10000000,
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D_IO_CFG0(D_IO_H));
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writel((readl(D_IO_DAT(D_IO_H)) & ~(1 << 7)), D_IO_DAT(D_IO_H));
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writel((readl(D_IO_CFG0(D_IO_E)) & ~0x7000) | 0x1000,
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D_IO_CFG0(D_IO_E));
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writel((readl(D_IO_DAT(D_IO_E)) & ~(1 << 3)), D_IO_DAT(D_IO_E));
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break;
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case 1:
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printk("fpga_config:mode1\r\n");
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cx20810_set_mode(CX20810_96K_16BIT_MODE, 1);
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// writel((readl(D_IO_CFG0(D_IO_D)) & ~0x7000000) |
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// 0x1000000, D_IO_CFG0(D_IO_D));
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// writel((readl(D_IO_DAT(D_IO_D)) & ~(1 << 6)),
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// D_IO_DAT(D_IO_D));
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// writel((readl(D_IO_CFG0(D_IO_D)) & ~0x7000) |
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// 0x1000, D_IO_CFG0(D_IO_D));
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// writel((readl(D_IO_DAT(D_IO_D)) | (1 << 3)),
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// D_IO_DAT(D_IO_D));
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// writel((readl(D_IO_CFG0(D_IO_D)) & ~0x70000) |
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// 0x10000, D_IO_CFG0(D_IO_D));
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// writel((readl(D_IO_DAT(D_IO_D)) & ~(1 << 4)),
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// D_IO_DAT(D_IO_D));
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writel((readl(D_IO_CFG0(D_IO_E)) & ~0x70000) | 0x10000,
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D_IO_CFG0(D_IO_E));
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writel((readl(D_IO_DAT(D_IO_E)) & ~(1 << 4)), D_IO_DAT(D_IO_E));
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writel((readl(D_IO_CFG0(D_IO_H)) & ~0x70000000) | 0x10000000,
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D_IO_CFG0(D_IO_H));
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writel((readl(D_IO_DAT(D_IO_H)) & ~(1 << 7)), D_IO_DAT(D_IO_H));
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writel((readl(D_IO_CFG0(D_IO_E)) & ~0x7000) | 0x1000,
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D_IO_CFG0(D_IO_E));
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writel((readl(D_IO_DAT(D_IO_E)) | (1 << 3)), D_IO_DAT(D_IO_E));
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break;
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case 2:
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printk("fpga_config:mode2\r\n");
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cx20810_set_mode(CX20810_48K_16BIT_MODE, 0);
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// writel((readl(D_IO_CFG0(D_IO_D)) & ~0x7000000) |
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// 0x1000000, D_IO_CFG0(D_IO_D));
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// writel((readl(D_IO_DAT(D_IO_D)) & ~(1 << 6)),
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// D_IO_DAT(D_IO_D));
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// writel((readl(D_IO_CFG0(D_IO_D)) & ~0x7000) |
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// 0x1000, D_IO_CFG0(D_IO_D));
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// writel((readl(D_IO_DAT(D_IO_D)) & ~(1 << 3)),
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// D_IO_DAT(D_IO_D));
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// writel((readl(D_IO_CFG0(D_IO_D)) & ~0x70000) |
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// 0x10000, D_IO_CFG0(D_IO_D));
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// writel((readl(D_IO_DAT(D_IO_D)) | (1 << 4)),
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// D_IO_DAT(D_IO_D));
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writel((readl(D_IO_CFG0(D_IO_E)) & ~0x70000) | 0x10000,
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D_IO_CFG0(D_IO_E));
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writel((readl(D_IO_DAT(D_IO_E)) & ~(1 << 4)), D_IO_DAT(D_IO_E));
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writel((readl(D_IO_CFG0(D_IO_H)) & ~0x70000000) | 0x10000000,
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D_IO_CFG0(D_IO_H));
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writel((readl(D_IO_DAT(D_IO_H)) | (1 << 7)), D_IO_DAT(D_IO_H));
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writel((readl(D_IO_CFG0(D_IO_E)) & ~0x7000) | 0x1000,
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D_IO_CFG0(D_IO_E));
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writel((readl(D_IO_DAT(D_IO_E)) & ~(1 << 3)), D_IO_DAT(D_IO_E));
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break;
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default:
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break;
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}
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return len;
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} else if (pfile->private_data == p_reg_debug) {
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return len;
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} else if (pfile->private_data == p_dsp_settings) {
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return len;
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} else if (pfile->private_data == p_au) {
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t_data_unit tmp_data;
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copy_from_user((void *)&tmp_data, puser, len);
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if (tmp_data.opcode < eDU_MAX) {
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memcpy(&database[tmp_data.opcode], &tmp_data, sizeof(t_data_unit));
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return len;
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} else {
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return 0;
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}
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} else if (pfile->private_data == p_vol) {
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unsigned char tmp;
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copy_from_user((void *)&tmp, puser, len);
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// tipa_set_vol(tmp);
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return len;
|
||
|
|
}
|
||
|
|
// else if(pfile->private_data == p_8740)
|
||
|
|
// {
|
||
|
|
// unsigned char * pbuf;
|
||
|
|
// pbuf = kmalloc(len, GFP_KERNEL);
|
||
|
|
// copy_from_user((void*)pbuf, puser, len);
|
||
|
|
// printk("8740 nwrite:%d\r\n", at_8740_write(pbuf, len));
|
||
|
|
// kfree(pbuf);
|
||
|
|
// return len;
|
||
|
|
// }
|
||
|
|
// else if(pfile->private_data == p_8740_wakeup)
|
||
|
|
// {
|
||
|
|
// printk("8740 wakeup\r\n");
|
||
|
|
// at_8740_wakeup();
|
||
|
|
// return len;
|
||
|
|
// }
|
||
|
|
else {
|
||
|
|
}
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct file_operations gp_fops = {
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
.open = gp_open,
|
||
|
|
.release = gp_close,
|
||
|
|
.read = gp_read,
|
||
|
|
.write = gp_write,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init fpga_config_init(void) {
|
||
|
|
D_IO_BASE = (unsigned int)ioremap(D_IO_BASE_PHY, D_IO_LEN);
|
||
|
|
if (!D_IO_BASE) {
|
||
|
|
printk("[gen_prov] init gpio err\r\n");
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
kset_vendor = kset_create_and_add("vendor", NULL, NULL);
|
||
|
|
kobj_pa.kset = kset_vendor;
|
||
|
|
kobject_init_and_add(&kobj_pa, &gen_ktype, NULL, "pa");
|
||
|
|
|
||
|
|
major_num = register_chrdev(0, "fpga_chr", &gp_fops);
|
||
|
|
if (major_num < 0) {
|
||
|
|
printk("reg_chr_err\n");
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
p_class = class_create(THIS_MODULE, "fpga_class");
|
||
|
|
if (p_class == NULL) {
|
||
|
|
printk("class create err\n");
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
p_fpga =
|
||
|
|
device_create(p_class, NULL, MKDEV(major_num, 0), NULL, "fpga_config");
|
||
|
|
if (p_fpga == NULL) {
|
||
|
|
printk("device_create err:fpga\n");
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
p_reg_debug =
|
||
|
|
device_create(p_class, NULL, MKDEV(major_num, 1), NULL, "reg_debug");
|
||
|
|
if (p_reg_debug == NULL) {
|
||
|
|
printk("device_create err:reg_debug\n");
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
p_dsp_settings =
|
||
|
|
device_create(p_class, NULL, MKDEV(major_num, 2), NULL, "dsp_settings");
|
||
|
|
if (p_dsp_settings == NULL) {
|
||
|
|
printk("device_create err:p_dsp_settings\n");
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
p_au = device_create(p_class, NULL, MKDEV(major_num, 3), NULL, "au_base");
|
||
|
|
if (p_au == NULL) {
|
||
|
|
printk("device_create err:au_base\n");
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
p_tk = device_create(p_class, NULL, MKDEV(major_num, 4), NULL, "touch_key");
|
||
|
|
if (p_tk == NULL) {
|
||
|
|
printk("device_create err:touch_key\n");
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
p_vol = device_create(p_class, NULL, MKDEV(major_num, 5), NULL, "vbox_vol");
|
||
|
|
if (p_vol == NULL) {
|
||
|
|
printk("device_create err:vbox_vol\n");
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
// p_8740 = device_create(p_class, NULL, MKDEV(major_num, 6), NULL,
|
||
|
|
// "atml_sec"); if(p_8740 == NULL)
|
||
|
|
// {
|
||
|
|
// printk("device_create err:p_8740\n");
|
||
|
|
// return 1;
|
||
|
|
// }
|
||
|
|
|
||
|
|
// p_8740_wakeup = device_create(p_class, NULL, MKDEV(major_num, 7),
|
||
|
|
// NULL, "atml_sec_wake"); if(p_8740_wakeup == NULL)
|
||
|
|
// {
|
||
|
|
// printk("device_create err:p_8740\n");
|
||
|
|
// return 1;
|
||
|
|
// }
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
//module_init(fpga_config_init);
|
||
|
|
|
||
|
|
static void __exit fpga_config_exit(void) {}
|
||
|
|
module_exit(fpga_config_exit);
|
||
|
|
|
||
|
|
/* Module information */
|
||
|
|
MODULE_AUTHOR("feitao");
|
||
|
|
MODULE_DESCRIPTION("fpga config");
|
||
|
|
MODULE_LICENSE("GPL");
|
||
|
|
MODULE_ALIAS("platform:fpga");
|