288 lines
7.4 KiB
C
288 lines
7.4 KiB
C
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/*
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*********************************************************************************************************
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* LINUX-KERNEL
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* AllWinner Linux Platform Develop Kits
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* Kernel Module
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*
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* (c) Copyright 2006-2011, kevin.z China
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* All Rights Reserved
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*
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* File : standby_twi.c
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* By : kevin.z
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* Version : v1.0
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* Date : 2011-5-31 15:22
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* Descript:
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* Update : date auther ver notes
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*********************************************************************************************************
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*/
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#include "standby_i.h"
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#define TWI_CHECK_TIMEOUT (0x2ff)
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static __twic_reg_t* TWI_REG_BASE[3] = {
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(__twic_reg_t*)IO_ADDRESS(AW_TWI0_BASE),
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(__twic_reg_t*)IO_ADDRESS(AW_TWI1_BASE),
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(__twic_reg_t*)IO_ADDRESS(AW_TWI2_BASE)
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};
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static __u32 TwiClkRegBak = 0;
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static __u32 TwiCtlRegBak = 0;
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static __twic_reg_t *twi_reg = (__twic_reg_t *)(0);
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/*
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*********************************************************************************************************
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* standby_twi_init
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*
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*Description: init twi transfer.
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*
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*Arguments :
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*
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*Return :
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*
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*********************************************************************************************************
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*/
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__s32 standby_twi_init(int group)
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{
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twi_reg = TWI_REG_BASE[group];
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TwiClkRegBak = twi_reg->reg_clkr;
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TwiCtlRegBak = 0x80&twi_reg->reg_ctl;/* backup INT_EN;no need for BUS_EN(0xc0) */
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//twi_reg->reg_clkr = (2<<3)|3; //100k
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twi_reg->reg_clkr = (5<<3)|0; //400k, M = 5, N=0;
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twi_reg->reg_reset |= 0x1;
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while(twi_reg->reg_reset&0x1);
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return 0;
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}
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/*
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*********************************************************************************************************
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* standby_twi_exit
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*
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*Description: exit twi transfer.
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*
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*Arguments :
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*
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*Return :
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*
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*********************************************************************************************************
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*/
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__s32 standby_twi_exit(void)
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{
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/* softreset twi module */
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twi_reg->reg_reset |= 0x1;
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/* delay */
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//change_runtime_env();
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//delay_ms(10);
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/* restore clock division */
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twi_reg->reg_clkr = TwiClkRegBak;
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/* restore INT_EN */
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twi_reg->reg_ctl |= TwiCtlRegBak;
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return 0;
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}
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/*
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*********************************************************************************************************
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* _standby_twi_stop
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*
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*Description: stop current twi transfer.
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*
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*Arguments :
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*
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*Return :
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*
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*********************************************************************************************************
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*/
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static int _standby_twi_stop(void)
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{
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unsigned int nop_read;
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unsigned int timeout = TWI_CHECK_TIMEOUT;
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twi_reg->reg_ctl = (twi_reg->reg_ctl & 0xc0) | 0x10 | 0x08;/* set stop+clear int flag */
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nop_read = twi_reg->reg_ctl;
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nop_read = nop_read;
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// 1. stop bit is zero.
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while((twi_reg->reg_ctl & 0x10)&&(timeout--));
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if(timeout == 0)
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{
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return -1;
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}
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// 2. twi fsm is idle(0xf8).
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timeout = TWI_CHECK_TIMEOUT;
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while((0xf8 != twi_reg->reg_status)&&(timeout--));
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if(timeout == 0)
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{
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return -1;
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}
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// 3. twi scl & sda must high level.
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timeout = TWI_CHECK_TIMEOUT;
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while((0x3a != twi_reg->reg_lctl)&&(timeout--));
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if(timeout == 0)
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{
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return -1;
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}
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return 0;
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}
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/*
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*********************************************************************************************************
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* twi_byte_rw
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*
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*Description: twi byte read and write.
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*
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*Arguments : op operation read or write;
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* saddr slave address;
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* baddr byte address;
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* data pointer to the data to be read or write;
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*
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*Return : result;
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* = EPDK_OK, byte read or write successed;
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* = EPDK_FAIL, btye read or write failed!
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*********************************************************************************************************
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*/
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__s32 twi_byte_rw(enum twi_op_type_e op, __u8 saddr, __u8 baddr, __u8 *data)
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{
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unsigned char state_tmp;
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unsigned int timeout;
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int ret = -1;
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twi_reg->reg_efr = 0;/* <20><><EFBFBD><D7BC>д<EFBFBD><D0B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>0 */
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state_tmp = twi_reg->reg_status;
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if(state_tmp != 0xf8)
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{
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goto stop_out;
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}
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/* control registser bitmap
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7 6 5 4 3 2 1 0
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INT_EN BUS_EN START STOP INT_FLAG ACK NOT NOT
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*/
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//1.Send Start
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twi_reg->reg_ctl |= 0x20;
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timeout = TWI_CHECK_TIMEOUT;
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while((!(twi_reg->reg_ctl & 0x08))&&(timeout--));
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if(timeout == 0)
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{
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goto stop_out;
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}
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state_tmp = twi_reg->reg_status;
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if(state_tmp != 0x08)
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{
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goto stop_out;
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}
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//2.Send Slave Address
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twi_reg->reg_data = ((saddr<<1)&0xfe) | 0; /* slave address + write */
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twi_reg->reg_ctl &= 0xCF;
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timeout = TWI_CHECK_TIMEOUT;
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while((!(twi_reg->reg_ctl & 0x08))&&(timeout--));
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if(timeout == 0)
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{
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goto stop_out;
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}
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state_tmp = twi_reg->reg_status;
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if(state_tmp != 0x18)
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{
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goto stop_out;
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}
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//3.Send Byte Address
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twi_reg->reg_data = baddr;
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twi_reg->reg_ctl &= 0xCF;
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timeout = TWI_CHECK_TIMEOUT;
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while((!(twi_reg->reg_ctl & 0x08))&&(timeout--));
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if(timeout == 0)
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{
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goto stop_out;
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}
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state_tmp = twi_reg->reg_status;
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if(state_tmp != 0x28)
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{
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goto stop_out;
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}
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if(op == TWI_OP_WR)
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{
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//4.Send Data to be write
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twi_reg->reg_data = *data;
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twi_reg->reg_ctl &= 0xCF;
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timeout = TWI_CHECK_TIMEOUT;
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while((!(twi_reg->reg_ctl & 0x08))&&(timeout--));
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if(timeout == 0)
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{
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goto stop_out;
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}
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state_tmp = twi_reg->reg_status;
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if(state_tmp != 0x28)
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{
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goto stop_out;
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}
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}
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else
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{
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//4. Send restart for read
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twi_reg->reg_ctl = (twi_reg->reg_ctl & 0xc0) | 0x20 | 0x08; /* set start+clear int flag */
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timeout = TWI_CHECK_TIMEOUT;
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while((!(twi_reg->reg_ctl & 0x08))&&(timeout--));
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if(timeout == 0)
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{
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goto stop_out;
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}
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state_tmp = twi_reg->reg_status;
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if(state_tmp != 0x10)
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{
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goto stop_out;
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}
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//5.Send Slave Address
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twi_reg->reg_data = (saddr<<1) | 1;/* slave address+ read */
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twi_reg->reg_ctl &= 0xCF; /* clear int flag then 0x40 come in */
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timeout = TWI_CHECK_TIMEOUT;
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while((!(twi_reg->reg_ctl & 0x08))&&(timeout--));
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if(timeout == 0)
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{
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goto stop_out;
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}
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state_tmp = twi_reg->reg_status;
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if(state_tmp != 0x40)
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{
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goto stop_out;
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}
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//6.Get data
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twi_reg->reg_ctl &= 0xCF; /* clear int flag then data come in */
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timeout = TWI_CHECK_TIMEOUT;
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while((!(twi_reg->reg_ctl & 0x08))&&(timeout--));
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if(timeout == 0)
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{
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goto stop_out;
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}
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*data = twi_reg->reg_data;
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state_tmp = twi_reg->reg_status;
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if(state_tmp != 0x58)
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{
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goto stop_out;
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}
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}
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ret = 0;
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stop_out:
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//WRITE: step 5; READ: step 7
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//Send Stop
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_standby_twi_stop();
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return ret;
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}
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