281 lines
9.4 KiB
C
281 lines
9.4 KiB
C
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/*
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* hardware interfaces for XRadio drivers
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*
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* Copyright (c) 2013
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* Xradio Technology Co., Ltd. <www.xradiotech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef XRADIO_HWIO_H_INCLUDED
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#define XRADIO_HWIO_H_INCLUDED
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/* extern */ struct xradio_common;
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/* DPLL initial values */
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#define DPLL_INIT_VAL_XRADIO (0x0EC4F121)
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/* Hardware Type Definitions */
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#define HIF_HW_TYPE_XRADIO (1)
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#define CHECK_ADDR_LEN 1
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#define NEW_VERSION 1
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/* Sdio addr is 4*spi_addr */
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#define SPI_REG_ADDR_TO_SDIO(spi_reg_addr) ((spi_reg_addr) << 2)
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#define SDIO_ADDR17BIT(buf_id, mpf, rfu, reg_id_ofs) \
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((((buf_id) & 0x1F) << 7) \
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| (((mpf) & 1) << 6) \
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| (((rfu) & 1) << 5) \
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| (((reg_id_ofs) & 0x1F) << 0))
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#define MAX_RETRY 3
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/* boot loader start address in SRAM */
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#define DOWNLOAD_BOOT_LOADER_OFFSET (0x00000000)
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/* 32K, 0x4000 to 0xDFFF */
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#define DOWNLOAD_FIFO_OFFSET (0x00004000)
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/* 32K */
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#define DOWNLOAD_FIFO_SIZE (0x00008000)
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/* 128 bytes, 0xFF80 to 0xFFFF */
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#define DOWNLOAD_CTRL_OFFSET (0x0000FF80)
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#define DOWNLOAD_CTRL_DATA_DWORDS (32-6)
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/* Download control area */
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struct download_cntl_t {
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/* size of whole firmware file (including Cheksum), host init */
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u32 ImageSize;
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/* downloading flags */
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u32 Flags;
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/* No. of bytes put into the download, init & updated by host */
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u32 Put;
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/* last traced program counter, last ARM reg_pc */
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u32 TracePc;
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/* No. of bytes read from the download, host init, device updates */
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u32 Get;
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/* r0, boot losader status, host init to pending, device updates */
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u32 Status;
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/* Extra debug info, r1 to r14 if status=r0=DOWNLOAD_EXCEPTION */
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u32 DebugData[DOWNLOAD_CTRL_DATA_DWORDS];
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};
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#define DOWNLOAD_IMAGE_SIZE_REG \
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(DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, ImageSize))
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#define DOWNLOAD_FLAGS_REG \
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(DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, Flags))
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#define DOWNLOAD_PUT_REG \
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(DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, Put))
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#define DOWNLOAD_TRACE_PC_REG \
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(DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, TracePc))
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#define DOWNLOAD_GET_REG \
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(DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, Get))
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#define DOWNLOAD_STATUS_REG \
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(DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, Status))
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#define DOWNLOAD_DEBUG_DATA_REG \
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(DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, DebugData))
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#define DOWNLOAD_DEBUG_DATA_LEN (108)
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#define DOWNLOAD_BLOCK_SIZE (1024)
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/* For boot loader detection */
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#define DOWNLOAD_ARE_YOU_HERE (0x87654321)
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#define DOWNLOAD_I_AM_HERE (0x12345678)
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/* Download error code */
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#define DOWNLOAD_PENDING (0xFFFFFFFF)
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#define DOWNLOAD_SUCCESS (0)
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#define DOWNLOAD_EXCEPTION (1)
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#define DOWNLOAD_ERR_MEM_1 (2)
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#define DOWNLOAD_ERR_MEM_2 (3)
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#define DOWNLOAD_ERR_SOFTWARE (4)
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#define DOWNLOAD_ERR_FILE_SIZE (5)
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#define DOWNLOAD_ERR_CHECKSUM (6)
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#define DOWNLOAD_ERR_OVERFLOW (7)
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#define DOWNLOAD_ERR_IMAGE (8)
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#define DOWNLOAD_ERR_HOST (9)
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#define DOWNLOAD_ERR_ABORT (10)
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#define SYS_BASE_ADDR_SILICON (0)
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#define AHB_MEMORY_ADDRESS (SYS_BASE_ADDR_SILICON + 0x08000000)
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#define PAC_BASE_ADDRESS_SILICON (SYS_BASE_ADDR_SILICON + 0x09000000)
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#define PAC_BASE_ADDRESS_SILICON (SYS_BASE_ADDR_SILICON + 0x09000000)
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#define PAC_SHARED_MEMORY_SILICON (PAC_BASE_ADDRESS_SILICON)
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#define APB_ADDR(addr) (PAC_SHARED_MEMORY_SILICON + (addr))
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#if (NEW_VERSION)
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#define PWRCTRL_WLAN_ADDRESS (SYS_BASE_ADDR_SILICON + 0x0AC80000)
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#define PWRCTRL_WLAN_START_CFG (PWRCTRL_WLAN_ADDRESS + 0x18)
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#define PWRCTRL_WLAN_COMMON_CFG (PWRCTRL_WLAN_ADDRESS + 0x178)
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#define PWRCTRL_COMMON_REG_DONE (0x1)
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#define PWRCTRL_COMMON_REG_BT (0x4)
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#define PWRCTRL_COMMON_REG_ARBT (0x8)
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#define PWRCTRL_WLAN_DPLL_CTRL (PWRCTRL_WLAN_ADDRESS + 0x154)
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#else
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#define PWRCTRL_WLAN_ADDRESS (SYS_BASE_ADDR_SILICON + 0x0AC80000)
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#define PWRCTRL_WLAN_START_CFG (PWRCTRL_WLAN_ADDRESS + 0x18)
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#define PWRCTRL_WLAN_COMMON_CFG (PWRCTRL_WLAN_ADDRESS + 0x78)
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#define PWRCTRL_COMMON_REG_DONE (0x1)
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#define PWRCTRL_COMMON_REG_BT (0x4)
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#define PWRCTRL_COMMON_REG_ARBT (0x8)
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#define PWRCTRL_WLAN_DPLL_CTRL (PWRCTRL_WLAN_ADDRESS + 0x54)
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#endif
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/* ***************************************************************
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*Device register definitions
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*************************************************************** */
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/* WBF - SPI Register Addresses */
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#define HIF_ADDR_ID_BASE (0x0000)
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/* 16/32 bits */
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#define HIF_CONFIG_REG_ID (0x0000)
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/* 16/32 bits */
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#define HIF_CONTROL_REG_ID (0x0001)
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/* 16 bits, Q mode W/R */
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#define HIF_IN_OUT_QUEUE_REG_ID (0x0002)
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/* 32 bits, AHB bus R/W */
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#define HIF_AHB_DPORT_REG_ID (0x0003)
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/* 16/32 bits */
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#define HIF_SRAM_BASE_ADDR_REG_ID (0x0004)
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/* 32 bits, APB bus R/W */
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#define HIF_SRAM_DPORT_REG_ID (0x0005)
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/* 32 bits, t_settle/general */
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#define HIF_TSET_GEN_R_W_REG_ID (0x0006)
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/* 16 bits, Q mode read, no length */
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#define HIF_FRAME_OUT_REG_ID (0x0007)
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#define HIF_ADDR_ID_MAX (HIF_FRAME_OUT_REG_ID)
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/* WBF - Control register bit set */
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/* next o/p length, bit 11 to 0 */
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#define HIF_CTRL_NEXT_LEN_MASK (0x0FFF)
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#define HIF_CTRL_WUP_BIT (BIT(12))
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#define HIF_CTRL_RDY_BIT (BIT(13))
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#define HIF_CTRL_IRQ_ENABLE (BIT(14))
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#define HIF_CTRL_RDY_ENABLE (BIT(15))
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#define HIF_CTRL_IRQ_RDY_ENABLE (BIT(14)|BIT(15))
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/* SPI Config register bit set */
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#define HIF_CONFIG_FRAME_BIT (BIT(2))
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#define HIF_CONFIG_WORD_MODE_BITS (BIT(3)|BIT(4))
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#define HIF_CONFIG_WORD_MODE_1 (BIT(3))
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#define HIF_CONFIG_WORD_MODE_2 (BIT(4))
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#define HIF_CONFIG_ERROR_0_BIT (BIT(5))
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#define HIF_CONFIG_ERROR_1_BIT (BIT(6))
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#define HIF_CONFIG_ERROR_2_BIT (BIT(7))
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/* TBD: Sure??? */
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#define HIF_CONFIG_CSN_FRAME_BIT (BIT(7))
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#define HIF_CONFIG_ERROR_3_BIT (BIT(8))
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#define HIF_CONFIG_ERROR_4_BIT (BIT(9))
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/* QueueM */
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#define HIF_CONFIG_ACCESS_MODE_BIT (BIT(10))
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/* AHB bus */
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#define HIF_CONFIG_AHB_PFETCH_BIT (BIT(11))
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#define HIF_CONFIG_CPU_CLK_DIS_BIT (BIT(12))
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/* APB bus */
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#define HIF_CONFIG_PFETCH_BIT (BIT(13))
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/* cpu reset */
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#define HIF_CONFIG_CPU_RESET_BIT (BIT(14))
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#define HIF_CONFIG_CLEAR_INT_BIT (BIT(15))
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/* For XRADIO the IRQ Enable and Ready Bits are in CONFIG register */
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#define HIF_CONF_IRQ_RDY_ENABLE (BIT(16)|BIT(17))
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int xradio_data_read(struct xradio_common *hw_priv, void *buf,
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size_t buf_len);
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int xradio_data_write(struct xradio_common *hw_priv, const void *buf,
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size_t buf_len);
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int xradio_reg_read(struct xradio_common *hw_priv, u16 addr, void *buf,
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size_t buf_len);
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int xradio_reg_write(struct xradio_common *hw_priv, u16 addr,
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const void *buf, size_t buf_len);
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int xradio_reg_bit_operate(struct xradio_common *hw_priv, u16 addr, u32 set, u32 clr);
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int xradio_indirect_read(struct xradio_common *hw_priv, u32 addr, void *buf,
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size_t buf_len, u32 prefetch, u16 port_addr);
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int xradio_apb_write(struct xradio_common *hw_priv, u32 addr,
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const void *buf, size_t buf_len);
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int xradio_ahb_write(struct xradio_common *hw_priv, u32 addr,
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const void *buf, size_t buf_len);
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static inline int xradio_reg_read_16(struct xradio_common *hw_priv,
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u16 addr, u16 *val)
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{
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int ret = 0;
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u32 bigVal = 0;
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ret = xradio_reg_read(hw_priv, addr, &bigVal, sizeof(bigVal));
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*val = (u16)bigVal;
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return ret;
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}
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static inline int xradio_reg_write_16(struct xradio_common *hw_priv,
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u16 addr, u16 val)
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{
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u32 bigVal = (u32)val;
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return xradio_reg_write(hw_priv, addr, &bigVal, sizeof(bigVal));
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}
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static inline int xradio_reg_read_32(struct xradio_common *hw_priv,
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u16 addr, u32 *val)
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{
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return xradio_reg_read(hw_priv, addr, val, sizeof(*val));
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}
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static inline int xradio_reg_write_32(struct xradio_common *hw_priv,
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u16 addr, u32 val)
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{
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return xradio_reg_write(hw_priv, addr, &val, sizeof(val));
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}
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static inline int xradio_apb_read(struct xradio_common *hw_priv, u32 addr,
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void *buf, size_t buf_len)
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{
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return xradio_indirect_read(hw_priv, addr, buf, buf_len,
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HIF_CONFIG_PFETCH_BIT,
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HIF_SRAM_DPORT_REG_ID);
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}
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static inline int xradio_ahb_read(struct xradio_common *hw_priv, u32 addr,
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void *buf, size_t buf_len)
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{
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return xradio_indirect_read(hw_priv, addr, buf, buf_len,
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HIF_CONFIG_AHB_PFETCH_BIT,
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HIF_AHB_DPORT_REG_ID);
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}
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static inline int xradio_apb_read_32(struct xradio_common *hw_priv,
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u32 addr, u32 *val)
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{
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return xradio_apb_read(hw_priv, addr, val, sizeof(*val));
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}
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static inline int xradio_apb_write_32(struct xradio_common *hw_priv,
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u32 addr, u32 val)
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{
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return xradio_apb_write(hw_priv, addr, &val, sizeof(val));
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}
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static inline int xradio_ahb_read_32(struct xradio_common *hw_priv,
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u32 addr, u32 *val)
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{
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return xradio_ahb_read(hw_priv, addr, val, sizeof(*val));
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}
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static inline int xradio_ahb_write_32(struct xradio_common *hw_priv,
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u32 addr, u32 val)
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{
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return xradio_ahb_write(hw_priv, addr, &val, sizeof(val));
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}
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static inline u32 xradio_dllctrl_convert(u32 dpll)
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{
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return ((((dpll>>31)&0x1) << 0) | /*config*/
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(((dpll>>29)&0x3) << 1) | /*dither*/
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(((dpll>>12)&0x1) << 3) | /*frac ctrl*/
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(((dpll>>13)&0xffff) << 4) | /*frac*/
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(((dpll>>4)&0xff) << 20)); /*divn*/
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}
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#endif /* XRADIO_HWIO_H_INCLUDED */
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