322 lines
8.0 KiB
C
322 lines
8.0 KiB
C
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/*
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* Hardware I/O implementation for XRadio drivers
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*
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* Copyright (c) 2013
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* Xradio Technology Co., Ltd. <www.xradiotech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include "xradio.h"
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#include "hwio.h"
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#include "sbus.h"
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static int __xradio_read(struct xradio_common *hw_priv, u16 addr,
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void *buf, size_t buf_len, int buf_id)
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{
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u16 addr_sdio;
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u32 sdio_reg_addr_17bit ;
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#if (CHECK_ADDR_LEN)
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/* Check if buffer is aligned to 4 byte boundary */
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if (SYS_WARN(((unsigned long)buf & 3) && (buf_len > 4))) {
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sbus_printk(XRADIO_DBG_ERROR, "%s: buffer is not aligned.\n",
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__func__);
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return -EINVAL;
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}
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#endif
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/* Convert to SDIO Register Address */
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addr_sdio = SPI_REG_ADDR_TO_SDIO(addr);
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sdio_reg_addr_17bit = SDIO_ADDR17BIT(buf_id, 0, 0, addr_sdio);
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SYS_BUG(!hw_priv->sbus_ops);
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return hw_priv->sbus_ops->sbus_data_read(hw_priv->sbus_priv,
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sdio_reg_addr_17bit,
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buf, buf_len);
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}
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static int __xradio_write(struct xradio_common *hw_priv, u16 addr,
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const void *buf, size_t buf_len, int buf_id)
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{
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u16 addr_sdio;
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u32 sdio_reg_addr_17bit ;
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#if (CHECK_ADDR_LEN)
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/* Check if buffer is aligned to 4 byte boundary */
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if (SYS_WARN(((unsigned long)buf & 3) && (buf_len > 4))) {
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sbus_printk(XRADIO_DBG_ERROR, "%s: buffer is not aligned.\n",
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__func__);
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return -EINVAL;
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}
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#endif
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/* Convert to SDIO Register Address */
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addr_sdio = SPI_REG_ADDR_TO_SDIO(addr);
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sdio_reg_addr_17bit = SDIO_ADDR17BIT(buf_id, 0, 0, addr_sdio);
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SYS_BUG(!hw_priv->sbus_ops);
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return hw_priv->sbus_ops->sbus_data_write(hw_priv->sbus_priv,
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sdio_reg_addr_17bit,
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buf, buf_len);
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}
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static inline int __xradio_read_reg32(struct xradio_common *hw_priv,
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u16 addr, u32 *val)
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{
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return __xradio_read(hw_priv, addr, val, sizeof(val), 0);
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}
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static inline int __xradio_write_reg32(struct xradio_common *hw_priv,
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u16 addr, u32 val)
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{
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return __xradio_write(hw_priv, addr, &val, sizeof(val), 0);
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}
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int xradio_reg_read(struct xradio_common *hw_priv, u16 addr,
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void *buf, size_t buf_len)
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{
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int ret;
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SYS_BUG(!hw_priv->sbus_ops);
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hw_priv->sbus_ops->lock(hw_priv->sbus_priv);
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ret = __xradio_read(hw_priv, addr, buf, buf_len, 0);
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hw_priv->sbus_ops->unlock(hw_priv->sbus_priv);
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return ret;
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}
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int xradio_reg_write(struct xradio_common *hw_priv, u16 addr,
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const void *buf, size_t buf_len)
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{
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int ret;
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SYS_BUG(!hw_priv->sbus_ops);
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hw_priv->sbus_ops->lock(hw_priv->sbus_priv);
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ret = __xradio_write(hw_priv, addr, buf, buf_len, 0);
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hw_priv->sbus_ops->unlock(hw_priv->sbus_priv);
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return ret;
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}
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int xradio_reg_bit_operate(struct xradio_common *hw_priv, u16 addr, u32 set, u32 clr)
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{
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int ret;
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u32 val32;
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SYS_BUG(!hw_priv->sbus_ops);
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hw_priv->sbus_ops->lock(hw_priv->sbus_priv);
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ret = __xradio_read_reg32(hw_priv, addr, &val32);
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if (ret < 0 && 1 == addr) { //means control reg read failed
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ret = __xradio_read_reg32(hw_priv, addr, &val32);
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printk(KERN_ERR"[SDIO-DCE] read control reg agian and val is 0x%x\n", val32);
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}
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if (ret < 0) {
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sbus_printk(XRADIO_DBG_ERROR, "%s: Can't read reg.\n", __func__);
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goto out;
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}
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val32 &= ~clr;
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val32 |= set;
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ret = __xradio_write_reg32(hw_priv, addr, val32);
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if (ret < 0) {
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sbus_printk(XRADIO_DBG_ERROR, "%s: Can't write reg.\n", __func__);
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}
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out:
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hw_priv->sbus_ops->unlock(hw_priv->sbus_priv);
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return ret;
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}
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int xradio_data_read(struct xradio_common *hw_priv, void *buf, size_t buf_len)
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{
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int ret, retry = 1;
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SYS_BUG(!hw_priv->sbus_ops);
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hw_priv->sbus_ops->lock(hw_priv->sbus_priv);
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{
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int buf_id_rx = hw_priv->buf_id_rx;
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while (retry <= MAX_RETRY) {
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ret = __xradio_read(hw_priv, HIF_IN_OUT_QUEUE_REG_ID, buf,
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buf_len, buf_id_rx + 1);
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if (!ret) {
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buf_id_rx = (buf_id_rx + 1) & 3;
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hw_priv->buf_id_rx = buf_id_rx;
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break;
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} else {
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retry++;
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mdelay(1);
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sbus_printk(XRADIO_DBG_ERROR, "%s, error :[%d]\n",
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__func__, ret);
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}
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}
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}
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hw_priv->sbus_ops->unlock(hw_priv->sbus_priv);
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return ret;
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}
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int xradio_data_write(struct xradio_common *hw_priv, const void *buf,
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size_t buf_len)
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{
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int ret, retry = 1;
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SYS_BUG(!hw_priv->sbus_ops);
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hw_priv->sbus_ops->lock(hw_priv->sbus_priv);
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{
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int buf_id_tx = hw_priv->buf_id_tx;
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while (retry <= MAX_RETRY) {
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ret = __xradio_write(hw_priv, HIF_IN_OUT_QUEUE_REG_ID, buf,
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buf_len, buf_id_tx);
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if (!ret) {
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buf_id_tx = (buf_id_tx + 1) & 31;
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hw_priv->buf_id_tx = buf_id_tx;
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break;
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} else {
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retry++;
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mdelay(1);
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sbus_printk(XRADIO_DBG_ERROR, "%s,error :[%d]\n",
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__func__, ret);
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}
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}
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}
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hw_priv->sbus_ops->unlock(hw_priv->sbus_priv);
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return ret;
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}
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int xradio_indirect_read(struct xradio_common *hw_priv, u32 addr, void *buf,
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size_t buf_len, u32 prefetch, u16 port_addr)
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{
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u32 val32 = 0;
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int i, ret;
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if ((buf_len / 2) >= 0x1000) {
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sbus_printk(XRADIO_DBG_ERROR,
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"%s: Can't read more than 0xfff words.\n",
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__func__);
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return -EINVAL;
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goto out;
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}
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hw_priv->sbus_ops->lock(hw_priv->sbus_priv);
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/* Write address */
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ret = __xradio_write_reg32(hw_priv, HIF_SRAM_BASE_ADDR_REG_ID, addr);
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if (ret < 0) {
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sbus_printk(XRADIO_DBG_ERROR,
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"%s: Can't write address register.\n", __func__);
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goto out;
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}
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/* Read CONFIG Register Value - We will read 32 bits */
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ret = __xradio_read_reg32(hw_priv, HIF_CONFIG_REG_ID, &val32);
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if (ret < 0) {
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sbus_printk(XRADIO_DBG_ERROR,
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"%s: Can't read config register.\n", __func__);
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goto out;
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}
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/* Set PREFETCH bit */
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ret = __xradio_write_reg32(hw_priv, HIF_CONFIG_REG_ID, val32 | prefetch);
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if (ret < 0) {
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sbus_printk(XRADIO_DBG_ERROR,
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"%s: Can't write prefetch bit.\n", __func__);
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goto out;
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}
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/* Check for PRE-FETCH bit to be cleared */
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for (i = 0; i < 20; i++) {
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ret = __xradio_read_reg32(hw_priv, HIF_CONFIG_REG_ID, &val32);
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if (ret < 0) {
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sbus_printk(XRADIO_DBG_ERROR,
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"%s: Can't check prefetch bit.\n", __func__);
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goto out;
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}
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if (!(val32 & prefetch))
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break;
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mdelay(i);
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}
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if (val32 & prefetch) {
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sbus_printk(XRADIO_DBG_ERROR,
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"%s: Prefetch bit is not cleared.\n", __func__);
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goto out;
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}
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/* Read data port */
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ret = __xradio_read(hw_priv, port_addr, buf, buf_len, 0);
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if (ret < 0) {
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sbus_printk(XRADIO_DBG_ERROR,
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"%s: Can't read data port.\n", __func__);
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goto out;
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}
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out:
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hw_priv->sbus_ops->unlock(hw_priv->sbus_priv);
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return ret;
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}
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int xradio_apb_write(struct xradio_common *hw_priv, u32 addr, const void *buf,
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size_t buf_len)
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{
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int ret;
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if ((buf_len / 2) >= 0x1000) {
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sbus_printk(XRADIO_DBG_ERROR,
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"%s: Can't wrire more than 0xfff words.\n", __func__);
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return -EINVAL;
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}
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hw_priv->sbus_ops->lock(hw_priv->sbus_priv);
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/* Write address */
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ret = __xradio_write_reg32(hw_priv, HIF_SRAM_BASE_ADDR_REG_ID, addr);
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if (ret < 0) {
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sbus_printk(XRADIO_DBG_ERROR,
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"%s: Can't write address register.\n", __func__);
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goto out;
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}
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/* Write data port */
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ret = __xradio_write(hw_priv, HIF_SRAM_DPORT_REG_ID, buf, buf_len, 0);
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if (ret < 0) {
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sbus_printk(XRADIO_DBG_ERROR, "%s: Can't write data port.\n",
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__func__);
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goto out;
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}
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out:
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hw_priv->sbus_ops->unlock(hw_priv->sbus_priv);
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return ret;
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}
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int xradio_ahb_write(struct xradio_common *hw_priv, u32 addr, const void *buf,
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size_t buf_len)
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{
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int ret;
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if ((buf_len / 2) >= 0x1000) {
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sbus_printk(XRADIO_DBG_ERROR,
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"%s: Can't wrire more than 0xfff words.\n",
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__func__);
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return -EINVAL;
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}
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hw_priv->sbus_ops->lock(hw_priv->sbus_priv);
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/* Write address */
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ret = __xradio_write_reg32(hw_priv, HIF_SRAM_BASE_ADDR_REG_ID, addr);
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if (ret < 0) {
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sbus_printk(XRADIO_DBG_ERROR,
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"%s: Can't write address register.\n", __func__);
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goto out;
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}
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/* Write data port */
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ret = __xradio_write(hw_priv, HIF_AHB_DPORT_REG_ID, buf, buf_len, 0);
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if (ret < 0) {
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sbus_printk(XRADIO_DBG_ERROR,
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"%s: Can't write data port.\n", __func__);
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goto out;
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}
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out:
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hw_priv->sbus_ops->unlock(hw_priv->sbus_priv);
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return ret;
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}
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