112 lines
3.5 KiB
C
112 lines
3.5 KiB
C
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/*
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* drivers/char/sunxi-scr/sunxi-scr.h
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*
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* Copyright (C) 2016 Allwinner.
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* fuzhaoke <fuzhaoke@allwinnertech.com>
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*
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* SUNXI SCR Register Definition
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __SUNXI_SCR_H__
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#define __SUNXI_SCR_H__
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#include "smartcard.h"
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#include "sunxi-scr-user.h"
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#define SCR_MODULE_NAME "smartcard"
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/* smart card registers */
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#define SCR_CSR_OFF (0x000)
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#define SCR_INTEN_OFF (0x004)
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#define SCR_INTST_OFF (0x008)
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#define SCR_FCSR_OFF (0x00c)
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#define SCR_FCNT_OFF (0x010)
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#define SCR_RPT_OFF (0x014)
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#define SCR_DIV_OFF (0x018)
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#define SCR_LTIM_OFF (0x01c)
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#define SCR_CTIM_OFF (0x020)
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#define SCR_LCTL_OFF (0x030)
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#define SCR_FSM_OFF (0x03c)
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#define SCR_FIFO_OFF (0x100)
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/* smart card interrupt status */
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#define SCR_INTSTA_DEACT (0x1<<23)
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#define SCR_INTSTA_ACT (0x1<<22)
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#define SCR_INTSTA_INS (0x1<<21)
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#define SCR_INTSTA_REM (0x1<<20)
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#define SCR_INTSTA_ATRDONE (0x1<<19)
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#define SCR_INTSTA_ATRFAIL (0x1<<18)
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#define SCR_INTSTA_CHTO (0x1<<17) /*Character Timout */
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#define SCR_INTSTA_CLOCK (0x1<<16)
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#define SCR_INTSTA_RXPERR (0x1<<12)
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#define SCR_INTSTA_RXDONE (0x1<<11)
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#define SCR_INTSTA_RXFTH (0x1<<10)
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#define SCR_INTSTA_RXFFULL (0x1<<9)
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#define SCR_INTSTA_TXPERR (0x1<<4)
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#define SCR_INTSTA_TXDONE (0x1<<3)
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#define SCR_INTSTA_TXFTH (0x1<<2)
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#define SCR_INTSTA_TXFEMPTY (0x1<<1)
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#define SCR_INTSTA_TXFDONE (0x1<<0)
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#define SCR_BUF_SIZE 256
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#define SCR_FIFO_DEPTH 8 /* just half of hw fifo size */
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#define SCR_RX_TRANSMIT_NOYET 0
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#define SCR_RX_TRANSMIT_TMOUT 1 /* time out */
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enum scr_atr_status {
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SCR_ATR_RESP_INVALID,
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SCR_ATR_RESP_FAIL,
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SCR_ATR_RESP_OK,
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};
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struct sunxi_scr {
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void __iomem *reg_base;
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struct clk *scr_clk;
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struct clk *scr_clk_source;
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struct platform_device *scr_device;
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struct pinctrl *scr_pinctrl;
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struct resource *mem_res;
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uint32_t clk_freq;
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uint32_t irq_no;
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spinlock_t rx_lock;
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int32_t open_cnt; /* support multi_process */
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bool suspended;
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/* smart card register parameters */
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uint32_t inten_bm; /* interrupt enable bit map */
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uint32_t txfifo_thh; /* txfifo threshold */
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uint32_t rxfifo_thh; /* rxfifo threahold */
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uint32_t tx_repeat; /* tx repeat */
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uint32_t rx_repeat; /* rx repeat */
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uint32_t scclk_div; /* scclk divisor */
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uint32_t baud_div; /* baud divisor */
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uint8_t act_time; /* active/deactive time, in scclk cycles */
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uint8_t rst_time; /* reset time, in scclk cycles */
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uint8_t atr_time; /* ATR limit time, in scclk cycles */
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uint32_t guard_time; /* gaurd time, in ETUs */
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uint32_t chlimit_time; /* character limit time, in ETUs */
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/* some necessary flags */
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volatile uint8_t atr_resp;
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volatile uint8_t rx_transmit_status;
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struct scr_card_para card_para;
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struct scr_atr scr_atr_des;
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struct smc_atr_para smc_atr_para;
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struct smc_pps_para smc_pps_para;
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wait_queue_head_t scr_poll;
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struct timer_list poll_timer;
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bool card_in;
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bool card_last;
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};
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#endif
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