481 lines
9.8 KiB
C
481 lines
9.8 KiB
C
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/*
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* ac102.h -- ac102 ALSA Soc Audio driver
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*
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* Version: 1.0
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*
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* Author: panjunwen
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef _AC102_H
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#define _AC102_H
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/*** AC102 Codec Register Define***/
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/*Chip Reset*/
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#define CHIP_AUDIO_RST 0x00
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/*Power Control*/
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#define PWR_CTRL1 0x01
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#define PWR_CTRL2 0x02
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/*System Function Control*/
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#define SYS_FUNC_CTRL 0x03
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/*System Clock Control*/
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#define ADC_CLK_SET 0x04
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#define DAC_CLK_SET 0x05
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#define SYS_CLK_ENA 0x06
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/*I2S Common Control*/
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#define I2S_CTRL 0x07
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#define I2S_BCLK_CTRL 0x08
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#define I2S_LRCK_CTRL1 0x09
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#define I2S_LRCK_CTRL2 0x0A
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#define I2S_FMT_CTRL1 0x0B
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#define I2S_FMT_CTRL2 0x0C
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#define I2S_FMT_CTRL3 0x0D
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#define I2S_SLOT_CTRL 0x0E
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/*I2S TX Control*/
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#define I2S_TX_CTRL 0x0F
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#define I2S_TX_CHMP_CTRL 0x11
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#define I2S_TX_MIX_SRC 0x13
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/*I2S RX Control*/
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#define I2S_RX_CHMP_CTRL 0x16
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#define I2S_RX_MIX_SRC 0x18
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/*ADC Digital Control*/
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#define ADC_DIG_CTRL 0x19
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#define ADC_DVC 0x1A
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/*DAC Digital Control*/
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#define DAC_DIG_CTRL 0x1B
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#define DAC_DVC 0x1C
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#define DAC_MIX_SRC 0x1D
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/*Digital Pad Drive Control*/
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#define DIG_PADDRV_CTRL 0x1F
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/*ADC Analog Control*/
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#define ADC_ANA_CTRL1 0x20
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#define ADC_ANA_CTRL2 0x21
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#define ADC_ANA_CTRL3 0x22
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#define ADC_ANA_CTRL4 0x23
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#define ADC_ANA_CTRL5 0x24
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/*DAC Analog Control*/
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#define DAC_ANA_CTRL1 0x25
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#define DAC_ANA_CTRL2 0x26
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#define DAC_ANA_CTRL3 0x27
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#define DAC_ANA_CTRL4 0x28
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/*ADC AGC Control*/
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#define AGC_STA 0x30
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#define AGC_CTRL 0x31
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#define AGC_DEBT 0x32
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#define AGC_TGLVL 0x33
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#define AGC_MAXG 0x34
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#define AGC_AVGC1 0x35
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#define AGC_AVGC2 0x36
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#define AGC_AVGC3 0x37
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#define AGC_AVGC4 0x38
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#define AGC_DECAYT1 0x39
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#define AGC_DECAYT2 0x3A
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#define AGC_ATTACKT1 0x3B
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#define AGC_ATTACKT2 0x3C
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#define AGC_NTH 0x3D
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#define AGC_NAVGC1 0x3E
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#define AGC_NAVGC2 0x3F
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#define AGC_NAVGC3 0x40
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#define AGC_NAVGC4 0x41
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#define HPF_COEF1 0x42
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#define HPF_COEF2 0x43
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#define HPF_COEF3 0x44
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#define HPF_COEF4 0x45
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#define AGC_OPT 0x46
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/*DAC EQ Control*/
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#define EQ_CTRL 0x4F
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/*EQ Band1 Coef Control*/
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#define EQ1_B0_H 0x50
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#define EQ1_B0_M 0x51
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#define EQ1_B0_L 0x52
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#define EQ1_B1_H 0x53
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#define EQ1_B1_M 0x54
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#define EQ1_B1_L 0x55
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#define EQ1_B2_H 0x56
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#define EQ1_B2_M 0x57
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#define EQ1_B2_L 0x58
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#define EQ1_A1_H 0x59
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#define EQ1_A1_M 0x5A
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#define EQ1_A1_L 0x5B
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#define EQ1_A2_H 0x5C
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#define EQ1_A2_M 0x5D
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#define EQ1_A2_L 0x5E
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/*EQ Band2 Coef Control*/
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#define EQ2_B0_H 0x60
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#define EQ2_B0_M 0x61
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#define EQ2_B0_L 0x62
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#define EQ2_B1_H 0x63
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#define EQ2_B1_M 0x64
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#define EQ2_B1_L 0x65
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#define EQ2_B2_H 0x66
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#define EQ2_B2_M 0x67
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#define EQ2_B2_L 0x68
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#define EQ2_A1_H 0x69
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#define EQ2_A1_M 0x6A
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#define EQ2_A1_L 0x6B
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#define EQ2_A2_H 0x6C
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#define EQ2_A2_M 0x6D
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#define EQ2_A2_L 0x6E
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/*EQ Band3 Coef Control*/
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#define EQ3_B0_H 0x70
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#define EQ3_B0_M 0x71
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#define EQ3_B0_L 0x72
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#define EQ3_B1_H 0x73
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#define EQ3_B1_M 0x74
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#define EQ3_B1_L 0x75
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#define EQ3_B2_H 0x76
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#define EQ3_B2_M 0x77
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#define EQ3_B2_L 0x78
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#define EQ3_A1_H 0x79
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#define EQ3_A1_M 0x7A
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#define EQ3_A1_L 0x7B
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#define EQ3_A2_H 0x7C
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#define EQ3_A2_M 0x7D
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#define EQ3_A2_L 0x7E
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/*** AC102 Codec Register Bit Define***/
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/*PWR_CTRL1*/
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#define MBIAS_VCTRL 0
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#define DLDO_VCTRL 2
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#define ALDO_VCTRL 5
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/*PWR_CTRL2*/
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#define IREF_EN 0
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#define VREF_EN 1
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#define MBIAS_EN 2
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#define DLDO_EN 3
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#define ALDO_EN 4
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#define IREF_CTRL 5
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/*SYS_FUNC_CTRL*/
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#define DAC_ANA_OUT_EN 0
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#define MCLK_AUTO_DET_EN 1
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#define AGC_GEN 2
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#define NO_SW_MODE_STA 3
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#define ADC_REC_FUNC_EN 4
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#define DAC_PLAY_FUNC_EN 5
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#define VREF_SPUP_STA 6
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/*ADC_CLK_SET*/
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#define NADC 0
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/*DAC_CLK_SET*/
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#define NDAC 0
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/*SYS_CLK_ENA*/
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#define ADC_DIG_CLK_EN 0
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#define AGC_HPF_CLK_EN 1
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#define DAC_DIG_CLK_EN 2
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#define EQ_CLK_EN 3
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#define I2S_CLK_EN 4
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#define SYSCLK_EN 5
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/*I2S_CTRL*/
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#define BCLK_IOEN 7
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#define LRCK_IOEN 6
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#define SDO_EN 4
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#define TXEN 2
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#define RXEN 1
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#define GEN 0
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/*I2S_BCLK_CTRL*/
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#define EDGE_TRANSFER 5
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#define BCLK_POLARITY 4
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#define BCLKDIV 0
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/*I2S_LRCK_CTRL1*/
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#define LRCK_POLARITY 4
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#define LRCK_PERIODH 0
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/*I2S_LRCK_CTRL2*/
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#define LRCK_PERIODL 0
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/*I2S_FMT_CTRL1*/
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#define ENCD_SEL 6
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#define MODE_SEL 4
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#define OFFSET 2
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#define TX_SLOT_HIZ 1
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#define TX_STATE 0
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/*I2S_FMT_CTRL2*/
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#define SLOT_WIDTH_SEL 4
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#define SAMPLE_RESOLUTION 0
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/*I2S_FMT_CTRL3*/
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#define TX_MLS 7
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#define SEXT 5
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#define OUT_MUTE 3
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#define LRCK_WIDTH 2
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#define TX_PDM 0
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/*I2S_SLOT_CTRL*/
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#define TX_CHSEL 0
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#define RX_CHSEL 2
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/*I2S_TX_CTRL*/
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#define TX_CHEN 0
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/*I2S_TX_CHMP_CTRL*/
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#define TX_CH1_MAP 0
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#define TX_CH2_MAP 1
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#define TX_CH3_MAP 2
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#define TX_CH4_MAP 3
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/*I2S_TX_MIX_SRC*/
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#define TX_MIXL_RECD_SRC 0
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#define TX_MIXL_PLAY_SRC 1
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#define TX_MIXR_RECD_SRC 2
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#define TX_MIXR_RXM_SRC 3
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#define TX_MIXL_RECD_GAIN 4
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#define TX_MIXL_PLAY_GAIN 5
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#define TX_MIXR_RECD_GAIN 6
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#define TX_MIXR_RXM_GAIN 7
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/*I2S_RX_CHMP_CTRL*/
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#define RX_CH1_MAP 0
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#define RX_CH2_MAP 2
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#define RX_CH3_MAP 4
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#define RX_CH4_MAP 6
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/* I2S_RX_MIX_SRC*/
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#define RX_MIX_RXL_SRC 0
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#define RX_MIX_RXR_SRC 1
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#define RX_MIX_RXL_GAIN 2
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#define RX_MIX_RXR_GAIN 3
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/* ADC_DIG_CTRL*/
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#define ADC_DIG_EN 0
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#define ADOUT_DLY_EN 1
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#define ADOUT_DTS 2
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#define ADC_PTN_SEL 4
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#define DIG_MIC_OSR 6
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#define DIG_MIC_EN 7
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/*DAC_DIG_CTRL*/
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#define DAC_DIG_EN 0
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#define DAC_PTN_SEL 1
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#define DITHER_SGM 3
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#define DVC_ZCD_EN 6
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/*DAC_MIX_SRC*/
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#define DAC_MIX_RXM_SRC 0
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#define DAC_MIX_RECD_SRC 1
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#define DAC_MIX_RXM_GAIN 2
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#define DAC_MIX_RECD_GAIN 3
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/*DIG_PADDRV_CTRL*/
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#define BCLK_DRV 0
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#define LRCK_DRV 2
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#define SDOUT_DRV 4
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/*ADC_ANA_CTRL1*/
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#define ADC_PGA_GEN 0
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#define PGA_CTRL_RCM 1
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#define PGA_GAIN_CTRL 3
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/*ADC_ANA_CTRL2*/
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#define DITHER_LEVEL_CTRL 0
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#define DSM_VREFP_OUTCTRL 3
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#define DSM_VREFP_LPMODE_EN 5
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#define ADC_SEL_OUT_EDGE 6
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#define DSM_DIS 7
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/*ADC_ANA_CTRL3*/
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#define PGA_OI_M_CTRL 0
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#define PGA_OI_NM_CTRL 3
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#define ADC_DEM_DIS 6
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#define ADC_DITHER_EN 7
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/*ADC_ANA_CTRL4*/
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#define PGA_MAMP_IB_SEL 0
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#define PGA_NMAMP_IB_SEL 3
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#define PGA_IN_VCM_CTRL 6
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/*ADC_ANA_CTRL5*/
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#define DSM_OTA_CTRL 0
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#define DSM_COMP_IB_SEL 2
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#define DSM_OTA_IB_SEL 5
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/*DAC_ANA_CTRL1*/
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#define LOMUTE 2
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#define RSWITCH 3
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#define RAMP_EN 4
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#define VRDA_EN 5
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#define DAC_EN 7
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/*DAC_ANA_CTRL2*/
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#define LINE_OUT_AMP_GAIN 0
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#define LINE_OUT_DIF_EN 4
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#define LINE_OUT_EN 5
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/*DAC_ANA_CTRL3*/
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#define BCEN 1
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#define LINEOPBC 2
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#define DACOPBC 5
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/*DAC_ANA_CTRL4*/
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#define LOUT_VOL_ZCD_EN 0
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#define LOUT_AUTO_ATT_EN 1
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#define AUTO_ATT_STEP 2
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#define RAMP_TIME 4
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/*AGC_CTRL*/
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#define AGC_HYS_SET 0
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#define NOISE_DET_EN 2
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#define HPF_EN 3
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#define AGC_EN 4
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#define AGC_NOISE_FLAG 5
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#define AGC_SAT_FLAG 6
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/*AGC_DEBT*/
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#define SIGNAL_DEB_TIME 0
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#define NOISE_DEB_TIME 4
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/*AGC_TGLVL*/
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#define AGC_TGLVL_SET 0
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/*AGC_NTH*/
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#define AGC_NOISE_THRES 0
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/* AGC_OPT*/
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#define AGC_OUT_NOISE_STA 0
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#define AVER_FILT_COEF_SEL 1
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#define AGC_GAIN_HYS_SET 2
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#define ENERGY_DEFAULT_VAL 4
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/*EQ_CTRL*/
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#define EQ_EN 0
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/*** Some Config Value ***/
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/*I2S BCLK POLARITY Control*/
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#define BCLK_NORMAL_DRIVE_N_SAMPLE_P 0
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#define BCLK_INVERT_DRIVE_P_SAMPLE_N 1
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/*I2S LRCK POLARITY Control*/
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#define LRCK_LEFT_LOW_RIGHT_HIGH 0
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#define LRCK_LEFT_HIGH_RIGHT_LOW 1
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/*I2S Format Selection*/
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#define PCM_FORMAT 0
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#define LEFT_JUSTIFIED_FORMAT 1
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#define RIGHT_JUSTIFIED_FORMAT 2
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/*ADC Digital Debug Control*/
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#define ADC_PTN_NORMAL 0
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#define ADC_PTN_0x5A5A5A 1
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#define ADC_PTN_0x123456 2
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#define ADC_PTN_RX_MIX_DATA 3
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/*DAC Digital Debug Control*/
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#define DAC_PTN_NORMAL 0
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#define DAC_PTN_MINUS_6dB_SIN 1
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#define DAC_PTN_MINUS_60dB_SIN 2
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#define DAC_PTN_ZERO 3
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/*ADC PGA GAIN Control*/
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#define ADC_PGA_GAIN_0dB 0
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#define ADC_PGA_GAIN_1dB 1
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#define ADC_PGA_GAIN_2dB 2
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#define ADC_PGA_GAIN_3dB 3
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#define ADC_PGA_GAIN_4dB 4
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#define ADC_PGA_GAIN_5dB 5
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#define ADC_PGA_GAIN_6dB 6
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#define ADC_PGA_GAIN_7dB 7
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#define ADC_PGA_GAIN_8dB 8
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#define ADC_PGA_GAIN_9dB 9
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#define ADC_PGA_GAIN_10dB 10
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#define ADC_PGA_GAIN_11dB 11
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#define ADC_PGA_GAIN_12dB 12
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#define ADC_PGA_GAIN_13dB 13
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#define ADC_PGA_GAIN_14dB 14
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#define ADC_PGA_GAIN_15dB 15
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#define ADC_PGA_GAIN_16dB 16
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#define ADC_PGA_GAIN_17dB 17
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#define ADC_PGA_GAIN_18dB 18
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#define ADC_PGA_GAIN_19dB 19
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#define ADC_PGA_GAIN_20dB 20
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#define ADC_PGA_GAIN_21dB 21
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#define ADC_PGA_GAIN_22dB 22
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#define ADC_PGA_GAIN_23dB 23
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#define ADC_PGA_GAIN_24dB 24
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#define ADC_PGA_GAIN_25dB 25
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#define ADC_PGA_GAIN_26dB 26
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#define ADC_PGA_GAIN_27dB 27
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#define ADC_PGA_GAIN_28dB 28
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||
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#define ADC_PGA_GAIN_29dB 29
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||
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#define ADC_PGA_GAIN_30dB 30
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||
|
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#define ADC_PGA_GAIN_31dB 31
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||
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|
||
|
|
/*DAC LINEOUT GAIN Control*/
|
||
|
|
#define DAC_LINEOUT_GAIN_0dB 0
|
||
|
|
#define DAC_LINEOUT_GAIN_MINUS_3dB 1
|
||
|
|
#define DAC_LINEOUT_GAIN_MINUS_6dB 2
|
||
|
|
#define DAC_LINEOUT_GAIN_MINUS_9dB 3
|
||
|
|
#define DAC_LINEOUT_GAIN_MINUS_12dB 4
|
||
|
|
#define DAC_LINEOUT_GAIN_MINUS_15dB 5
|
||
|
|
#define DAC_LINEOUT_GAIN_MINUS_18dB 6
|
||
|
|
#define DAC_LINEOUT_GAIN_MINUS_21dB 7
|
||
|
|
#define DAC_LINEOUT_GAIN_MINUS_24dB 8
|
||
|
|
#define DAC_LINEOUT_GAIN_MINUS_27dB 9
|
||
|
|
#define DAC_LINEOUT_GAIN_MINUS_30dB 10
|
||
|
|
#define DAC_LINEOUT_GAIN_MINUS_33dB 11
|
||
|
|
#define DAC_LINEOUT_GAIN_MINUS_36dB 12
|
||
|
|
#define DAC_LINEOUT_GAIN_MINUS_39dB 13
|
||
|
|
#define DAC_LINEOUT_GAIN_MINUS_42dB 14
|
||
|
|
#define DAC_LINEOUT_GAIN_MINUS_45dB 15
|
||
|
|
|
||
|
|
/*ADC/DAC CLK DIV*/
|
||
|
|
#define ADC_DAC_CLK_DIV_1 0
|
||
|
|
#define ADC_DAC_CLK_DIV_2 1
|
||
|
|
#define ADC_DAC_CLK_DIV_3 2
|
||
|
|
#define ADC_DAC_CLK_DIV_4 3
|
||
|
|
#define ADC_DAC_CLK_DIV_6 4
|
||
|
|
#define ADC_DAC_CLK_DIV_8 5
|
||
|
|
#define ADC_DAC_CLK_DIV_12 6
|
||
|
|
#define ADC_DAC_CLK_DIV_16 7
|
||
|
|
#define ADC_DAC_CLK_DIV_24 8
|
||
|
|
|
||
|
|
|
||
|
|
#endif
|
||
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