367 lines
8.0 KiB
C
367 lines
8.0 KiB
C
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/*
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* Copyright © 2015-2016, Shuge
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* Author: Sugar <shugeLinux@gmail.com>
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*
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* This file is provided under a dual BSD/GPL license. When using or
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* redistributing this file, you may do so under either license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/errno.h>
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#include <linux/unistd.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/spinlock.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <linux/mfd/acx00-mfd.h>
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#include <linux/sunxi-sid.h>
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#define EXTEPHY_CTRL0 0x0014
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#define EXTEPHY_CTRL1 0x0016
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#define EPHY_CTRL 0x6000
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#define EPHY_SID 0x8004
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atomic_t ephy_en;
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struct ephy_res {
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struct device_driver *plat_drv;
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struct device_driver *phy_drv;
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struct phy_device *phydev;
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struct acx00 *acx;
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};
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static struct ephy_res ephy_priv;
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int ephy_is_enable(void)
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{
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return atomic_read(&ephy_en);
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}
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EXPORT_SYMBOL_GPL(ephy_is_enable);
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/**
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* @name ephy_read_sid
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* @brief read ephy sid from efuse
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* @param[IN] none
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* @param[OUT] p_ephy_cali: ephy calibration value
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* @return return 0 if success,-value if fail
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*/
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static s32 ephy_read_sid(u16 *p_ephy_cali)
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{
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s32 ret = 0;
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u8 buf[6];
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if (!p_ephy_cali) {
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pr_info("%s's pointer type args are NULL!\n", __func__);
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return -1;
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}
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ret = sunxi_efuse_readn(EFUSE_OEM_NAME, buf, 6);
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if (ret != 0) {
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pr_info("sunxi_efuse_readn failed:%d\n", ret);
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return ret;
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}
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*p_ephy_cali = buf[0] + (buf[1] << 8);
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return ret;
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}
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#if 0
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static int ephy_reset(struct phy_device *phydev)
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{
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int bmcr;
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/* Software Reset PHY */
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bmcr = phy_read(phydev, MII_BMCR);
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if (bmcr < 0)
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return bmcr;
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bmcr |= BMCR_RESET;
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bmcr = phy_write(phydev, MII_BMCR, bmcr);
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if (bmcr < 0)
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return bmcr;
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do {
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bmcr = phy_read(phydev, MII_BMCR);
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if (bmcr < 0)
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return bmcr;
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} while (bmcr & BMCR_RESET);
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return 0;
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}
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#endif
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static void disable_intelligent_ieee(struct phy_device *phydev)
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{
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unsigned int value;
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phy_write(phydev, 0x1f, 0x0100); /* switch to page 1 */
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value = phy_read(phydev, 0x17); /* read address 0 0x17 register */
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value &= ~(1 << 3); /* reg 0x17 bit 3, set 0 to disable IEEE */
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phy_write(phydev, 0x17, value);
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phy_write(phydev, 0x1f, 0x0000); /* switch to page 0 */
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}
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static void disable_802_3az_ieee(struct phy_device *phydev)
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{
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unsigned int value;
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phy_write(phydev, 0xd, 0x7);
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phy_write(phydev, 0xe, 0x3c);
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phy_write(phydev, 0xd, 0x1 << 14 | 0x7);
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value = phy_read(phydev, 0xe);
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value &= ~(0x1 << 1);
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phy_write(phydev, 0xd, 0x7);
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phy_write(phydev, 0xe, 0x3c);
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phy_write(phydev, 0xd, 0x1 << 14 | 0x7);
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phy_write(phydev, 0xe, value);
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phy_write(phydev, 0x1f, 0x0200); /* switch to page 2 */
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phy_write(phydev, 0x18, 0x0000);
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}
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static int ephy_config_init(struct phy_device *phydev)
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{
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int value;
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/* Iint ephy */
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phy_write(phydev, 0x1f, 0x0100); /* Switch to Page 1 */
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phy_write(phydev, 0x12, 0x4824); /* Disable APS */
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phy_write(phydev, 0x1f, 0x0200); /* Switch to Page 2 */
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phy_write(phydev, 0x18, 0x0000); /* PHYAFE TRX optimization */
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phy_write(phydev, 0x1f, 0x0600); /* Switch to Page 6 */
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phy_write(phydev, 0x14, 0x708f); /* PHYAFE TX optimization */
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phy_write(phydev, 0x13, 0xF000); /* PHYAFE RX optimization */
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phy_write(phydev, 0x15, 0x1530);
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phy_write(phydev, 0x1f, 0x0800); /* Switch to Page 6 */
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phy_write(phydev, 0x18, 0x00bc); /* PHYAFE TRX optimization */
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#if 0
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/* Disable Auto Power Saving mode */
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phy_write(phydev, 0x1f, 0x0100); /* Switch to Page 1 */
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value = phy_read(phydev, 0x17);
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value &= ~BIT(13);
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phy_write(phydev, 0x17, value);
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#endif
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disable_intelligent_ieee(phydev); /* Disable Intelligent IEEE */
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disable_802_3az_ieee(phydev); /* Disable 802.3az IEEE */
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phy_write(phydev, 0x1f, 0x0000); /* Switch to Page 0 */
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#ifdef CONFIG_MFD_ACX00
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value = acx00_reg_read(ephy_priv.acx, EPHY_CTRL);
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if (phydev->interface == PHY_INTERFACE_MODE_RMII)
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value |= (1 << 11);
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else
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value &= (~(1 << 11));
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acx00_reg_write(ephy_priv.acx, EPHY_CTRL, value | (1 << 11));
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#endif
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#if defined(CONFIG_ARCH_SUN50IW6)
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value = phy_read(phydev, 0x13);
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value |= 1 << 12;
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phy_write(phydev, 0x13, value);
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#endif
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return 0;
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}
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static int ephy_probe(struct phy_device *phydev)
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{
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struct phy_driver *drv;
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if (!phydev)
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return -ENODEV;
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drv = phydev->drv;
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ephy_priv.phy_drv = &drv->mdiodrv.driver;
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ephy_priv.phydev = phydev;
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return 0;
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}
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#if 0
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static int ephy_ack_interrupt(struct phy_device *phydev)
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{
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int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
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if (err < 0)
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return err;
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return 0;
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}
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#endif
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static void sunxi_ephy_enable(struct ephy_res *priv)
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{
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#ifdef CONFIG_MFD_ACX00
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int value;
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#if defined(CONFIG_ARCH_SUN50IW6)
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u16 ephy_cali = 0;
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#endif
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if (!acx00_enable()) {
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msleep(50);
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if (!acx00_enable()) {
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pr_err("acx00 is no enable, and sunxi_ephy_enable is fail\n");
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return;
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}
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}
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value = acx00_reg_read(priv->acx, EXTEPHY_CTRL0);
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value |= 0x03;
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acx00_reg_write(priv->acx, EXTEPHY_CTRL0, value);
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value = acx00_reg_read(priv->acx, EXTEPHY_CTRL1);
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value |= 0x0f;
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acx00_reg_write(priv->acx, EXTEPHY_CTRL1, value);
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acx00_reg_write(priv->acx, EPHY_CTRL, 0x06);
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/*for ephy */
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value = acx00_reg_read(priv->acx, EPHY_CTRL);
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value &= ~(0xf << 12);
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#if defined(CONFIG_ARCH_SUN50IW6)
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ephy_read_sid(&ephy_cali);
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value |= (0x0F & (0x03 + ephy_cali)) << 12;
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#else
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value |= (0x0F & (0x03 + acx00_reg_read(priv->acx, EPHY_SID))) << 12;
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#endif
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acx00_reg_write(priv->acx, EPHY_CTRL, value);
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atomic_set(&ephy_en, 1);
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#endif
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}
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static struct phy_driver ephy_driver = {
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.phy_id = 0x00441400,
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.name = "ephy",
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.phy_id_mask = 0x0ffffff0,
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.features = PHY_BASIC_FEATURES | SUPPORTED_Pause |
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SUPPORTED_Asym_Pause,
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#if 0
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.flags = PHY_HAS_INTERRUPT,
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.ack_interrupt = ephy_ack_interrupt,
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#endif
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.config_init = &ephy_config_init,
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.config_aneg = &genphy_config_aneg,
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.read_status = &genphy_read_status,
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.suspend = genphy_suspend,
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.resume = genphy_resume,
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.probe = ephy_probe,
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};
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static const struct platform_device_id sunxi_ephy_id[] = {
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{ "acx-ephy", 0},
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{ },
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};
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MODULE_DEVICE_TABLE(platform, sunxi_ephy_id);
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static int ephy_plat_probe(struct platform_device *pdev)
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{
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struct acx00 *ax = dev_get_drvdata(pdev->dev.parent);
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if (!ax)
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return -ENODEV;
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ephy_priv.acx = ax;
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platform_set_drvdata(pdev, &ephy_priv);
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ephy_priv.plat_drv = pdev->dev.driver;
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atomic_set(&ephy_en, 0);
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sunxi_ephy_enable(&ephy_priv);
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return 0;
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}
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static int ephy_plat_remove(struct platform_device *pdev)
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{
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return 0;
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}
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static int sunxi_phy_suspend(struct device *dev)
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{
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atomic_set(&ephy_en, 0);
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return 0;
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}
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static int sunxi_phy_resume(struct device *dev)
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{
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sunxi_ephy_enable(&ephy_priv);
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return 0;
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}
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/* Suspend hook structures */
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static const struct dev_pm_ops sunxi_phy_pm_ops = {
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.suspend = sunxi_phy_suspend,
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.resume = sunxi_phy_resume,
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};
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static struct platform_driver ephy_plat_driver = {
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.driver = {
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.name = "acx-ephy",
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.owner = THIS_MODULE,
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.pm = &sunxi_phy_pm_ops,
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},
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.probe = ephy_plat_probe,
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.remove = ephy_plat_remove,
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.id_table = sunxi_ephy_id,
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};
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static int ephy_init(void)
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{
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int ret = 0;
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ret = platform_driver_register(&ephy_plat_driver);
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if (ret)
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return -EINVAL;
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ret = phy_driver_register(&ephy_driver, THIS_MODULE);
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if (ret)
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platform_driver_unregister(&ephy_plat_driver);
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return ret;
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}
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static void ephy_exit(void)
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{
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if (ephy_priv.plat_drv)
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platform_driver_unregister(&ephy_plat_driver);
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phy_driver_unregister(&ephy_driver);
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}
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module_init(ephy_init);
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module_exit(ephy_exit);
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static struct mdio_device_id __maybe_unused ephy_tbl[] = {
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{ 0x00441400, 0x0ffffff0 },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, ephy_tbl);
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MODULE_DESCRIPTION("Allwinner EPHY drivers");
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MODULE_AUTHOR("Sugar <shugeLinux@gmail.com>");
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MODULE_LICENSE("GPL");
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