311 lines
9.3 KiB
C
Executable File
311 lines
9.3 KiB
C
Executable File
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef __ARCH_INTERRUPTS_H__
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#define __ARCH_INTERRUPTS_H__
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#ifndef __KERNEL__
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/** Mask for an interrupt. */
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/* Note: must handle breaking interrupts into high and low words manually. */
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#define INT_MASK_LO(intno) (1 << (intno))
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#define INT_MASK_HI(intno) (1 << ((intno) - 32))
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#ifndef __ASSEMBLER__
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#define INT_MASK(intno) (1ULL << (intno))
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#endif
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#endif
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/** Where a given interrupt executes */
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#define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
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/** Where to store a vector for a given interrupt. */
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#define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
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/** The base address of user-level interrupts. */
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#define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
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/** Additional synthetic interrupt. */
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#define INT_BREAKPOINT (63)
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#define INT_ITLB_MISS 0
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#define INT_MEM_ERROR 1
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#define INT_ILL 2
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#define INT_GPV 3
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#define INT_SN_ACCESS 4
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#define INT_IDN_ACCESS 5
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#define INT_UDN_ACCESS 6
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#define INT_IDN_REFILL 7
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#define INT_UDN_REFILL 8
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#define INT_IDN_COMPLETE 9
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#define INT_UDN_COMPLETE 10
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#define INT_SWINT_3 11
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#define INT_SWINT_2 12
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#define INT_SWINT_1 13
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#define INT_SWINT_0 14
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#define INT_UNALIGN_DATA 15
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#define INT_DTLB_MISS 16
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#define INT_DTLB_ACCESS 17
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#define INT_DMATLB_MISS 18
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#define INT_DMATLB_ACCESS 19
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#define INT_SNITLB_MISS 20
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#define INT_SN_NOTIFY 21
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#define INT_SN_FIREWALL 22
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#define INT_IDN_FIREWALL 23
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#define INT_UDN_FIREWALL 24
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#define INT_TILE_TIMER 25
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#define INT_IDN_TIMER 26
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#define INT_UDN_TIMER 27
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#define INT_DMA_NOTIFY 28
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#define INT_IDN_CA 29
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#define INT_UDN_CA 30
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#define INT_IDN_AVAIL 31
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#define INT_UDN_AVAIL 32
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#define INT_PERF_COUNT 33
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#define INT_INTCTRL_3 34
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#define INT_INTCTRL_2 35
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#define INT_INTCTRL_1 36
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#define INT_INTCTRL_0 37
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#define INT_BOOT_ACCESS 38
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#define INT_WORLD_ACCESS 39
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#define INT_I_ASID 40
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#define INT_D_ASID 41
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#define INT_DMA_ASID 42
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#define INT_SNI_ASID 43
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#define INT_DMA_CPL 44
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#define INT_SN_CPL 45
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#define INT_DOUBLE_FAULT 46
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#define INT_SN_STATIC_ACCESS 47
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#define INT_AUX_PERF_COUNT 48
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#define NUM_INTERRUPTS 49
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#ifndef __ASSEMBLER__
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#define QUEUED_INTERRUPTS ( \
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(1ULL << INT_MEM_ERROR) | \
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(1ULL << INT_DMATLB_MISS) | \
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(1ULL << INT_DMATLB_ACCESS) | \
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(1ULL << INT_SNITLB_MISS) | \
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(1ULL << INT_SN_NOTIFY) | \
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(1ULL << INT_SN_FIREWALL) | \
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(1ULL << INT_IDN_FIREWALL) | \
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(1ULL << INT_UDN_FIREWALL) | \
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(1ULL << INT_TILE_TIMER) | \
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(1ULL << INT_IDN_TIMER) | \
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(1ULL << INT_UDN_TIMER) | \
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(1ULL << INT_DMA_NOTIFY) | \
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(1ULL << INT_IDN_CA) | \
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(1ULL << INT_UDN_CA) | \
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(1ULL << INT_IDN_AVAIL) | \
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(1ULL << INT_UDN_AVAIL) | \
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(1ULL << INT_PERF_COUNT) | \
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(1ULL << INT_INTCTRL_3) | \
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(1ULL << INT_INTCTRL_2) | \
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(1ULL << INT_INTCTRL_1) | \
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(1ULL << INT_INTCTRL_0) | \
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(1ULL << INT_BOOT_ACCESS) | \
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(1ULL << INT_WORLD_ACCESS) | \
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(1ULL << INT_I_ASID) | \
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(1ULL << INT_D_ASID) | \
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(1ULL << INT_DMA_ASID) | \
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(1ULL << INT_SNI_ASID) | \
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(1ULL << INT_DMA_CPL) | \
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(1ULL << INT_SN_CPL) | \
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(1ULL << INT_DOUBLE_FAULT) | \
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(1ULL << INT_AUX_PERF_COUNT) | \
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0)
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#define NONQUEUED_INTERRUPTS ( \
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(1ULL << INT_ITLB_MISS) | \
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(1ULL << INT_ILL) | \
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(1ULL << INT_GPV) | \
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(1ULL << INT_SN_ACCESS) | \
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(1ULL << INT_IDN_ACCESS) | \
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(1ULL << INT_UDN_ACCESS) | \
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(1ULL << INT_IDN_REFILL) | \
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(1ULL << INT_UDN_REFILL) | \
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(1ULL << INT_IDN_COMPLETE) | \
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(1ULL << INT_UDN_COMPLETE) | \
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(1ULL << INT_SWINT_3) | \
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(1ULL << INT_SWINT_2) | \
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(1ULL << INT_SWINT_1) | \
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(1ULL << INT_SWINT_0) | \
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(1ULL << INT_UNALIGN_DATA) | \
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(1ULL << INT_DTLB_MISS) | \
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(1ULL << INT_DTLB_ACCESS) | \
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(1ULL << INT_SN_STATIC_ACCESS) | \
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0)
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#define CRITICAL_MASKED_INTERRUPTS ( \
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(1ULL << INT_MEM_ERROR) | \
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(1ULL << INT_DMATLB_MISS) | \
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(1ULL << INT_DMATLB_ACCESS) | \
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(1ULL << INT_SNITLB_MISS) | \
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(1ULL << INT_SN_NOTIFY) | \
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(1ULL << INT_SN_FIREWALL) | \
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(1ULL << INT_IDN_FIREWALL) | \
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(1ULL << INT_UDN_FIREWALL) | \
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(1ULL << INT_TILE_TIMER) | \
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(1ULL << INT_IDN_TIMER) | \
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(1ULL << INT_UDN_TIMER) | \
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(1ULL << INT_DMA_NOTIFY) | \
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(1ULL << INT_IDN_CA) | \
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(1ULL << INT_UDN_CA) | \
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(1ULL << INT_IDN_AVAIL) | \
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(1ULL << INT_UDN_AVAIL) | \
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(1ULL << INT_PERF_COUNT) | \
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(1ULL << INT_INTCTRL_3) | \
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(1ULL << INT_INTCTRL_2) | \
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(1ULL << INT_INTCTRL_1) | \
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(1ULL << INT_INTCTRL_0) | \
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(1ULL << INT_AUX_PERF_COUNT) | \
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0)
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#define CRITICAL_UNMASKED_INTERRUPTS ( \
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(1ULL << INT_ITLB_MISS) | \
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(1ULL << INT_ILL) | \
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(1ULL << INT_GPV) | \
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(1ULL << INT_SN_ACCESS) | \
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(1ULL << INT_IDN_ACCESS) | \
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(1ULL << INT_UDN_ACCESS) | \
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(1ULL << INT_IDN_REFILL) | \
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(1ULL << INT_UDN_REFILL) | \
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(1ULL << INT_IDN_COMPLETE) | \
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(1ULL << INT_UDN_COMPLETE) | \
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(1ULL << INT_SWINT_3) | \
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(1ULL << INT_SWINT_2) | \
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(1ULL << INT_SWINT_1) | \
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(1ULL << INT_SWINT_0) | \
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(1ULL << INT_UNALIGN_DATA) | \
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(1ULL << INT_DTLB_MISS) | \
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(1ULL << INT_DTLB_ACCESS) | \
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(1ULL << INT_BOOT_ACCESS) | \
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(1ULL << INT_WORLD_ACCESS) | \
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(1ULL << INT_I_ASID) | \
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(1ULL << INT_D_ASID) | \
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(1ULL << INT_DMA_ASID) | \
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(1ULL << INT_SNI_ASID) | \
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(1ULL << INT_DMA_CPL) | \
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(1ULL << INT_SN_CPL) | \
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(1ULL << INT_DOUBLE_FAULT) | \
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(1ULL << INT_SN_STATIC_ACCESS) | \
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0)
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#define MASKABLE_INTERRUPTS ( \
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(1ULL << INT_MEM_ERROR) | \
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(1ULL << INT_IDN_REFILL) | \
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(1ULL << INT_UDN_REFILL) | \
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(1ULL << INT_IDN_COMPLETE) | \
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(1ULL << INT_UDN_COMPLETE) | \
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(1ULL << INT_DMATLB_MISS) | \
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(1ULL << INT_DMATLB_ACCESS) | \
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(1ULL << INT_SNITLB_MISS) | \
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(1ULL << INT_SN_NOTIFY) | \
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(1ULL << INT_SN_FIREWALL) | \
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(1ULL << INT_IDN_FIREWALL) | \
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(1ULL << INT_UDN_FIREWALL) | \
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(1ULL << INT_TILE_TIMER) | \
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(1ULL << INT_IDN_TIMER) | \
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(1ULL << INT_UDN_TIMER) | \
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(1ULL << INT_DMA_NOTIFY) | \
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(1ULL << INT_IDN_CA) | \
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(1ULL << INT_UDN_CA) | \
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(1ULL << INT_IDN_AVAIL) | \
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(1ULL << INT_UDN_AVAIL) | \
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(1ULL << INT_PERF_COUNT) | \
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(1ULL << INT_INTCTRL_3) | \
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(1ULL << INT_INTCTRL_2) | \
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(1ULL << INT_INTCTRL_1) | \
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(1ULL << INT_INTCTRL_0) | \
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(1ULL << INT_AUX_PERF_COUNT) | \
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0)
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#define UNMASKABLE_INTERRUPTS ( \
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(1ULL << INT_ITLB_MISS) | \
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(1ULL << INT_ILL) | \
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(1ULL << INT_GPV) | \
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(1ULL << INT_SN_ACCESS) | \
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(1ULL << INT_IDN_ACCESS) | \
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(1ULL << INT_UDN_ACCESS) | \
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(1ULL << INT_SWINT_3) | \
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(1ULL << INT_SWINT_2) | \
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(1ULL << INT_SWINT_1) | \
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(1ULL << INT_SWINT_0) | \
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(1ULL << INT_UNALIGN_DATA) | \
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(1ULL << INT_DTLB_MISS) | \
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(1ULL << INT_DTLB_ACCESS) | \
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(1ULL << INT_BOOT_ACCESS) | \
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(1ULL << INT_WORLD_ACCESS) | \
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(1ULL << INT_I_ASID) | \
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(1ULL << INT_D_ASID) | \
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(1ULL << INT_DMA_ASID) | \
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(1ULL << INT_SNI_ASID) | \
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(1ULL << INT_DMA_CPL) | \
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(1ULL << INT_SN_CPL) | \
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(1ULL << INT_DOUBLE_FAULT) | \
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(1ULL << INT_SN_STATIC_ACCESS) | \
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0)
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#define SYNC_INTERRUPTS ( \
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(1ULL << INT_ITLB_MISS) | \
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(1ULL << INT_ILL) | \
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(1ULL << INT_GPV) | \
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(1ULL << INT_SN_ACCESS) | \
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(1ULL << INT_IDN_ACCESS) | \
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(1ULL << INT_UDN_ACCESS) | \
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(1ULL << INT_IDN_REFILL) | \
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(1ULL << INT_UDN_REFILL) | \
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(1ULL << INT_IDN_COMPLETE) | \
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(1ULL << INT_UDN_COMPLETE) | \
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(1ULL << INT_SWINT_3) | \
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(1ULL << INT_SWINT_2) | \
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(1ULL << INT_SWINT_1) | \
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(1ULL << INT_SWINT_0) | \
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(1ULL << INT_UNALIGN_DATA) | \
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(1ULL << INT_DTLB_MISS) | \
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(1ULL << INT_DTLB_ACCESS) | \
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(1ULL << INT_SN_STATIC_ACCESS) | \
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0)
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#define NON_SYNC_INTERRUPTS ( \
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(1ULL << INT_MEM_ERROR) | \
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(1ULL << INT_DMATLB_MISS) | \
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(1ULL << INT_DMATLB_ACCESS) | \
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(1ULL << INT_SNITLB_MISS) | \
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(1ULL << INT_SN_NOTIFY) | \
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(1ULL << INT_SN_FIREWALL) | \
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(1ULL << INT_IDN_FIREWALL) | \
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(1ULL << INT_UDN_FIREWALL) | \
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(1ULL << INT_TILE_TIMER) | \
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(1ULL << INT_IDN_TIMER) | \
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(1ULL << INT_UDN_TIMER) | \
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(1ULL << INT_DMA_NOTIFY) | \
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(1ULL << INT_IDN_CA) | \
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(1ULL << INT_UDN_CA) | \
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(1ULL << INT_IDN_AVAIL) | \
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(1ULL << INT_UDN_AVAIL) | \
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(1ULL << INT_PERF_COUNT) | \
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(1ULL << INT_INTCTRL_3) | \
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(1ULL << INT_INTCTRL_2) | \
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(1ULL << INT_INTCTRL_1) | \
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(1ULL << INT_INTCTRL_0) | \
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(1ULL << INT_BOOT_ACCESS) | \
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(1ULL << INT_WORLD_ACCESS) | \
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(1ULL << INT_I_ASID) | \
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(1ULL << INT_D_ASID) | \
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(1ULL << INT_DMA_ASID) | \
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(1ULL << INT_SNI_ASID) | \
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(1ULL << INT_DMA_CPL) | \
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(1ULL << INT_SN_CPL) | \
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(1ULL << INT_DOUBLE_FAULT) | \
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(1ULL << INT_AUX_PERF_COUNT) | \
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0)
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#endif /* !__ASSEMBLER__ */
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#endif /* !__ARCH_INTERRUPTS_H__ */
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