337 lines
9.3 KiB
C
Executable File
337 lines
9.3 KiB
C
Executable File
// SPDX-License-Identifier: GPL-2.0+
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/*
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* DPAA backplane driver for SerDes 28G.
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* Author: Florinel Iordache <florinel.iordache@nxp.com>
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*
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* Copyright 2018 NXP
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include "fsl_backplane.h"
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#define BIN_M1_SEL 0x0000c000
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#define BIN_Long_SEL 0x0000d000
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#define CDR_SEL_MASK 0x0000f000
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#define PRE_COE_SHIFT 16
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#define POST_COE_SHIFT 8
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#define ZERO_COE_SHIFT 24
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#define TECR0_INIT 0x20808000
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#define RESET_REQ_MASK 0x80000000
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#define RECR3_SNP_START_MASK 0x80000000
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#define RECR3_SNP_DONE_MASK 0x40000000
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#define RECR4_SNP_DATA_MASK 0x000003ff
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#define RECR4_SNP_DATA_SHIFT 0
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#define RECR4_EQ_SNPBIN_SIGN_MASK 0x200
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#define RECR3_GAINK2_MASK 0x1f000000
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#define RECR3_GAINK2_SHIFT 24
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/* Required only for 1000BASE KX */
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#define GCR1_REIDL_TH_MASK 0x00700000
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#define GCR1_REIDL_EX_SEL_MASK 0x000c0000
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#define GCR1_REIDL_ET_MAS_MASK 0x04000000
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#define TECR0_AMP_RED_MASK 0x0000003f
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struct per_lane_ctrl_status {
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u32 gcr0; /* 0x.000 - General Control Register 0 */
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u32 resv1; /* 0x.004 - Reserved */
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u32 resv2; /* 0x.008 - Reserved */
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u32 resv3; /* 0x.00C - Reserved */
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u32 resv4; /* 0x.010 - Reserved */
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u32 resv5; /* 0x.014 - Reserved */
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u32 resv6; /* 0x.018 - Reserved */
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u32 resv7; /* 0x.01C - Reserved */
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u32 trstctl; /* 0x.020 - TX Reset Control Register */
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u32 tgcr0; /* 0x.024 - TX General Control Register 0 */
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u32 tgcr1; /* 0x.028 - TX General Control Register 1 */
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u32 tgcr2; /* 0x.02C - TX General Control Register 2 */
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u32 tecr0; /* 0x.030 - Transmit Equalization Control Register 0 */
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u32 tecr1; /* 0x.034 - Transmit Equalization Control Register 1 */
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u32 resv8; /* 0x.038 - Reserved */
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u32 resv9; /* 0x.03C - Reserved */
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u32 rrstctl; /* 0x.040 - RX Reset Control Register */
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u32 rgcr0; /* 0x.044 - RX General Control Register 0 */
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u32 rxgcr1; /* 0x.048 - RX General Control Register 1 */
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u32 resv10; /* 0x.04C - Reserved */
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u32 recr0; /* 0x.050 - RX Equalization Register 0 */
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u32 recr1; /* 0x.054 - RX Equalization Register 1 */
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u32 recr2; /* 0x.058 - RX Equalization Register 2 */
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u32 recr3; /* 0x.05C - RX Equalization Register 3 */
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u32 recr4; /* 0x.060 - RX Equalization Register 4 */
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u32 resv11; /* 0x.064 - Reserved */
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u32 rccr0; /* 0x.068 - RX Calibration Register 0 */
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u32 rccr1; /* 0x.06C - RX Calibration Register 1 */
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u32 rcpcr0; /* 0x.070 - RX Clock Path Register 0 */
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u32 rsccr0; /* 0x.074 - RX Sampler Calibration Control Register 0 */
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u32 rsccr1; /* 0x.078 - RX Sampler Calibration Control Register 1 */
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u32 resv12; /* 0x.07C - Reserved */
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u32 ttlcr0; /* 0x.080 - Transition Tracking Loop Register 0 */
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u32 ttlcr1; /* 0x.084 - Transition Tracking Loop Register 1 */
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u32 ttlcr2; /* 0x.088 - Transition Tracking Loop Register 2 */
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u32 ttlcr3; /* 0x.08C - Transition Tracking Loop Register 3 */
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u32 resv13; /* 0x.090 - Reserved */
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u32 resv14; /* 0x.094 - Reserved */
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u32 resv15; /* 0x.098 - Reserved */
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u32 resv16; /* 0x.09C - Reserved */
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u32 tcsr0; /* 0x.0A0 - Test Control/Status Register 0 */
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u32 tcsr1; /* 0x.0A4 - Test Control/Status Register 1 */
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u32 tcsr2; /* 0x.0A8 - Test Control/Status Register 2 */
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u32 tcsr3; /* 0x.0AC - Test Control/Status Register 3 */
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u32 tcsr4; /* 0x.0B0 - Test Control/Status Register 4 */
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u32 resv17; /* 0x.0B4 - Reserved */
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u32 resv18; /* 0x.0B8 - Reserved */
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u32 resv19; /* 0x.0BC - Reserved */
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u32 rxcb0; /* 0x.0C0 - RX Control Block Register 0 */
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u32 rxcb1; /* 0x.0C4 - RX Control Block Register 1 */
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u32 resv20; /* 0x.0C8 - Reserved */
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u32 resv21; /* 0x.0CC - Reserved */
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u32 rxss0; /* 0x.0D0 - RX Speed Switch Register 0 */
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u32 rxss1; /* 0x.0D4 - RX Speed Switch Register 1 */
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u32 rxss2; /* 0x.0D8 - RX Speed Switch Register 2 */
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u32 resv22; /* 0x.0DC - Reserved */
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u32 txcb0; /* 0x.0E0 - TX Control Block Register 0 */
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u32 txcb1; /* 0x.0E4 - TX Control Block Register 1 */
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u32 resv23; /* 0x.0E8 - Reserved */
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u32 resv24; /* 0x.0EC - Reserved */
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u32 txss0; /* 0x.0F0 - TX Speed Switch Register 0 */
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u32 txss1; /* 0x.0F4 - TX Speed Switch Register 1 */
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u32 txss2; /* 0x.0F8 - TX Speed Switch Register 2 */
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u32 resv25; /* 0x.0FC - Reserved */
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};
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static struct serdes_access srds;
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static u32 get_lane_memmap_size(void)
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{
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return 0x100;
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}
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static void reset_lane(void *reg)
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{
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struct per_lane_ctrl_status *reg_base = reg;
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u32 val;
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unsigned long timeout;
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/* reset Tx lane: send reset request */
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srds.iowrite32(srds.ioread32(®_base->trstctl) | RESET_REQ_MASK,
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®_base->trstctl);
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udelay(1);
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timeout = 10;
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while (timeout--) {
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val = srds.ioread32(®_base->trstctl);
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if (!(val & RESET_REQ_MASK))
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break;
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usleep_range(5, 20);
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}
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/* reset Rx lane: send reset request */
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srds.iowrite32(srds.ioread32(®_base->rrstctl) | RESET_REQ_MASK,
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®_base->rrstctl);
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udelay(1);
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timeout = 10;
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while (timeout--) {
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val = srds.ioread32(®_base->rrstctl);
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if (!(val & RESET_REQ_MASK))
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break;
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usleep_range(5, 20);
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}
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/* wait for a while after reset */
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timeout = jiffies + 10;
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while (time_before(jiffies, timeout)) {
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schedule();
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usleep_range(5, 20);
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}
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}
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static void tune_tecr(void *reg, u32 ratio_preq, u32 ratio_pst1q, u32 adpt_eq, bool reset)
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{
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struct per_lane_ctrl_status *reg_base = reg;
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u32 val;
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if (reset) {
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/* reset lanes */
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reset_lane(reg);
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}
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val = TECR0_INIT |
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ratio_preq << PRE_COE_SHIFT |
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ratio_pst1q << POST_COE_SHIFT;
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srds.iowrite32(val, ®_base->tecr0);
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val = adpt_eq << ZERO_COE_SHIFT;
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srds.iowrite32(val, ®_base->tecr1);
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udelay(1);
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}
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static void lane_set_1gkx(void *reg)
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{
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struct per_lane_ctrl_status *reg_base = reg;
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u32 val;
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/* reset lanes */
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reset_lane(reg);
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/* set gcr1 for 1GKX */
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val = srds.ioread32(®_base->rxgcr1);
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val &= ~(GCR1_REIDL_TH_MASK | GCR1_REIDL_EX_SEL_MASK |
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GCR1_REIDL_ET_MAS_MASK);
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srds.iowrite32(val, ®_base->rxgcr1);
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udelay(1);
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/* set tecr0 for 1GKX */
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val = srds.ioread32(®_base->tecr0);
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val &= ~TECR0_AMP_RED_MASK;
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srds.iowrite32(val, ®_base->tecr0);
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udelay(1);
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}
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static int get_median_gaink2(u32 *reg)
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{
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int gaink2_snap_shot[BIN_SNAPSHOT_NUM];
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u32 rx_eq_snp;
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struct per_lane_ctrl_status *reg_base;
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int timeout;
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int i, j, tmp, pos;
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reg_base = (struct per_lane_ctrl_status *)reg;
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for (i = 0; i < BIN_SNAPSHOT_NUM; i++) {
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/* wait RECR3_SNP_DONE_MASK has cleared */
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timeout = 100;
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while (srds.ioread32(®_base->recr3) &
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RECR3_SNP_DONE_MASK) {
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udelay(1);
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timeout--;
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if (timeout == 0)
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break;
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}
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/* start snap shot */
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srds.iowrite32((srds.ioread32(®_base->recr3) |
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RECR3_SNP_START_MASK),
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®_base->recr3);
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/* wait for SNP done */
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timeout = 100;
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while (!(srds.ioread32(®_base->recr3) &
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RECR3_SNP_DONE_MASK)) {
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udelay(1);
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timeout--;
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if (timeout == 0)
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break;
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}
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/* read and save the snap shot */
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rx_eq_snp = srds.ioread32(®_base->recr3);
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gaink2_snap_shot[i] = (rx_eq_snp & RECR3_GAINK2_MASK) >>
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RECR3_GAINK2_SHIFT;
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/* terminate the snap shot by setting GCR1[REQ_CTL_SNP] */
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srds.iowrite32((srds.ioread32(®_base->recr3) &
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~RECR3_SNP_START_MASK),
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®_base->recr3);
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}
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/* get median of the 5 snap shot */
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for (i = 0; i < BIN_SNAPSHOT_NUM - 1; i++) {
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tmp = gaink2_snap_shot[i];
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pos = i;
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for (j = i + 1; j < BIN_SNAPSHOT_NUM; j++) {
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if (gaink2_snap_shot[j] < tmp) {
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tmp = gaink2_snap_shot[j];
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pos = j;
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}
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}
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gaink2_snap_shot[pos] = gaink2_snap_shot[i];
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gaink2_snap_shot[i] = tmp;
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}
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return gaink2_snap_shot[2];
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}
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static bool is_bin_early(int bin_sel, void *reg)
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{
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bool early = false;
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int bin_snap_shot[BIN_SNAPSHOT_NUM];
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int i, negative_count = 0;
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struct per_lane_ctrl_status *reg_base = reg;
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int timeout;
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for (i = 0; i < BIN_SNAPSHOT_NUM; i++) {
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/* wait RECR3_SNP_DONE_MASK has cleared */
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timeout = 100;
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while ((srds.ioread32(®_base->recr3) & RECR3_SNP_DONE_MASK)) {
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udelay(1);
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timeout--;
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if (timeout == 0)
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break;
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}
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/* set TCSR1[CDR_SEL] to BinM1/BinLong */
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if (bin_sel == BIN_M1) {
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srds.iowrite32((srds.ioread32(®_base->recr4) &
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~CDR_SEL_MASK) | BIN_M1_SEL,
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®_base->recr4);
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} else {
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srds.iowrite32((srds.ioread32(®_base->recr4) &
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~CDR_SEL_MASK) | BIN_Long_SEL,
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®_base->recr4);
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}
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/* start snap shot */
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srds.iowrite32(srds.ioread32(®_base->recr3) | RECR3_SNP_START_MASK,
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®_base->recr3);
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/* wait for SNP done */
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timeout = 100;
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while (!(srds.ioread32(®_base->recr3) & RECR3_SNP_DONE_MASK)) {
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udelay(1);
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timeout--;
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if (timeout == 0)
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break;
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}
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/* read and save the snap shot */
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bin_snap_shot[i] = (srds.ioread32(®_base->recr4) &
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RECR4_SNP_DATA_MASK) >> RECR4_SNP_DATA_SHIFT;
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if (bin_snap_shot[i] & RECR4_EQ_SNPBIN_SIGN_MASK)
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negative_count++;
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/* terminate the snap shot by setting GCR1[REQ_CTL_SNP] */
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srds.iowrite32(srds.ioread32(®_base->recr3) & ~RECR3_SNP_START_MASK,
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®_base->recr3);
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}
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if (((bin_sel == BIN_M1) && (negative_count > BIN_M1_THRESHOLD)) ||
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((bin_sel == BIN_LONG && (negative_count > BIN_LONG_THRESHOLD)))) {
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early = true;
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}
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return early;
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}
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struct serdes_access* setup_serdes_access_28g(void)
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{
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srds.get_lane_memmap_size = get_lane_memmap_size;
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srds.tune_tecr = tune_tecr;
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srds.reset_lane = reset_lane;
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srds.lane_set_1gkx = lane_set_1gkx;
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srds.get_median_gaink2 = get_median_gaink2;
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srds.is_bin_early = is_bin_early;
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return &srds;
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}
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