182 lines
6.1 KiB
C
Executable File
182 lines
6.1 KiB
C
Executable File
/* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of copyright holder nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DPAA2_QDMA_H
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#define __DPAA2_QDMA_H
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#define LONG_FORMAT 1
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#define DPAA2_QDMA_STORE_SIZE 16
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#define NUM_CH 8
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#define QDMA_DMR_OFFSET 0x0
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#define QDMA_DQ_EN (0 << 30)
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#define QDMA_DQ_DIS (1 << 30)
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#define QDMA_DSR_M_OFFSET 0x10004
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struct dpaa2_qdma_sd_d {
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uint32_t rsv:32;
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union {
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struct {
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uint32_t ssd:12; /* souce stride distance */
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uint32_t sss:12; /* souce stride size */
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uint32_t rsv1:8;
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} sdf;
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struct {
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uint32_t dsd:12; /* Destination stride distance */
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uint32_t dss:12; /* Destination stride size */
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uint32_t rsv2:8;
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} ddf;
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} df;
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uint32_t rbpcmd; /* Route-by-port command */
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uint32_t cmd;
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} __attribute__((__packed__));
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/* Source descriptor command read transaction type for RBP=0:
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coherent copy of cacheable memory */
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#define QDMA_SD_CMD_RDTTYPE_COHERENT (0xb << 28)
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/* Destination descriptor command write transaction type for RBP=0:
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coherent copy of cacheable memory */
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#define QDMA_DD_CMD_WRTTYPE_COHERENT (0x6 << 28)
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#define LX2160_QDMA_DD_CMD_WRTTYPE_COHERENT (0xb << 28)
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#define QMAN_FD_FMT_ENABLE (1) /* frame list table enable */
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#define QMAN_FD_BMT_ENABLE (1 << 15) /* bypass memory translation */
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#define QMAN_FD_BMT_DISABLE (0 << 15) /* bypass memory translation */
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#define QMAN_FD_SL_DISABLE (0 << 14) /* short lengthe disabled */
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#define QMAN_FD_SL_ENABLE (1 << 14) /* short lengthe enabled */
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#define QDMA_FINAL_BIT_DISABLE (0 << 31) /* final bit disable */
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#define QDMA_FINAL_BIT_ENABLE (1 << 31) /* final bit enable */
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#define QDMA_FD_SHORT_FORMAT (1 << 11) /* short format */
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#define QDMA_FD_LONG_FORMAT (0 << 11) /* long format */
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#define QDMA_SER_DISABLE (0 << 8) /* no notification */
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#define QDMA_SER_CTX (1 << 8) /* notification by FQD_CTX[fqid] */
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#define QDMA_SER_DEST (2 << 8) /* notification by destination desc */
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#define QDMA_SER_BOTH (3 << 8) /* soruce and dest notification */
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#define QDMA_FD_SPF_ENALBE (1 << 30) /* source prefetch enable */
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#define QMAN_FD_VA_ENABLE (1 << 14) /* Address used is virtual address */
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#define QMAN_FD_VA_DISABLE (0 << 14)/* Address used is a real address */
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#define QMAN_FD_CBMT_ENABLE (1 << 15) /* Flow Context: 49bit physical address */
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#define QMAN_FD_CBMT_DISABLE (0 << 15) /* Flow Context: 64bit virtual address */
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#define QMAN_FD_SC_DISABLE (0 << 27) /* stashing control */
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#define QDMA_FL_FMT_SBF (0x0) /* Single buffer frame */
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#define QDMA_FL_FMT_SGE 0x2 /* Scatter gather frame */
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#define QDMA_FL_BMT_ENABLE (0x1 << 15)/* enable bypass memory translation */
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#define QDMA_FL_BMT_DISABLE 0x0 /* enable bypass memory translation */
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#define QDMA_FL_SL_LONG (0x0 << 2)/* long length */
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#define QDMA_FL_SL_SHORT 0x1 /* short length */
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#define QDMA_FL_F (0x1)/* last frame list bit */
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/*Description of Frame list table structure*/
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struct dpaa2_qdma_chan {
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struct virt_dma_chan vchan;
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struct virt_dma_desc vdesc;
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enum dma_status status;
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struct dpaa2_qdma_engine *qdma;
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struct mutex dpaa2_queue_mutex;
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spinlock_t queue_lock;
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struct dma_pool *fd_pool;
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struct list_head comp_used;
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struct list_head comp_free;
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};
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struct dpaa2_qdma_comp {
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dma_addr_t fd_bus_addr;
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dma_addr_t fl_bus_addr;
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dma_addr_t desc_bus_addr;
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void *fd_virt_addr;
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void *fl_virt_addr;
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void *desc_virt_addr;
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struct dpaa2_qdma_chan *qchan;
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struct virt_dma_desc vdesc;
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struct list_head list;
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};
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struct dpaa2_qdma_engine {
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struct dma_device dma_dev;
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u32 n_chans;
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struct dpaa2_qdma_chan chans[NUM_CH];
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bool qdma_wrtype_fixup;
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struct dpaa2_qdma_priv *priv;
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};
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/*
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* dpaa2_qdma_priv - driver private data
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*/
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struct dpaa2_qdma_priv {
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int dpqdma_id;
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struct iommu_domain *iommu_domain;
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struct dpdmai_attr dpdmai_attr;
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struct device *dev;
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struct fsl_mc_io *mc_io;
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struct fsl_mc_device *dpdmai_dev;
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struct dpdmai_rx_queue_attr rx_queue_attr[DPDMAI_PRIO_NUM];
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struct dpdmai_tx_queue_attr tx_queue_attr[DPDMAI_PRIO_NUM];
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uint8_t num_pairs;
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struct dpaa2_qdma_engine *dpaa2_qdma;
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struct dpaa2_qdma_priv_per_prio *ppriv;
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};
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struct dpaa2_qdma_priv_per_prio {
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int req_fqid;
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int rsp_fqid;
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int prio;
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struct dpaa2_io_store *store;
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struct dpaa2_io_notification_ctx nctx;
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struct dpaa2_qdma_priv *priv;
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};
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static struct soc_device_attribute soc_fixup_tuning[] = {
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{ .family = "QorIQ LX2160A"},
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{ },
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};
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/* FD pool size: one FD + 3 Frame list + 2 source/destination descriptor */
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#define FD_POOL_SIZE (sizeof(struct dpaa2_fd) + \
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sizeof(struct dpaa2_fl_entry) * 3 + \
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sizeof(struct dpaa2_qdma_sd_d) * 2)
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#endif /* __DPAA2_QDMA_H */
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