// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2160ARDB
//
// Copyright 2018 NXP

/dts-v1/;

#include "fsl-lx2160a.dtsi"

/ {
	model = "NXP Layerscape LX2160ARDB";
	compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";

	aliases {
		crypto = &crypto;
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	sb_3v3: regulator-sb3v3 {
		compatible = "regulator-fixed";
		regulator-name = "MC34717-3.3VSB";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&crypto {
	status = "okay";
};

&esdhc0 {
	sd-uhs-sdr104;
	sd-uhs-sdr50;
	sd-uhs-sdr25;
	sd-uhs-sdr12;
	status = "okay";
};

&esdhc1 {
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	bus-width = <8>;
	status = "okay";
};

&i2c0 {
	status = "okay";

	i2c-mux@77 {
		compatible = "nxp,pca9547";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2>;

			power-monitor@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <1000>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			temperature-sensor@4c {
				compatible = "nxp,sa56004";
				reg = <0x4c>;
				vcc-supply = <&sb_3v3>;
			};

			temperature-sensor@4d {
				compatible = "nxp,sa56004";
				reg = <0x4d>;
				vcc-supply = <&sb_3v3>;
			};
		};
	};
};

&i2c4 {
	status = "okay";

	rtc@51 {
		compatible = "nxp,pcf2129";
		reg = <0x51>;
		// IRQ10_B
		interrupts = <0 150 0x4>;
	};
};

&fspi {
	status = "okay";
	nxp,fspi-has-second-chip;
	flash0: mt35xu512aba@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,m25p80";
		m25p,fast-read;
		spi-max-frequency = <50000000>;
		reg = <0>;
		/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
		spi-rx-bus-width = <8>;
		spi-tx-bus-width = <1>;
	};

	flash1: mt35xu512aba@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,m25p80";
		m25p,fast-read;
		spi-max-frequency = <50000000>;
		reg = <1>;
		/* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
		spi-rx-bus-width = <8>;
		spi-tx-bus-width = <1>;
	};
};

&uart0 {
	status = "okay";
};

&uart1 {
	status = "okay";
};

&usb0 {
	status = "okay";
};

&usb1 {
	status = "okay";
};

&emdio1 {
	rgmii_phy1: ethernet-phy@1 {
		/* AR8035 PHY - "compatible" property not strictly needed */
		compatible = "ethernet-phy-id004d.d072";
		reg = <0x1>;
		/* Poll mode - no "interrupts" property defined */
	};
	rgmii_phy2: ethernet-phy@2 {
		/* AR8035 PHY - "compatible" property not strictly needed */
		compatible = "ethernet-phy-id004d.d072";
		reg = <0x2>;
		/* Poll mode - no "interrupts" property defined */
	};
	aquantia_phy1: ethernet-phy@4 {
		/* AQR107 PHY - "compatible" property not strictly needed */
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <0x4>;
		/* Poll mode - no "interrupts" property defined */
	};
	aquantia_phy2: ethernet-phy@5 {
		/* AQR107 PHY - "compatible" property not strictly needed */
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <0x5>;
		/* Poll mode - no "interrupts" property defined */
	};
};

&emdio2 {
	inphi_phy: emdio2_phy@0 {
		compatible = "ethernet-phy-ieee802.3-c45";
		reg = <0x0>;
		interrupts = <0 9 IRQ_TYPE_EDGE_FALLING>,
			<0 10 IRQ_TYPE_EDGE_FALLING>;
	};
};

&dpmac3 {
	phy-handle = <&aquantia_phy1>;
	phy-connection-type = "xgmii";
};

&dpmac4 {
	phy-handle = <&aquantia_phy2>;
	phy-connection-type = "xgmii";
};

&dpmac5 {
	phy-handle = <&inphi_phy>;
};

&dpmac6 {
	phy-handle = <&inphi_phy>;
};

&dpmac17 {
	phy-handle = <&rgmii_phy1>;
	phy-connection-type = "rgmii-id";
};

&dpmac18 {
	phy-handle = <&rgmii_phy2>;
	phy-connection-type = "rgmii-id";
};

&sata0 {
	status = "okay";
};

&sata1 {
	status = "okay";
};

&sata2 {
	status = "okay";
};

&sata3 {
	status = "okay";
};