// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 *
 * Mingkai Hu <mingkai.hu@nxp.com>
 */

/dts-v1/;

#include "hcen1004a-ls1046a.dtsi"

/ {
	model = "LS1046A RDB Board";
	compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";

	aliases {
		serial0 = &duart0;
		serial1 = &duart1;
		serial2 = &duart2;
		serial3 = &duart3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};



&i2c0 {
	status = "okay";

	temp@48 {
		compatible = "ti,tmp101";
		reg = <0x48>;
	};

	rtc@32 {
		compatible = "epson,rx8025";
		reg = <0x32>;
	};

	eeprom@56 {
		compatible = "atmel,24c512";
		reg = <0x52>;
	};

	eeprom@57 {
		compatible = "atmel,24c512";
		reg = <0x53>;
	};
};

&ifc {
	#address-cells = <2>;
	#size-cells = <1>;
	/* NAND Flashe and CPLD on board */
	ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
	status = "okay";

	nand@0,0 {
		compatible = "fsl,ifc-nand";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x0 0x0 0x10000>;
	};

	cpld: board-control@2,0 {
		compatible = "fsl,ls1046ardb-cpld";
		reg = <0x2 0x0 0x0000100>;
	};
};

&qspi {
	num-cs = <2>;
	bus-num = <0>;
	status = "disable";
	fsl,qspi-has-second-chip;

	qflash0: s25fs512s@0 {
		compatible = "spansion,m25p80";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		reg = <0>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
	};

	qflash1: s25fs512s@1 {
		compatible = "spansion,m25p80";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		reg = <1>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
	};
};

#include "fsl-ls1046-post.dtsi"

&fman0 {
	ethernet@e4000 {
		phy-handle = <&rgmii_phy1>;
		phy-connection-type = "rgmii";
	};

	ethernet@e6000 {
		phy-handle = <&rgmii_phy2>;
		phy-connection-type = "rgmii";
	};

	ethernet@e8000 {
		phy-handle = <&sgmii_phy1>;
		phy-connection-type = "sgmii";
	};

	ethernet@ea000 {
		phy-handle = <&sgmii_phy2>;
		phy-connection-type = "sgmii";
	};

	ethernet@f0000 { /* 10GEC1 */
		fixed-link = <0 1 1000 0 0>;
		phy-connection-type = "xgmii";
	};

	ethernet@f2000 { /* 10GEC2 */
		fixed-link = <0 1 1000 0 0>;
		phy-connection-type = "xgmii";
	};

	mdio@fc000 {

		rgmii_phy1: ethernet-phy@1 {
			reg = <0x1>;
		};

		sgmii_phy1: ethernet-phy@17 {
			reg = <0x17>;
		};

		sgmii_phy2: ethernet-phy@14 {
			reg = <0x14>;
		};
	};

	mdio@fd000 {

		rgmii_phy2: ethernet-phy@5 {
			reg = <0x1>;
		};
	};
};