Merge branch 'master' of http://git.komect.net/ISG/secogateway
This commit is contained in:
wuhuanzheng
commit
c1b918b9fb
kernel/linux-4.14.83
.config.gitignorelinux_arm64.its
arch/arm64
KconfigMakefile
config-4.9.140boot/dts
Makefile
freescale
huachentel
Makefilefsl-ls1043-post.dtsifsl-ls1046-post.dtsifsl-ls1046a.dtsifsl-tmu-map1.dtsifsl-tmu-map2.dtsifsl-tmu-map3.dtsifsl-tmu.dtsihc-ls1012a-hcen101.dtshc-ls1043a-hcen1002a-sdk.dtshc-ls1043a-hcen1002a-usdpaa.dtshc-ls1043a-hcen1002a.dtshc-ls1043a-hcen1002b-sdk.dtshc-ls1043a-hcen1002b-usdpaa.dtshc-ls1043a-hcen1002b.dtshc-ls1043a-hcen104-sdk.dtshc-ls1043a-hcen104-usdpaa.dtshc-ls1043a-hcen104.dtshc-ls1046a-hcen1004-sdk.dtshc-ls1046a-hcen1004-usdpaa.dtshc-ls1046a-hcen1004.dtshc-ls1046a-hcen1004a-sdk.dtshc-ls1046a-hcen1004a-usdpaa.dtshc-ls1046a-hcen1004a.dtshcen1002a-ls1043a.dtsihcen1002b-ls1043a.dtsihcen1004-ls1046a.dtsihcen1004a-ls1046a.dtsihcen101-ls1012a.dtsihcen104-ls1043a.dtsiqoriq-bman-portals-sdk.dtsiqoriq-bman-portals.dtsiqoriq-dpaa-eth.dtsiqoriq-fman3-0-10g-0.dtsiqoriq-fman3-0-10g-1.dtsiqoriq-fman3-0-1g-0.dtsiqoriq-fman3-0-1g-1.dtsiqoriq-fman3-0-1g-2.dtsiqoriq-fman3-0-1g-3.dtsiqoriq-fman3-0-1g-4.dtsiqoriq-fman3-0-1g-5.dtsiqoriq-fman3-0-6oh.dtsiqoriq-fman3-0.dtsiqoriq-qman-portals-sdk.dtsiqoriq-qman-portals.dtsi
configs
drivers
KconfigMakefile
crypto/caam
gpu/drm/nouveau/nvkm/subdev/i2c
hctel
i2c/busses
net
spi
staging/fsl_qbman
usb/serial
huachentel
include
linux
net/netfilter
soc/arc
uapi/linux
netfilter
netfilter_ipv4
netfilter_ipv6
net
File diff suppressed because it is too large
Load Diff
|
|
@ -39,7 +39,6 @@
|
|||
*.symtypes
|
||||
*.tar
|
||||
*.xz
|
||||
*.itb
|
||||
Module.symvers
|
||||
modules.builtin
|
||||
|
||||
|
|
@ -77,7 +76,7 @@ modules.builtin
|
|||
!.gitignore
|
||||
!.mailmap
|
||||
!.cocciconfig
|
||||
!.config
|
||||
|
||||
#
|
||||
# Generated include files
|
||||
#
|
||||
|
|
|
|||
|
|
@ -1084,6 +1084,12 @@ config RANDOMIZE_MODULE_REGION_FULL
|
|||
|
||||
endmenu
|
||||
|
||||
menu "huachentel device"
|
||||
|
||||
source "huachentel/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Boot options"
|
||||
|
||||
config ARM64_ACPI_PARKING_PROTOCOL
|
||||
|
|
|
|||
|
|
@ -117,7 +117,7 @@ boot := arch/arm64/boot
|
|||
KBUILD_IMAGE := $(boot)/Image.gz
|
||||
KBUILD_DTBS := dtbs
|
||||
|
||||
all: Image.gz $(KBUILD_DTBS) $(KBUILD_ITB)
|
||||
all: Image.gz $(KBUILD_DTBS)
|
||||
|
||||
|
||||
Image: vmlinux
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@ dts-dirs += sprd
|
|||
dts-dirs += xilinx
|
||||
dts-dirs += lg
|
||||
dts-dirs += zte
|
||||
dts-dirs += huachentel
|
||||
|
||||
subdir-y := $(dts-dirs)
|
||||
|
||||
|
|
|
|||
|
|
@ -25,14 +25,6 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
|
|||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
|
||||
|
||||
# add dtb support for hc-enxxx
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1043a-hcen104.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1043a-hcen104-sdk.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1043a-hcen104-usdpaa.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1043a-hcen1002.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1043a-hcen1002-sdk.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1043a-hcen1002-usdpaa.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
clean-files := *.dtb
|
||||
|
|
|
|||
|
|
@ -17,13 +17,13 @@ thermal_zones: thermal-zones {
|
|||
|
||||
trips {
|
||||
alert0: alert0 {
|
||||
temperature = <85000>;
|
||||
temperature = <75000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
crit0: crit0 {
|
||||
temperature = <105000>;
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
|
|
@ -47,13 +47,13 @@ thermal_zones: thermal-zones {
|
|||
|
||||
trips {
|
||||
alert1: alert1 {
|
||||
temperature = <85000>;
|
||||
temperature = <75000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
crit1: crit1 {
|
||||
temperature = <105000>;
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
|
|
@ -77,13 +77,13 @@ thermal_zones: thermal-zones {
|
|||
|
||||
trips {
|
||||
alert2: alert2 {
|
||||
temperature = <85000>;
|
||||
temperature = <75000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
crit2: crit2 {
|
||||
temperature = <105000>;
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
|
|
@ -107,13 +107,13 @@ thermal_zones: thermal-zones {
|
|||
|
||||
trips {
|
||||
alert3: alert3 {
|
||||
temperature = <85000>;
|
||||
temperature = <75000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
crit3: crit3 {
|
||||
temperature = <105000>;
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
|
|
@ -137,13 +137,13 @@ thermal_zones: thermal-zones {
|
|||
|
||||
trips {
|
||||
alert4: alert4 {
|
||||
temperature = <85000>;
|
||||
temperature = <75000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
crit4: crit4 {
|
||||
temperature = <105000>;
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
|
|
@ -167,13 +167,13 @@ thermal_zones: thermal-zones {
|
|||
|
||||
trips {
|
||||
alert5: alert5 {
|
||||
temperature = <85000>;
|
||||
temperature = <75000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
crit5: crit5 {
|
||||
temperature = <105000>;
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
|
|
@ -197,13 +197,13 @@ thermal_zones: thermal-zones {
|
|||
|
||||
trips {
|
||||
alert6: alert6 {
|
||||
temperature = <85000>;
|
||||
temperature = <75000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
crit6: crit6 {
|
||||
temperature = <105000>;
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
|
|
@ -227,7 +227,7 @@ thermal_zones: thermal-zones {
|
|||
|
||||
trips {
|
||||
alert7: alert7 {
|
||||
temperature = <85000>;
|
||||
temperature = <75000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -0,0 +1,27 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1012a-hcen101.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1043a-hcen104.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1043a-hcen104-sdk.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1043a-hcen104-usdpaa.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1043a-hcen1002a.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1043a-hcen1002a-sdk.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1043a-hcen1002a-usdpaa.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1043a-hcen1002b.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1043a-hcen1002b-sdk.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1043a-hcen1002b-usdpaa.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1046a-hcen1004.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1046a-hcen1004-sdk.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1046a-hcen1004-usdpaa.dtb
|
||||
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1046a-hcen1004a.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1046a-hcen1004a-sdk.dtb
|
||||
dtb-$(CONFIG_ARCH_LAYERSCAPE) += hc-ls1046a-hcen1004a-usdpaa.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
clean-files := *.dtb
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* QorIQ FMan v3 device tree nodes for ls1043
|
||||
*
|
||||
* Copyright 2015-2016 Freescale Semiconductor Inc.
|
||||
*/
|
||||
|
||||
&soc {
|
||||
|
||||
/* include used FMan blocks */
|
||||
#include "qoriq-fman3-0.dtsi"
|
||||
#include "qoriq-fman3-0-1g-0.dtsi"
|
||||
#include "qoriq-fman3-0-1g-1.dtsi"
|
||||
#include "qoriq-fman3-0-1g-2.dtsi"
|
||||
#include "qoriq-fman3-0-1g-3.dtsi"
|
||||
#include "qoriq-fman3-0-1g-4.dtsi"
|
||||
#include "qoriq-fman3-0-1g-5.dtsi"
|
||||
#include "qoriq-fman3-0-10g-0.dtsi"
|
||||
|
||||
};
|
||||
|
||||
&fman0 {
|
||||
/* these aliases provide the FMan ports mapping */
|
||||
enet0: ethernet@e0000 {
|
||||
};
|
||||
|
||||
enet1: ethernet@e2000 {
|
||||
};
|
||||
|
||||
enet2: ethernet@e4000 {
|
||||
};
|
||||
|
||||
enet3: ethernet@e6000 {
|
||||
};
|
||||
|
||||
enet4: ethernet@e8000 {
|
||||
};
|
||||
|
||||
enet5: ethernet@ea000 {
|
||||
};
|
||||
|
||||
enet6: ethernet@f0000 {
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* QorIQ FMan v3 device tree nodes for ls1046
|
||||
*
|
||||
* Copyright 2015-2016 Freescale Semiconductor Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
&soc {
|
||||
|
||||
/* include used FMan blocks */
|
||||
#include "qoriq-fman3-0.dtsi"
|
||||
#include "qoriq-fman3-0-1g-0.dtsi"
|
||||
#include "qoriq-fman3-0-1g-1.dtsi"
|
||||
#include "qoriq-fman3-0-1g-2.dtsi"
|
||||
#include "qoriq-fman3-0-1g-3.dtsi"
|
||||
#include "qoriq-fman3-0-1g-4.dtsi"
|
||||
#include "qoriq-fman3-0-1g-5.dtsi"
|
||||
#include "qoriq-fman3-0-10g-0.dtsi"
|
||||
#include "qoriq-fman3-0-10g-1.dtsi"
|
||||
};
|
||||
|
||||
&fman0 {
|
||||
/* these aliases provide the FMan ports mapping */
|
||||
enet0: ethernet@e0000 {
|
||||
};
|
||||
|
||||
enet1: ethernet@e2000 {
|
||||
};
|
||||
|
||||
enet2: ethernet@e4000 {
|
||||
};
|
||||
|
||||
enet3: ethernet@e6000 {
|
||||
};
|
||||
|
||||
enet4: ethernet@e8000 {
|
||||
};
|
||||
|
||||
enet5: ethernet@ea000 {
|
||||
};
|
||||
|
||||
enet6: ethernet@f0000 {
|
||||
};
|
||||
|
||||
enet7: ethernet@f2000 {
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,789 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
|
||||
*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Mingkai Hu <mingkai.hu@nxp.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
compatible = "fsl,ls1046a";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
crypto = &crypto;
|
||||
fman0 = &fman0;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
ethernet4 = &enet4;
|
||||
ethernet5 = &enet5;
|
||||
ethernet6 = &enet6;
|
||||
ethernet7 = &enet7;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cooling_map0: cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x1>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x2>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x3>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
l2: l2-cache {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
/*
|
||||
* PSCI node is not added default, U-boot will add missing
|
||||
* parts if it determines to use PSCI.
|
||||
*/
|
||||
entry-method = "arm,psci";
|
||||
|
||||
CPU_PH20: cpu-ph20 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "PH20";
|
||||
arm,psci-suspend-param = <0x0>;
|
||||
entry-latency-us = <1000>;
|
||||
exit-latency-us = <1000>;
|
||||
min-residency-us = <3000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
sysclk: sysclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible ="syscon-reboot";
|
||||
regmap = <&dcfg>;
|
||||
offset = <0xb0>;
|
||||
mask = <0x02>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>,
|
||||
<&cpu1>,
|
||||
<&cpu2>,
|
||||
<&cpu3>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1400000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x1410000 0 0x10000>, /* GICD */
|
||||
<0x0 0x1420000 0 0x20000>, /* GICC */
|
||||
<0x0 0x1440000 0 0x20000>, /* GICH */
|
||||
<0x0 0x1460000 0 0x20000>; /* GICV */
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
|
||||
|
||||
ddr: memory-controller@1080000 {
|
||||
compatible = "fsl,qoriq-memory-controller";
|
||||
reg = <0x0 0x1080000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
ifc: ifc@1530000 {
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
reg = <0x0 0x1530000 0x0 0x10000>;
|
||||
big-endian;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
qspi: quadspi@1550000 {
|
||||
compatible = "fsl,ls1021a-qspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x1550000 0x0 0x10000>,
|
||||
<0x0 0x40000000 0x0 0x10000000>;
|
||||
reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "qspi_en", "qspi";
|
||||
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc: esdhc@1560000 {
|
||||
compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
|
||||
reg = <0x0 0x1560000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 2 1>;
|
||||
voltage-ranges = <1800 1800 3300 3300>;
|
||||
sdhci,auto-cmd12;
|
||||
big-endian;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
scfg: scfg@1570000 {
|
||||
compatible = "fsl,ls1046a-scfg", "syscon";
|
||||
reg = <0x0 0x1570000 0x0 0x10000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
crypto: crypto@1700000 {
|
||||
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
|
||||
"fsl,sec-v4.0";
|
||||
fsl,sec-era = <8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x1700000 0x100000>;
|
||||
reg = <0x00 0x1700000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
sec_jr0: jr@10000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x10000 0x10000>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@20000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x20000 0x10000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@30000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@40000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x40000 0x10000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
qman: qman@1880000 {
|
||||
compatible = "fsl,qman";
|
||||
reg = <0x0 0x1880000 0x0 0x10000>;
|
||||
interrupts = <0 45 0x4>;
|
||||
memory-region = <&qman_fqd &qman_pfdr>;
|
||||
|
||||
};
|
||||
|
||||
bman: bman@1890000 {
|
||||
compatible = "fsl,bman";
|
||||
reg = <0x0 0x1890000 0x0 0x10000>;
|
||||
interrupts = <0 45 0x4>;
|
||||
memory-region = <&bman_fbpr>;
|
||||
|
||||
};
|
||||
|
||||
qportals: qman-portals@500000000 {
|
||||
ranges = <0x0 0x5 0x00000000 0x8000000>;
|
||||
};
|
||||
|
||||
bportals: bman-portals@508000000 {
|
||||
ranges = <0x0 0x5 0x08000000 0x8000000>;
|
||||
};
|
||||
|
||||
dcfg: dcfg@1ee0000 {
|
||||
compatible = "fsl,ls1046a-dcfg", "syscon";
|
||||
reg = <0x0 0x1ee0000 0x0 0x1000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
clockgen: clocking@1ee1000 {
|
||||
compatible = "fsl,ls1046a-clockgen";
|
||||
reg = <0x0 0x1ee1000 0x0 0x1000>;
|
||||
#clock-cells = <2>;
|
||||
clocks = <&sysclk>;
|
||||
};
|
||||
|
||||
tmu: tmu@1f00000 {
|
||||
compatible = "fsl,qoriq-tmu";
|
||||
reg = <0x0 0x1f00000 0x0 0x10000>;
|
||||
interrupts = <0 33 0x4>;
|
||||
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
|
||||
fsl,tmu-calibration =
|
||||
/* Calibration data group 1 */
|
||||
<0x00000000 0x00000026
|
||||
0x00000001 0x0000002d
|
||||
0x00000002 0x00000032
|
||||
0x00000003 0x00000039
|
||||
0x00000004 0x0000003f
|
||||
0x00000005 0x00000046
|
||||
0x00000006 0x0000004d
|
||||
0x00000007 0x00000054
|
||||
0x00000008 0x0000005a
|
||||
0x00000009 0x00000061
|
||||
0x0000000a 0x0000006a
|
||||
0x0000000b 0x00000071
|
||||
/* Calibration data group 2 */
|
||||
0x00010000 0x00000025
|
||||
0x00010001 0x0000002c
|
||||
0x00010002 0x00000035
|
||||
0x00010003 0x0000003d
|
||||
0x00010004 0x00000045
|
||||
0x00010005 0x0000004e
|
||||
0x00010006 0x00000057
|
||||
0x00010007 0x00000061
|
||||
0x00010008 0x0000006b
|
||||
0x00010009 0x00000076
|
||||
/* Calibration data group 3 */
|
||||
0x00020000 0x00000029
|
||||
0x00020001 0x00000033
|
||||
0x00020002 0x0000003d
|
||||
0x00020003 0x00000049
|
||||
0x00020004 0x00000056
|
||||
0x00020005 0x00000061
|
||||
0x00020006 0x0000006d
|
||||
/* Calibration data group 4 */
|
||||
0x00030000 0x00000021
|
||||
0x00030001 0x0000002a
|
||||
0x00030002 0x0000003c
|
||||
0x00030003 0x0000004e>;
|
||||
big-endian;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
#include "fsl-tmu.dtsi"
|
||||
|
||||
dspi: dspi@2100000 {
|
||||
compatible = "fsl,ls1021a-v1.0-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2100000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 1>;
|
||||
spi-num-chipselects = <5>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@2180000 {
|
||||
compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2180000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
dmas = <&edma0 1 39>,
|
||||
<&edma0 1 38>;
|
||||
dma-names = "tx", "rx";
|
||||
scl-gpios = <&gpio3 12 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@2190000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2190000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@21a0000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x21a0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@21b0000 {
|
||||
compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x21b0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
scl-gpios = <&gpio3 12 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
duart0: serial@21c0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0500 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
duart1: serial@21c0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0600 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
duart2: serial@21d0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0500 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
duart3: serial@21d0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0600 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
gpio0: gpio@2300000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2300000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@2310000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2310000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@2320000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2320000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@2330000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2330000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio-hc {
|
||||
compatible = "gpio-leds";
|
||||
};
|
||||
|
||||
lpuart0: serial@2950000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2950000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart1: serial@2960000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2960000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart2: serial@2970000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2970000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart3: serial@2980000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2980000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart4: serial@2990000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2990000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart5: serial@29a0000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x29a0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ftm0: ftm0@29d0000 {
|
||||
compatible = "fsl,ls1046a-ftm-alarm";
|
||||
reg = <0x0 0x29d0000 0x0 0x10000>,
|
||||
<0x0 0x1ee2140 0x0 0x4>;
|
||||
reg-names = "ftm", "pmctrl";
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
wdog0: watchdog@2ad0000 {
|
||||
compatible = "fsl,imx21-wdt";
|
||||
reg = <0x0 0x2ad0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
edma0: edma@2c00000 {
|
||||
#dma-cells = <2>;
|
||||
compatible = "fsl,vf610-edma";
|
||||
reg = <0x0 0x2c00000 0x0 0x10000>,
|
||||
<0x0 0x2c10000 0x0 0x10000>,
|
||||
<0x0 0x2c20000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma-tx", "edma-err";
|
||||
dma-channels = <32>;
|
||||
big-endian;
|
||||
clock-names = "dmamux0", "dmamux1";
|
||||
clocks = <&clockgen 4 1>,
|
||||
<&clockgen 4 1>;
|
||||
};
|
||||
|
||||
usb0: usb@2f00000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x2f00000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
usb1: usb@3000000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3000000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
usb2: usb@3100000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3100000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
sata: sata@3200000 {
|
||||
compatible = "fsl,ls1046a-ahci";
|
||||
reg = <0x0 0x3200000 0x0 0x10000>,
|
||||
<0x0 0x20140520 0x0 0x4>;
|
||||
reg-names = "ahci", "sata-ecc";
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
qdma: qdma@8380000 {
|
||||
compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
|
||||
reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
|
||||
<0x0 0x8390000 0x0 0x10000>, /* Status regs */
|
||||
<0x0 0x83a0000 0x0 0x40000>; /* Block regs */
|
||||
interrupts = <0 153 0x4>,
|
||||
<0 39 0x4>,
|
||||
<0 40 0x4>,
|
||||
<0 41 0x4>,
|
||||
<0 42 0x4>;
|
||||
interrupt-names = "qdma-error", "qdma-queue0",
|
||||
"qdma-queue1", "qdma-queue2", "qdma-queue3";
|
||||
channels = <8>;
|
||||
block-number = <1>;
|
||||
block-offset = <0x10000>;
|
||||
queues = <2>;
|
||||
status-sizes = <64>;
|
||||
queue-sizes = <64 64>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
msi1: msi-controller@1580000 {
|
||||
compatible = "fsl,ls1046a-msi";
|
||||
msi-controller;
|
||||
reg = <0x0 0x1580000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
msi2: msi-controller@1590000 {
|
||||
compatible = "fsl,ls1046a-msi";
|
||||
msi-controller;
|
||||
reg = <0x0 0x1590000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
msi3: msi-controller@15a0000 {
|
||||
compatible = "fsl,ls1046a-msi";
|
||||
msi-controller;
|
||||
reg = <0x0 0x15a0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
||||
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <4>;
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <6>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pcie@3500000 {
|
||||
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
||||
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <2>;
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <6>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pcie@3600000 {
|
||||
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
||||
0x50 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <2>;
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <6>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
serdes1: serdes@1ea0000 {
|
||||
reg = <0x0 0x1ea0000 0 0x00002000>;
|
||||
compatible = "fsl,serdes-10g";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
bman_fbpr: bman-fbpr {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
qman_fqd: qman-fqd {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x800000>;
|
||||
alignment = <0 0x800000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
qman_pfdr: qman-pfdr {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "qoriq-qman-portals.dtsi"
|
||||
#include "qoriq-bman-portals.dtsi"
|
||||
|
||||
&thermal_zones {
|
||||
thermal-zone0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone4 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Thermal Monitor Unit.
|
||||
*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* Tang Yuantian <andy.tang@nxp.com>
|
||||
*
|
||||
*/
|
||||
|
||||
&thermal_zones {
|
||||
thermal-zone0 {
|
||||
cooling-maps {
|
||||
map1 {
|
||||
trip = <&alert0>;
|
||||
cooling-device =
|
||||
<&cooling_map1 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone1 {
|
||||
cooling-maps {
|
||||
map1 {
|
||||
trip = <&alert1>;
|
||||
cooling-device =
|
||||
<&cooling_map1 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone2 {
|
||||
cooling-maps {
|
||||
map1 {
|
||||
trip = <&alert2>;
|
||||
cooling-device =
|
||||
<&cooling_map1 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone3 {
|
||||
cooling-maps {
|
||||
map1 {
|
||||
trip = <&alert3>;
|
||||
cooling-device =
|
||||
<&cooling_map1 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone4 {
|
||||
cooling-maps {
|
||||
map1 {
|
||||
trip = <&alert4>;
|
||||
cooling-device =
|
||||
<&cooling_map1 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone5 {
|
||||
cooling-maps {
|
||||
map1 {
|
||||
trip = <&alert5>;
|
||||
cooling-device =
|
||||
<&cooling_map1 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone6 {
|
||||
cooling-maps {
|
||||
map1 {
|
||||
trip = <&alert6>;
|
||||
cooling-device =
|
||||
<&cooling_map1 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone7 {
|
||||
cooling-maps {
|
||||
map1 {
|
||||
trip = <&alert7>;
|
||||
cooling-device =
|
||||
<&cooling_map1 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Thermal Monitor Unit.
|
||||
*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* Tang Yuantian <andy.tang@nxp.com>
|
||||
*
|
||||
*/
|
||||
|
||||
&thermal_zones {
|
||||
thermal-zone0 {
|
||||
cooling-maps {
|
||||
map2 {
|
||||
trip = <&alert0>;
|
||||
cooling-device =
|
||||
<&cooling_map2 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone1 {
|
||||
cooling-maps {
|
||||
map2 {
|
||||
trip = <&alert1>;
|
||||
cooling-device =
|
||||
<&cooling_map2 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone2 {
|
||||
cooling-maps {
|
||||
map2 {
|
||||
trip = <&alert2>;
|
||||
cooling-device =
|
||||
<&cooling_map2 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone3 {
|
||||
cooling-maps {
|
||||
map2 {
|
||||
trip = <&alert3>;
|
||||
cooling-device =
|
||||
<&cooling_map2 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone4 {
|
||||
cooling-maps {
|
||||
map2 {
|
||||
trip = <&alert4>;
|
||||
cooling-device =
|
||||
<&cooling_map2 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone5 {
|
||||
cooling-maps {
|
||||
map2 {
|
||||
trip = <&alert5>;
|
||||
cooling-device =
|
||||
<&cooling_map2 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone6 {
|
||||
cooling-maps {
|
||||
map2 {
|
||||
trip = <&alert6>;
|
||||
cooling-device =
|
||||
<&cooling_map2 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone7 {
|
||||
cooling-maps {
|
||||
map2 {
|
||||
trip = <&alert7>;
|
||||
cooling-device =
|
||||
<&cooling_map2 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Thermal Monitor Unit.
|
||||
*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* Tang Yuantian <andy.tang@nxp.com>
|
||||
*
|
||||
*/
|
||||
|
||||
&thermal_zones {
|
||||
thermal-zone0 {
|
||||
cooling-maps {
|
||||
map3 {
|
||||
trip = <&alert0>;
|
||||
cooling-device =
|
||||
<&cooling_map3 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone1 {
|
||||
cooling-maps {
|
||||
map3 {
|
||||
trip = <&alert1>;
|
||||
cooling-device =
|
||||
<&cooling_map3 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone2 {
|
||||
cooling-maps {
|
||||
map3 {
|
||||
trip = <&alert2>;
|
||||
cooling-device =
|
||||
<&cooling_map3 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone3 {
|
||||
cooling-maps {
|
||||
map3 {
|
||||
trip = <&alert3>;
|
||||
cooling-device =
|
||||
<&cooling_map3 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone4 {
|
||||
cooling-maps {
|
||||
map3 {
|
||||
trip = <&alert4>;
|
||||
cooling-device =
|
||||
<&cooling_map3 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone5 {
|
||||
cooling-maps {
|
||||
map3 {
|
||||
trip = <&alert5>;
|
||||
cooling-device =
|
||||
<&cooling_map3 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone6 {
|
||||
cooling-maps {
|
||||
map3 {
|
||||
trip = <&alert6>;
|
||||
cooling-device =
|
||||
<&cooling_map3 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone7 {
|
||||
cooling-maps {
|
||||
map3 {
|
||||
trip = <&alert7>;
|
||||
cooling-device =
|
||||
<&cooling_map3 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,251 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Thermal Monitor Unit.
|
||||
*
|
||||
* Copyright 2018 NXP
|
||||
*
|
||||
* Tang Yuantian <andy.tang@nxp.com>
|
||||
*
|
||||
*/
|
||||
|
||||
thermal_zones: thermal-zones {
|
||||
thermal_zone0: thermal-zone0 {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 0>;
|
||||
status = "disabled";
|
||||
|
||||
trips {
|
||||
alert0: alert0 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
crit0: crit0 {
|
||||
temperature = <105000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&alert0>;
|
||||
cooling-device =
|
||||
<&cooling_map0 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone1 {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 1>;
|
||||
status = "disabled";
|
||||
|
||||
trips {
|
||||
alert1: alert1 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
crit1: crit1 {
|
||||
temperature = <105000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&alert1>;
|
||||
cooling-device =
|
||||
<&cooling_map0 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone2 {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 2>;
|
||||
status = "disabled";
|
||||
|
||||
trips {
|
||||
alert2: alert2 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
crit2: crit2 {
|
||||
temperature = <105000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&alert2>;
|
||||
cooling-device =
|
||||
<&cooling_map0 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone3 {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 3>;
|
||||
status = "disabled";
|
||||
|
||||
trips {
|
||||
alert3: alert3 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
crit3: crit3 {
|
||||
temperature = <105000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&alert3>;
|
||||
cooling-device =
|
||||
<&cooling_map0 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone4 {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 4>;
|
||||
status = "disabled";
|
||||
|
||||
trips {
|
||||
alert4: alert4 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
crit4: crit4 {
|
||||
temperature = <105000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&alert4>;
|
||||
cooling-device =
|
||||
<&cooling_map0 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone5 {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 5>;
|
||||
status = "disabled";
|
||||
|
||||
trips {
|
||||
alert5: alert5 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
crit5: crit5 {
|
||||
temperature = <105000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&alert5>;
|
||||
cooling-device =
|
||||
<&cooling_map0 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone6 {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 6>;
|
||||
status = "disabled";
|
||||
|
||||
trips {
|
||||
alert6: alert6 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
crit6: crit6 {
|
||||
temperature = <105000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&alert6>;
|
||||
cooling-device =
|
||||
<&cooling_map0 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zone7 {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 7>;
|
||||
status = "disabled";
|
||||
|
||||
trips {
|
||||
alert7: alert7 {
|
||||
temperature = <95000>;
|
||||
hysteresis = <2000>;
|
||||
type = "passive";
|
||||
};
|
||||
|
||||
crit7: crit7 {
|
||||
temperature = <105000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&alert7>;
|
||||
cooling-device =
|
||||
<&cooling_map0 THERMAL_NO_LIMIT
|
||||
THERMAL_NO_LIMIT>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree file for Freescale LS1012A RDB Board.
|
||||
*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "hcen101-ls1012a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "huachentel hc-en101 Board";
|
||||
compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &pfe_mac0;
|
||||
ethernet1 = &pfe_mac1;
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&duart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
mmc-hs200-1_8v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pfe {
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethernet@0 {
|
||||
compatible = "fsl,pfe-gemac-port";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0>; /* GEM_ID */
|
||||
fsl,gemac-bus-id = <0x0>; /* BUS_ID */
|
||||
fsl,gemac-phy-id = <0x2>; /* PHY_ID */
|
||||
fsl,mdio-mux-val = <0x0>;
|
||||
phy-mode = "sgmii";
|
||||
fsl,pfe-phy-if-flags = <0x0>;
|
||||
|
||||
mdio@0 {
|
||||
reg = <0x1>; /* enabled/disabled */
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@1 {
|
||||
compatible = "fsl,pfe-gemac-port";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x1>; /* GEM_ID */
|
||||
fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
|
||||
fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
|
||||
fsl,mdio-mux-val = <0x0>;
|
||||
phy-mode = "rgmii-txid";
|
||||
fsl,pfe-phy-if-flags = <0x0>;
|
||||
|
||||
mdio@0 {
|
||||
reg = <0x0>; /* enabled/disabled */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "disable";
|
||||
qflash0: s25fs512s@0 {
|
||||
compatible = "spansion,m25p80";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <20000000>;
|
||||
m25p,fast-read;
|
||||
reg = <0>;
|
||||
spi-rx-bus-width = <2>;
|
||||
spi-tx-bus-width = <2>;
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -44,7 +44,7 @@
|
|||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "hc-ls1043a-hcen1002.dts"
|
||||
#include "hc-ls1043a-hcen1002a.dts"
|
||||
#include "qoriq-qman-portals-sdk.dtsi"
|
||||
#include "qoriq-bman-portals-sdk.dtsi"
|
||||
|
||||
|
|
@ -8,7 +8,7 @@
|
|||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include "hc-ls1043a-hcen1002-sdk.dts"
|
||||
#include "hc-ls1043a-hcen1002a-sdk.dts"
|
||||
|
||||
&soc {
|
||||
bp7: buffer-pool@7 {
|
||||
|
|
@ -85,11 +85,16 @@
|
|||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* For legacy usdpaa based use-cases, update the size and
|
||||
alignment parameters. e.g. to allocate 256 MB memory:
|
||||
size = <0 0x10000000>;
|
||||
alignment = <0 0x10000000>;
|
||||
*/
|
||||
usdpaa_mem: usdpaa_mem {
|
||||
compatible = "fsl,usdpaa-mem";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
size = <0 0x10000000>;
|
||||
alignment = <0 0x10000000>;
|
||||
size = <0 0x1000>;
|
||||
alignment = <0 0x1000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -8,7 +8,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "fsl-ls1043a.dtsi"
|
||||
#include "hcen1002a-ls1043a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1043A RDB Board";
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
|
||||
*
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Mingkai Hu <Mingkai.hu@freescale.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "hc-ls1043a-hcen1002b.dts"
|
||||
#include "qoriq-qman-portals-sdk.dtsi"
|
||||
#include "qoriq-bman-portals-sdk.dtsi"
|
||||
|
||||
&bman_fbpr {
|
||||
compatible = "fsl,bman-fbpr";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
&qman_fqd {
|
||||
compatible = "fsl,qman-fqd";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
&qman_pfdr {
|
||||
compatible = "fsl,qman-pfdr";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
#include "qoriq-dpaa-eth.dtsi"
|
||||
#include "qoriq-fman3-0-6oh.dtsi"
|
||||
};
|
||||
|
||||
&fman0 {
|
||||
compatible = "fsl,fman", "simple-bus";
|
||||
};
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
|
||||
*
|
||||
* Copyright 2014-2015, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include "hc-ls1043a-hcen1002b-sdk.dts"
|
||||
|
||||
&soc {
|
||||
bp7: buffer-pool@7 {
|
||||
compatible = "fsl,p4080-bpool", "fsl,bpool";
|
||||
fsl,bpid = <7>;
|
||||
fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
|
||||
fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
|
||||
};
|
||||
|
||||
bp8: buffer-pool@8 {
|
||||
compatible = "fsl,p4080-bpool", "fsl,bpool";
|
||||
fsl,bpid = <8>;
|
||||
fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
|
||||
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
|
||||
};
|
||||
|
||||
bp9: buffer-pool@9 {
|
||||
compatible = "fsl,p4080-bpool", "fsl,bpool";
|
||||
fsl,bpid = <9>;
|
||||
fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
|
||||
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
|
||||
};
|
||||
|
||||
fsl,dpaa {
|
||||
compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
|
||||
|
||||
ethernet@1 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
|
||||
fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
|
||||
};
|
||||
|
||||
ethernet@2 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
|
||||
fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
|
||||
};
|
||||
|
||||
ethernet@3 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
|
||||
fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
|
||||
};
|
||||
|
||||
ethernet@4 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
|
||||
fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
|
||||
};
|
||||
|
||||
ethernet@8 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
|
||||
fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
|
||||
|
||||
};
|
||||
dpa-fman0-oh@2 {
|
||||
compatible = "fsl,dpa-oh";
|
||||
/* Define frame queues for the OH port*/
|
||||
/* <OH Rx error, OH Rx default> */
|
||||
fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
|
||||
fsl,fman-oh-port = <&fman0_oh2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
/ {
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
/* For legacy usdpaa based use-cases, update the size and
|
||||
alignment parameters. e.g. to allocate 256 MB memory:
|
||||
size = <0 0x10000000>;
|
||||
alignment = <0 0x10000000>;
|
||||
*/
|
||||
usdpaa_mem: usdpaa_mem {
|
||||
compatible = "fsl,usdpaa-mem";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
size = <0 0x1000>;
|
||||
alignment = <0 0x1000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fman0 {
|
||||
fman0_oh2: port@83000 {
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,fman-port-oh";
|
||||
reg = <0x83000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,193 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
|
||||
*
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Mingkai Hu <Mingkai.hu@freescale.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "hcen1002b-ls1043a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1043A RDB Board";
|
||||
|
||||
aliases {
|
||||
crypto = &crypto;
|
||||
serial0 = &duart0;
|
||||
serial1 = &duart1;
|
||||
serial2 = &duart2;
|
||||
serial3 = &duart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
ina220@40 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
adt7461a@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
eeprom@52 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x52>;
|
||||
};
|
||||
eeprom@53 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x53>;
|
||||
};
|
||||
rtc@68 {
|
||||
compatible = "pericom,pt7c4338";
|
||||
reg = <0x68>;
|
||||
};
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf85263";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
|
||||
&ifc {
|
||||
status = "disable";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
/* NOR, NAND Flashes and FPGA on board */
|
||||
ranges = <0x0 0x0 0x0 0x60000000 0x08000000
|
||||
0x1 0x0 0x0 0x7e800000 0x00010000
|
||||
0x2 0x0 0x0 0x7fb00000 0x00000100>;
|
||||
|
||||
nor@0,0 {
|
||||
compatible = "cfi-flash";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@1,0 {
|
||||
compatible = "fsl,ifc-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x1 0x0 0x10000>;
|
||||
};
|
||||
|
||||
cpld: board-control@2,0 {
|
||||
compatible = "fsl,ls1043ardb-cpld";
|
||||
reg = <0x2 0x0 0x0000100>;
|
||||
};
|
||||
};
|
||||
|
||||
&dspi0 {
|
||||
bus-num = <0>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>; /* input clock */
|
||||
};
|
||||
|
||||
slic@2 {
|
||||
compatible = "maxim,ds26522";
|
||||
reg = <2>;
|
||||
spi-max-frequency = <2000000>;
|
||||
fsl,spi-cs-sck-delay = <100>;
|
||||
fsl,spi-sck-cs-delay = <50>;
|
||||
};
|
||||
|
||||
slic@3 {
|
||||
compatible = "maxim,ds26522";
|
||||
reg = <3>;
|
||||
spi-max-frequency = <2000000>;
|
||||
fsl,spi-cs-sck-delay = <100>;
|
||||
fsl,spi-sck-cs-delay = <50>;
|
||||
};
|
||||
};
|
||||
|
||||
&uqe {
|
||||
ucc_hdlc: ucc@2000 {
|
||||
compatible = "fsl,ucc-hdlc";
|
||||
rx-clock-name = "clk8";
|
||||
tx-clock-name = "clk9";
|
||||
fsl,rx-sync-clock = "rsync_pin";
|
||||
fsl,tx-sync-clock = "tsync_pin";
|
||||
fsl,tx-timeslot-mask = <0xfffffffe>;
|
||||
fsl,rx-timeslot-mask = <0xfffffffe>;
|
||||
fsl,tdm-framer-type = "e1";
|
||||
fsl,tdm-id = <0>;
|
||||
fsl,siram-entry-id = <0>;
|
||||
fsl,tdm-interface;
|
||||
};
|
||||
};
|
||||
|
||||
&duart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&duart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#include "fsl-ls1043-post.dtsi"
|
||||
|
||||
&fman0 {
|
||||
ethernet@e2000 {
|
||||
phy-handle = <&sgmii_phy1>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&rgmii_phy2>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
phy-handle = <&sgmii_phy2>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
phy-handle = <&sgmii_phy3>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
mdio@fc000 {
|
||||
sgmii_phy1: ethernet-phy@1 {
|
||||
reg = <0x16>;
|
||||
};
|
||||
|
||||
sgmii_phy2: ethernet-phy@2 {
|
||||
reg = <0x15>;
|
||||
};
|
||||
|
||||
sgmii_phy3: ethernet-phy@3 {
|
||||
reg = <0x17>;
|
||||
};
|
||||
|
||||
rgmii_phy2: ethernet-phy@4 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@fd000 {
|
||||
rgmii_phy1: ethernet-phy@5 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -8,7 +8,7 @@
|
|||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "fsl-ls1043a.dtsi"
|
||||
#include "hcen104-ls1043a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1043A RDB Board";
|
||||
|
|
@ -56,7 +56,7 @@
|
|||
};
|
||||
|
||||
&ifc {
|
||||
status = "okay";
|
||||
status = "disable";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
/* NOR, NAND Flashes and FPGA on board */
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
|
||||
*
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Mingkai Hu <Mingkai.hu@freescale.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "hc-ls1046a-hcen1004.dts"
|
||||
#include "qoriq-qman-portals-sdk.dtsi"
|
||||
#include "qoriq-bman-portals-sdk.dtsi"
|
||||
|
||||
&bman_fbpr {
|
||||
compatible = "fsl,bman-fbpr";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
&qman_fqd {
|
||||
compatible = "fsl,qman-fqd";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
&qman_pfdr {
|
||||
compatible = "fsl,qman-pfdr";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
#include "qoriq-dpaa-eth.dtsi"
|
||||
#include "qoriq-fman3-0-6oh.dtsi"
|
||||
};
|
||||
|
||||
&fsldpaa {
|
||||
ethernet@0 {
|
||||
status = "disabled";
|
||||
};
|
||||
ethernet@9 {
|
||||
compatible = "fsl,dpa-ethernet";
|
||||
fsl,fman-mac = <&enet7>;
|
||||
dma-coherent;
|
||||
};
|
||||
};
|
||||
|
||||
&fman0 {
|
||||
compatible = "fsl,fman", "simple-bus";
|
||||
};
|
||||
|
||||
&mdio9 {
|
||||
pcsphy6: ethernet-phy@0 {
|
||||
backplane-mode = "10gbase-kr";
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x0>;
|
||||
fsl,lane-handle = <&serdes1>;
|
||||
fsl,lane-reg = <0x8C0 0x40>; /* lane D */
|
||||
};
|
||||
};
|
||||
|
||||
&mdio10 {
|
||||
pcsphy7: ethernet-phy@0 {
|
||||
backplane-mode = "10gbase-kr";
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x0>;
|
||||
fsl,lane-handle = <&serdes1>;
|
||||
fsl,lane-reg = <0x880 0x40>; /* lane C */
|
||||
};
|
||||
};
|
||||
|
||||
/* Update MAC connections to backplane PHYs
|
||||
* &mac9 {
|
||||
* phy-handle = <&pcsphy6>;
|
||||
*};
|
||||
*
|
||||
*&mac10 {
|
||||
* phy-handle = <&pcsphy7>;
|
||||
*};
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,118 @@
|
|||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
|
||||
*
|
||||
* Copyright 2016, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include "hc-ls1046a-hcen1004-sdk.dts"
|
||||
|
||||
&soc {
|
||||
bp7: buffer-pool@7 {
|
||||
compatible = "fsl,ls1046a-bpool", "fsl,bpool";
|
||||
fsl,bpid = <7>;
|
||||
fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
|
||||
fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
|
||||
};
|
||||
|
||||
bp8: buffer-pool@8 {
|
||||
compatible = "fsl,ls1046a-bpool", "fsl,bpool";
|
||||
fsl,bpid = <8>;
|
||||
fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
|
||||
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
|
||||
};
|
||||
|
||||
bp9: buffer-pool@9 {
|
||||
compatible = "fsl,ls1046a-bpool", "fsl,bpool";
|
||||
fsl,bpid = <9>;
|
||||
fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
|
||||
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
|
||||
};
|
||||
|
||||
fsl,dpaa {
|
||||
compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
|
||||
|
||||
ethernet@1 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
|
||||
fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
|
||||
};
|
||||
|
||||
ethernet@2 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
|
||||
fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
|
||||
};
|
||||
|
||||
ethernet@3 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
|
||||
fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
|
||||
};
|
||||
|
||||
ethernet@4 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
|
||||
fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
|
||||
};
|
||||
|
||||
ethernet@5 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
|
||||
fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
|
||||
};
|
||||
|
||||
ethernet@8 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
|
||||
fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
|
||||
};
|
||||
|
||||
ethernet@9 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
|
||||
fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
|
||||
};
|
||||
|
||||
dpa-fman0-oh@2 {
|
||||
compatible = "fsl,dpa-oh";
|
||||
/* Define frame queues for the OH port*/
|
||||
/* <OH Rx error, OH Rx default> */
|
||||
fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
|
||||
fsl,fman-oh-port = <&fman0_oh2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
/ {
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
usdpaa_mem: usdpaa_mem {
|
||||
compatible = "fsl,usdpaa-mem";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
size = <0 0x10000000>;
|
||||
alignment = <0 0x10000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fman0 {
|
||||
fman0_oh2: port@83000 {
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,fman-port-oh";
|
||||
reg = <0x83000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,198 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
|
||||
*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Mingkai Hu <mingkai.hu@nxp.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "hcen1004-ls1046a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1046A RDB Board";
|
||||
compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
|
||||
|
||||
aliases {
|
||||
serial0 = &duart0;
|
||||
serial1 = &duart1;
|
||||
serial2 = &duart2;
|
||||
serial3 = &duart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&duart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&duart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
ina220@40 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x40>;
|
||||
shunt-resistor = <1000>;
|
||||
};
|
||||
|
||||
temp-sensor@4c {
|
||||
compatible = "adi,adt7461";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
eeprom@56 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x52>;
|
||||
};
|
||||
|
||||
eeprom@57 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x53>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
|
||||
rtc@51 {
|
||||
compatible = "nxp,pcf2129";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
*/
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
/* NAND Flashe and CPLD on board */
|
||||
ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
|
||||
0x2 0x0 0x0 0x7fb00000 0x00000100>;
|
||||
status = "okay";
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "fsl,ifc-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0 0x0 0x10000>;
|
||||
};
|
||||
|
||||
cpld: board-control@2,0 {
|
||||
compatible = "fsl,ls1046ardb-cpld";
|
||||
reg = <0x2 0x0 0x0000100>;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
num-cs = <2>;
|
||||
bus-num = <0>;
|
||||
status = "okay";
|
||||
fsl,qspi-has-second-chip;
|
||||
|
||||
qflash0: s25fs512s@0 {
|
||||
compatible = "spansion,m25p80";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
};
|
||||
|
||||
qflash1: s25fs512s@1 {
|
||||
compatible = "spansion,m25p80";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "fsl-ls1046-post.dtsi"
|
||||
|
||||
&fman0 {
|
||||
|
||||
ethernet@e2000 {
|
||||
phy-handle = <&sgmii_phy1>;
|
||||
phy-connection-type = "sgmii";
|
||||
max-speed = <1000>;
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&rgmii_phy2>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
phy-handle = <&sgmii_phy2>;
|
||||
phy-connection-type = "sgmii";
|
||||
max-speed = <1000>;
|
||||
};
|
||||
|
||||
ethernet@ea000 {
|
||||
phy-handle = <&sgmii_phy3>;
|
||||
phy-connection-type = "sgmii";
|
||||
max-speed = <1000>;
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
phy-handle = <&sgmii_phy4>;
|
||||
phy-connection-type = "sgmii";
|
||||
max-speed = <1000>;
|
||||
};
|
||||
|
||||
ethernet@f2000 {
|
||||
phy-handle = <&sgmii_phy5>;
|
||||
phy-connection-type = "sgmii";
|
||||
max-speed = <1000>;
|
||||
};
|
||||
|
||||
mdio@fc000 {
|
||||
rgmii_phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
sgmii_phy1: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
sgmii_phy2: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
|
||||
sgmii_phy3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
sgmii_phy4: ethernet-phy@6 {
|
||||
reg = <0x6>;
|
||||
};
|
||||
|
||||
sgmii_phy5: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@fd000 {
|
||||
rgmii_phy2: ethernet-phy@12 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
116
kernel/linux-4.14.83/arch/arm64/boot/dts/huachentel/hc-ls1046a-hcen1004a-sdk.dts
Executable file
116
kernel/linux-4.14.83/arch/arm64/boot/dts/huachentel/hc-ls1046a-hcen1004a-sdk.dts
Executable file
|
|
@ -0,0 +1,116 @@
|
|||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
|
||||
*
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Mingkai Hu <Mingkai.hu@freescale.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPLv2 or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "hc-ls1046a-hcen1004a.dts"
|
||||
#include "qoriq-qman-portals-sdk.dtsi"
|
||||
#include "qoriq-bman-portals-sdk.dtsi"
|
||||
|
||||
&bman_fbpr {
|
||||
compatible = "fsl,bman-fbpr";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
&qman_fqd {
|
||||
compatible = "fsl,qman-fqd";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
&qman_pfdr {
|
||||
compatible = "fsl,qman-pfdr";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
};
|
||||
|
||||
&soc {
|
||||
#include "qoriq-dpaa-eth.dtsi"
|
||||
#include "qoriq-fman3-0-6oh.dtsi"
|
||||
};
|
||||
|
||||
&fsldpaa {
|
||||
ethernet@0 {
|
||||
status = "disabled";
|
||||
};
|
||||
ethernet@1 {
|
||||
status = "disabled";
|
||||
};
|
||||
ethernet@9 {
|
||||
compatible = "fsl,dpa-ethernet";
|
||||
fsl,fman-mac = <&enet7>;
|
||||
dma-coherent;
|
||||
};
|
||||
};
|
||||
|
||||
&fman0 {
|
||||
compatible = "fsl,fman", "simple-bus";
|
||||
};
|
||||
|
||||
&mdio9 {
|
||||
pcsphy6: ethernet-phy@0 {
|
||||
backplane-mode = "10gbase-kr";
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x0>;
|
||||
fsl,lane-handle = <&serdes1>;
|
||||
fsl,lane-reg = <0x8C0 0x40>; /* lane D */
|
||||
};
|
||||
};
|
||||
|
||||
&mdio10 {
|
||||
pcsphy7: ethernet-phy@0 {
|
||||
backplane-mode = "10gbase-kr";
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x0>;
|
||||
fsl,lane-handle = <&serdes1>;
|
||||
fsl,lane-reg = <0x880 0x40>; /* lane C */
|
||||
};
|
||||
};
|
||||
|
||||
/* Update MAC connections to backplane PHYs
|
||||
* &mac9 {
|
||||
* phy-handle = <&pcsphy6>;
|
||||
*};
|
||||
*
|
||||
*&mac10 {
|
||||
* phy-handle = <&pcsphy7>;
|
||||
*};
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
|
||||
*
|
||||
* Copyright 2016, Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include "hc-ls1046a-hcen1004a-sdk.dts"
|
||||
|
||||
&soc {
|
||||
bp7: buffer-pool@7 {
|
||||
compatible = "fsl,ls1046a-bpool", "fsl,bpool";
|
||||
fsl,bpid = <7>;
|
||||
fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
|
||||
fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
|
||||
};
|
||||
|
||||
bp8: buffer-pool@8 {
|
||||
compatible = "fsl,ls1046a-bpool", "fsl,bpool";
|
||||
fsl,bpid = <8>;
|
||||
fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
|
||||
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
|
||||
};
|
||||
|
||||
bp9: buffer-pool@9 {
|
||||
compatible = "fsl,ls1046a-bpool", "fsl,bpool";
|
||||
fsl,bpid = <9>;
|
||||
fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
|
||||
fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
|
||||
};
|
||||
|
||||
fsl,dpaa {
|
||||
compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
|
||||
|
||||
ethernet@2 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
|
||||
fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
|
||||
};
|
||||
|
||||
ethernet@3 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
|
||||
fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
|
||||
};
|
||||
|
||||
ethernet@4 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
|
||||
fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
|
||||
};
|
||||
|
||||
ethernet@5 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
|
||||
fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
|
||||
};
|
||||
|
||||
ethernet@8 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
|
||||
fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
|
||||
};
|
||||
|
||||
ethernet@9 {
|
||||
compatible = "fsl,dpa-ethernet-init";
|
||||
fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
|
||||
fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
|
||||
fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
|
||||
};
|
||||
|
||||
dpa-fman0-oh@2 {
|
||||
compatible = "fsl,dpa-oh";
|
||||
/* Define frame queues for the OH port*/
|
||||
/* <OH Rx error, OH Rx default> */
|
||||
fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
|
||||
fsl,fman-oh-port = <&fman0_oh2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
/ {
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
usdpaa_mem: usdpaa_mem {
|
||||
compatible = "fsl,usdpaa-mem";
|
||||
alloc-ranges = <0 0 0x10000 0>;
|
||||
size = <0 0x10000000>;
|
||||
alignment = <0 0x10000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fman0 {
|
||||
fman0_oh2: port@83000 {
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,fman-port-oh";
|
||||
reg = <0x83000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,167 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
|
||||
*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Mingkai Hu <mingkai.hu@nxp.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "hcen1004a-ls1046a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "LS1046A RDB Board";
|
||||
compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
|
||||
|
||||
aliases {
|
||||
serial0 = &duart0;
|
||||
serial1 = &duart1;
|
||||
serial2 = &duart2;
|
||||
serial3 = &duart3;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&duart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&duart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
temp@48 {
|
||||
compatible = "ti,tmp101";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
rtc@32 {
|
||||
compatible = "epson,rx8025";
|
||||
reg = <0x32>;
|
||||
};
|
||||
|
||||
eeprom@56 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x52>;
|
||||
};
|
||||
|
||||
eeprom@57 {
|
||||
compatible = "atmel,24c512";
|
||||
reg = <0x53>;
|
||||
};
|
||||
};
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
/* NAND Flashe and CPLD on board */
|
||||
ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
|
||||
0x2 0x0 0x0 0x7fb00000 0x00000100>;
|
||||
status = "okay";
|
||||
|
||||
nand@0,0 {
|
||||
compatible = "fsl,ifc-nand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0 0x0 0x10000>;
|
||||
};
|
||||
|
||||
cpld: board-control@2,0 {
|
||||
compatible = "fsl,ls1046ardb-cpld";
|
||||
reg = <0x2 0x0 0x0000100>;
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
num-cs = <2>;
|
||||
bus-num = <0>;
|
||||
status = "disable";
|
||||
fsl,qspi-has-second-chip;
|
||||
|
||||
qflash0: s25fs512s@0 {
|
||||
compatible = "spansion,m25p80";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
};
|
||||
|
||||
qflash1: s25fs512s@1 {
|
||||
compatible = "spansion,m25p80";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-tx-bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "fsl-ls1046-post.dtsi"
|
||||
|
||||
&fman0 {
|
||||
ethernet@e4000 {
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
phy-handle = <&rgmii_phy2>;
|
||||
phy-connection-type = "rgmii";
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
phy-handle = <&sgmii_phy1>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@ea000 {
|
||||
phy-handle = <&sgmii_phy2>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@f0000 { /* 10GEC1 */
|
||||
fixed-link = <0 1 1000 0 0>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
ethernet@f2000 { /* 10GEC2 */
|
||||
fixed-link = <0 1 1000 0 0>;
|
||||
phy-connection-type = "xgmii";
|
||||
};
|
||||
|
||||
mdio@fc000 {
|
||||
|
||||
rgmii_phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
sgmii_phy1: ethernet-phy@17 {
|
||||
reg = <0x17>;
|
||||
};
|
||||
|
||||
sgmii_phy2: ethernet-phy@14 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio@fd000 {
|
||||
|
||||
rgmii_phy2: ethernet-phy@5 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,907 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
|
||||
*
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Mingkai Hu <Mingkai.hu@freescale.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "fsl,ls1043a";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
fman0 = &fman0;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
ethernet4 = &enet4;
|
||||
ethernet5 = &enet5;
|
||||
ethernet6 = &enet6;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/*
|
||||
* We expect the enable-method for cpu's to be "psci", but this
|
||||
* is dependent on the SoC FW, which will fill this in.
|
||||
*
|
||||
* Currently supported enable-method is psci v0.2
|
||||
*/
|
||||
cooling_map0: cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
#cooling-cells = <2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x2>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x3>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
l2: l2-cache {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
/*
|
||||
* PSCI node is not added default, U-boot will add missing
|
||||
* parts if it determines to use PSCI.
|
||||
*/
|
||||
entry-method = "arm,psci";
|
||||
|
||||
CPU_PH20: cpu-ph20 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "PH20";
|
||||
arm,psci-suspend-param = <0x0>;
|
||||
entry-latency-us = <1000>;
|
||||
exit-latency-us = <1000>;
|
||||
min-residency-us = <3000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0 0x80000000>;
|
||||
/* DRAM space 1, size: 2GiB DRAM */
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
bman_fbpr: bman-fbpr {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
qman_fqd: qman-fqd {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
qman_pfdr: qman-pfdr {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
sysclk: sysclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible ="syscon-reboot";
|
||||
regmap = <&dcfg>;
|
||||
offset = <0xb0>;
|
||||
mask = <0x02>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0xf08>, /* Physical Secure PPI */
|
||||
<1 14 0xf08>, /* Physical Non-Secure PPI */
|
||||
<1 11 0xf08>, /* Virtual PPI */
|
||||
<1 10 0xf08>; /* Hypervisor PPI */
|
||||
fsl,erratum-a008585;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <0 106 0x4>,
|
||||
<0 107 0x4>,
|
||||
<0 95 0x4>,
|
||||
<0 97 0x4>;
|
||||
interrupt-affinity = <&cpu0>,
|
||||
<&cpu1>,
|
||||
<&cpu2>,
|
||||
<&cpu3>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1400000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x1401000 0 0x1000>, /* GICD */
|
||||
<0x0 0x1402000 0 0x2000>, /* GICC */
|
||||
<0x0 0x1404000 0 0x2000>, /* GICH */
|
||||
<0x0 0x1406000 0 0x2000>; /* GICV */
|
||||
interrupts = <1 9 0xf08>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
|
||||
|
||||
clockgen: clocking@1ee1000 {
|
||||
compatible = "fsl,ls1043a-clockgen";
|
||||
reg = <0x0 0x1ee1000 0x0 0x1000>;
|
||||
#clock-cells = <2>;
|
||||
clocks = <&sysclk>;
|
||||
};
|
||||
|
||||
scfg: scfg@1570000 {
|
||||
compatible = "fsl,ls1043a-scfg", "syscon";
|
||||
reg = <0x0 0x1570000 0x0 0x10000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
crypto: crypto@1700000 {
|
||||
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
|
||||
"fsl,sec-v4.0";
|
||||
fsl,sec-era = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x1700000 0x100000>;
|
||||
reg = <0x00 0x1700000 0x0 0x100000>;
|
||||
interrupts = <0 75 0x4>;
|
||||
|
||||
sec_jr0: jr@10000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x10000 0x10000>;
|
||||
interrupts = <0 71 0x4>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@20000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x20000 0x10000>;
|
||||
interrupts = <0 72 0x4>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@30000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <0 73 0x4>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@40000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x40000 0x10000>;
|
||||
interrupts = <0 74 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
dcfg: dcfg@1ee0000 {
|
||||
compatible = "fsl,ls1043a-dcfg", "syscon";
|
||||
reg = <0x0 0x1ee0000 0x0 0x1000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
ifc: ifc@1530000 {
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
reg = <0x0 0x1530000 0x0 0x10000>;
|
||||
big-endian;
|
||||
interrupts = <0 43 0x4>;
|
||||
};
|
||||
|
||||
qspi: quadspi@1550000 {
|
||||
compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x1550000 0x0 0x10000>,
|
||||
<0x0 0x40000000 0x0 0x4000000>;
|
||||
reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
interrupts = <0 99 0x4>;
|
||||
clock-names = "qspi_en", "qspi";
|
||||
clocks = <&clockgen 4 0>, <&clockgen 4 0>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc: esdhc@1560000 {
|
||||
compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
|
||||
reg = <0x0 0x1560000 0x0 0x10000>;
|
||||
interrupts = <0 62 0x4>;
|
||||
clock-frequency = <0>;
|
||||
voltage-ranges = <1800 1800 3300 3300>;
|
||||
sdhci,auto-cmd12;
|
||||
big-endian;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
ddr: memory-controller@1080000 {
|
||||
compatible = "fsl,qoriq-memory-controller";
|
||||
reg = <0x0 0x1080000 0x0 0x1000>;
|
||||
interrupts = <0 144 0x4>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
tmu: tmu@1f00000 {
|
||||
compatible = "fsl,qoriq-tmu";
|
||||
reg = <0x0 0x1f00000 0x0 0x10000>;
|
||||
interrupts = <0 33 0x4>;
|
||||
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
|
||||
fsl,tmu-calibration = <0x00000000 0x00000026
|
||||
0x00000001 0x0000002d
|
||||
0x00000002 0x00000032
|
||||
0x00000003 0x00000039
|
||||
0x00000004 0x0000003f
|
||||
0x00000005 0x00000046
|
||||
0x00000006 0x0000004d
|
||||
0x00000007 0x00000054
|
||||
0x00000008 0x0000005a
|
||||
0x00000009 0x00000061
|
||||
0x0000000a 0x0000006a
|
||||
0x0000000b 0x00000071
|
||||
|
||||
0x00010000 0x00000025
|
||||
0x00010001 0x0000002c
|
||||
0x00010002 0x00000035
|
||||
0x00010003 0x0000003d
|
||||
0x00010004 0x00000045
|
||||
0x00010005 0x0000004e
|
||||
0x00010006 0x00000057
|
||||
0x00010007 0x00000061
|
||||
0x00010008 0x0000006b
|
||||
0x00010009 0x00000076
|
||||
|
||||
0x00020000 0x00000029
|
||||
0x00020001 0x00000033
|
||||
0x00020002 0x0000003d
|
||||
0x00020003 0x00000049
|
||||
0x00020004 0x00000056
|
||||
0x00020005 0x00000061
|
||||
0x00020006 0x0000006d
|
||||
|
||||
0x00030000 0x00000021
|
||||
0x00030001 0x0000002a
|
||||
0x00030002 0x0000003c
|
||||
0x00030003 0x0000004e>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
#include "fsl-tmu.dtsi"
|
||||
|
||||
qman: qman@1880000 {
|
||||
compatible = "fsl,qman";
|
||||
reg = <0x0 0x1880000 0x0 0x10000>;
|
||||
interrupts = <0 45 0x4>;
|
||||
memory-region = <&qman_fqd &qman_pfdr>;
|
||||
};
|
||||
|
||||
bman: bman@1890000 {
|
||||
compatible = "fsl,bman";
|
||||
reg = <0x0 0x1890000 0x0 0x10000>;
|
||||
interrupts = <0 45 0x4>;
|
||||
memory-region = <&bman_fbpr>;
|
||||
};
|
||||
|
||||
bportals: bman-portals@508000000 {
|
||||
ranges = <0x0 0x5 0x08000000 0x8000000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@500000000 {
|
||||
ranges = <0x0 0x5 0x00000000 0x8000000>;
|
||||
};
|
||||
|
||||
dspi0: dspi@2100000 {
|
||||
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2100000 0x0 0x10000>;
|
||||
interrupts = <0 64 0x4>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 0>;
|
||||
spi-num-chipselects = <5>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dspi1: dspi@2110000 {
|
||||
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2110000 0x0 0x10000>;
|
||||
interrupts = <0 65 0x4>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 0>;
|
||||
spi-num-chipselects = <5>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@2180000 {
|
||||
compatible = "fsl,vf610-i2c", "fsl,ls1043a-vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2180000 0x0 0x10000>;
|
||||
interrupts = <0 56 0x4>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 0>;
|
||||
dmas = <&edma0 1 39>,
|
||||
<&edma0 1 38>;
|
||||
dma-names = "tx", "rx";
|
||||
scl-gpios = <&gpio4 12 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@2190000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2190000 0x0 0x10000>;
|
||||
interrupts = <0 57 0x4>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@21a0000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x21a0000 0x0 0x10000>;
|
||||
interrupts = <0 58 0x4>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@21b0000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x21b0000 0x0 0x10000>;
|
||||
interrupts = <0 59 0x4>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
duart0: serial@21c0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0500 0x0 0x100>;
|
||||
interrupts = <0 54 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
};
|
||||
|
||||
duart1: serial@21c0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0600 0x0 0x100>;
|
||||
interrupts = <0 54 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
};
|
||||
|
||||
duart2: serial@21d0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0500 0x0 0x100>;
|
||||
interrupts = <0 55 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
};
|
||||
|
||||
duart3: serial@21d0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0600 0x0 0x100>;
|
||||
interrupts = <0 55 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
};
|
||||
|
||||
gpio1: gpio@2300000 {
|
||||
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2300000 0x0 0x10000>;
|
||||
interrupts = <0 66 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@2310000 {
|
||||
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2310000 0x0 0x10000>;
|
||||
interrupts = <0 67 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@2320000 {
|
||||
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2320000 0x0 0x10000>;
|
||||
interrupts = <0 68 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@2330000 {
|
||||
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2330000 0x0 0x10000>;
|
||||
interrupts = <0 134 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
sys {
|
||||
label = "sys";
|
||||
gpios = <&gpio4 12 1>;
|
||||
linux,default-trigger = "timer";
|
||||
};
|
||||
|
||||
lte_0 {
|
||||
label = "lte_0";
|
||||
gpios = <&gpio4 13 1>;
|
||||
};
|
||||
|
||||
lte_1 {
|
||||
label = "lte_1";
|
||||
gpios = <&gpio1 20 1>;
|
||||
};
|
||||
|
||||
lte_2 {
|
||||
label = "lte_2";
|
||||
gpios = <&gpio1 21 1>;
|
||||
};
|
||||
|
||||
wifi_24G {
|
||||
label = "wifi_24g";
|
||||
gpios = <&gpio4 11 1>;
|
||||
};
|
||||
|
||||
wifi_5G {
|
||||
label = "wifi_5g";
|
||||
gpios = <&gpio4 10 1>;
|
||||
};
|
||||
|
||||
cloud {
|
||||
label = "cloud";
|
||||
gpios = <&gpio1 16 0>;
|
||||
};
|
||||
|
||||
lte {
|
||||
label = "lte";
|
||||
gpios = <&gpio2 10 1>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys-polled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
poll-interval = <20>;
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&gpio2 27 1>;
|
||||
linux,code = <0x198>;
|
||||
};
|
||||
};
|
||||
|
||||
uqe: uqe@2400000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
compatible = "fsl,qe", "simple-bus";
|
||||
ranges = <0x0 0x0 0x2400000 0x40000>;
|
||||
reg = <0x0 0x2400000 0x0 0x480>;
|
||||
brg-frequency = <100000000>;
|
||||
bus-frequency = <200000000>;
|
||||
|
||||
fsl,qe-num-riscs = <1>;
|
||||
fsl,qe-num-snums = <28>;
|
||||
|
||||
qeic: qeic@80 {
|
||||
compatible = "fsl,qe-ic";
|
||||
reg = <0x80 0x80>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <0 77 0x04 0 77 0x04>;
|
||||
};
|
||||
|
||||
si1: si@700 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,ls1043-qe-si",
|
||||
"fsl,t1040-qe-si";
|
||||
reg = <0x700 0x80>;
|
||||
};
|
||||
|
||||
siram1: siram@1000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ls1043-qe-siram",
|
||||
"fsl,t1040-qe-siram";
|
||||
reg = <0x1000 0x800>;
|
||||
};
|
||||
|
||||
ucc@2000 {
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@2200 {
|
||||
cell-index = <3>;
|
||||
reg = <0x2200 0x200>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x10000 0x6000>;
|
||||
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0x6000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lpuart0: serial@2950000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2950000 0x0 0x1000>;
|
||||
interrupts = <0 48 0x4>;
|
||||
clocks = <&clockgen 0 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart1: serial@2960000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2960000 0x0 0x1000>;
|
||||
interrupts = <0 49 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart2: serial@2970000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2970000 0x0 0x1000>;
|
||||
interrupts = <0 50 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart3: serial@2980000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2980000 0x0 0x1000>;
|
||||
interrupts = <0 51 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart4: serial@2990000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2990000 0x0 0x1000>;
|
||||
interrupts = <0 52 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart5: serial@29a0000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x29a0000 0x0 0x1000>;
|
||||
interrupts = <0 53 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ftm0: ftm0@29d0000 {
|
||||
compatible = "fsl,ls1043a-ftm-alarm";
|
||||
reg = <0x0 0x29d0000 0x0 0x10000>,
|
||||
<0x0 0x1ee2140 0x0 0x4>;
|
||||
reg-names = "ftm", "pmctrl";
|
||||
interrupts = <0 86 0x4>;
|
||||
big-endian;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wdog0: wdog@2ad0000 {
|
||||
compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x0 0x2ad0000 0x0 0x10000>;
|
||||
interrupts = <0 83 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "wdog";
|
||||
big-endian;
|
||||
};
|
||||
|
||||
edma0: edma@2c00000 {
|
||||
#dma-cells = <2>;
|
||||
compatible = "fsl,vf610-edma";
|
||||
reg = <0x0 0x2c00000 0x0 0x10000>,
|
||||
<0x0 0x2c10000 0x0 0x10000>,
|
||||
<0x0 0x2c20000 0x0 0x10000>;
|
||||
interrupts = <0 103 0x4>,
|
||||
<0 103 0x4>;
|
||||
interrupt-names = "edma-tx", "edma-err";
|
||||
dma-channels = <32>;
|
||||
big-endian;
|
||||
clock-names = "dmamux0", "dmamux1";
|
||||
clocks = <&clockgen 4 0>,
|
||||
<&clockgen 4 0>;
|
||||
};
|
||||
|
||||
usb0: usb3@2f00000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x2f00000 0x0 0x10000>;
|
||||
interrupts = <0 60 0x4>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
usb1: usb3@3000000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3000000 0x0 0x10000>;
|
||||
interrupts = <0 61 0x4>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
usb2: usb3@3100000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3100000 0x0 0x10000>;
|
||||
interrupts = <0 63 0x4>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
sata: sata@3200000 {
|
||||
compatible = "fsl,ls1043a-ahci";
|
||||
reg = <0x0 0x3200000 0x0 0x10000>,
|
||||
<0x0 0x20140520 0x0 0x4>;
|
||||
reg-names = "ahci", "sata-ecc";
|
||||
interrupts = <0 69 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
qdma: qdma@8380000 {
|
||||
compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
|
||||
reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
|
||||
<0x0 0x8390000 0x0 0x10000>, /* Status regs */
|
||||
<0x0 0x83a0000 0x0 0x40000>; /* Block regs */
|
||||
interrupts = <0 152 0x4>,
|
||||
<0 39 0x4>,
|
||||
<0 40 0x4>,
|
||||
<0 41 0x4>,
|
||||
<0 42 0x4>;
|
||||
interrupt-names = "qdma-error", "qdma-queue0",
|
||||
"qdma-queue1", "qdma-queue2", "qdma-queue3";
|
||||
channels = <8>;
|
||||
block-number = <1>;
|
||||
block-offset = <0x10000>;
|
||||
queues = <2>;
|
||||
status-sizes = <64>;
|
||||
queue-sizes = <64 64>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
msi1: msi-controller1@1571000 {
|
||||
compatible = "fsl,ls1043a-msi";
|
||||
reg = <0x0 0x1571000 0x0 0x8>;
|
||||
msi-controller;
|
||||
interrupts = <0 116 0x4>;
|
||||
};
|
||||
|
||||
msi2: msi-controller2@1572000 {
|
||||
compatible = "fsl,ls1043a-msi";
|
||||
reg = <0x0 0x1572000 0x0 0x8>;
|
||||
msi-controller;
|
||||
interrupts = <0 126 0x4>;
|
||||
};
|
||||
|
||||
msi3: msi-controller3@1573000 {
|
||||
compatible = "fsl,ls1043a-msi";
|
||||
reg = <0x0 0x1573000 0x0 0x8>;
|
||||
msi-controller;
|
||||
interrupts = <0 160 0x4>;
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
||||
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 117 0x4>, /* PME interrupt */
|
||||
<0 118 0x4>; /* aer interrupt */
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <4>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
|
||||
<0000 0 0 2 &gic 0 111 0x4>,
|
||||
<0000 0 0 3 &gic 0 112 0x4>,
|
||||
<0000 0 0 4 &gic 0 113 0x4>;
|
||||
};
|
||||
|
||||
pcie@3500000 {
|
||||
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
||||
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 127 0x4>,
|
||||
<0 128 0x4>;
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
|
||||
<0000 0 0 2 &gic 0 121 0x4>,
|
||||
<0000 0 0 3 &gic 0 122 0x4>,
|
||||
<0000 0 0 4 &gic 0 123 0x4>;
|
||||
};
|
||||
|
||||
pcie@3600000 {
|
||||
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
||||
0x50 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 161 0x4>,
|
||||
<0 162 0x4>;
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
|
||||
<0000 0 0 2 &gic 0 155 0x4>,
|
||||
<0000 0 0 3 &gic 0 156 0x4>,
|
||||
<0000 0 0 4 &gic 0 157 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
#include "qoriq-qman-portals.dtsi"
|
||||
#include "qoriq-bman-portals.dtsi"
|
||||
|
||||
&thermal_zones {
|
||||
thermal-zone0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone5 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,903 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
|
||||
*
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Mingkai Hu <Mingkai.hu@freescale.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "fsl,ls1043a";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
fman0 = &fman0;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
ethernet4 = &enet4;
|
||||
ethernet5 = &enet5;
|
||||
ethernet6 = &enet6;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/*
|
||||
* We expect the enable-method for cpu's to be "psci", but this
|
||||
* is dependent on the SoC FW, which will fill this in.
|
||||
*
|
||||
* Currently supported enable-method is psci v0.2
|
||||
*/
|
||||
cooling_map0: cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
#cooling-cells = <2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x2>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x3>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
l2: l2-cache {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
/*
|
||||
* PSCI node is not added default, U-boot will add missing
|
||||
* parts if it determines to use PSCI.
|
||||
*/
|
||||
entry-method = "arm,psci";
|
||||
|
||||
CPU_PH20: cpu-ph20 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "PH20";
|
||||
arm,psci-suspend-param = <0x0>;
|
||||
entry-latency-us = <1000>;
|
||||
exit-latency-us = <1000>;
|
||||
min-residency-us = <3000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0 0x80000000>;
|
||||
/* DRAM space 1, size: 2GiB DRAM */
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
bman_fbpr: bman-fbpr {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
qman_fqd: qman-fqd {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
qman_pfdr: qman-pfdr {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
sysclk: sysclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible ="syscon-reboot";
|
||||
regmap = <&dcfg>;
|
||||
offset = <0xb0>;
|
||||
mask = <0x02>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0xf08>, /* Physical Secure PPI */
|
||||
<1 14 0xf08>, /* Physical Non-Secure PPI */
|
||||
<1 11 0xf08>, /* Virtual PPI */
|
||||
<1 10 0xf08>; /* Hypervisor PPI */
|
||||
fsl,erratum-a008585;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <0 106 0x4>,
|
||||
<0 107 0x4>,
|
||||
<0 95 0x4>,
|
||||
<0 97 0x4>;
|
||||
interrupt-affinity = <&cpu0>,
|
||||
<&cpu1>,
|
||||
<&cpu2>,
|
||||
<&cpu3>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1400000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x1401000 0 0x1000>, /* GICD */
|
||||
<0x0 0x1402000 0 0x2000>, /* GICC */
|
||||
<0x0 0x1404000 0 0x2000>, /* GICH */
|
||||
<0x0 0x1406000 0 0x2000>; /* GICV */
|
||||
interrupts = <1 9 0xf08>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
|
||||
|
||||
clockgen: clocking@1ee1000 {
|
||||
compatible = "fsl,ls1043a-clockgen";
|
||||
reg = <0x0 0x1ee1000 0x0 0x1000>;
|
||||
#clock-cells = <2>;
|
||||
clocks = <&sysclk>;
|
||||
};
|
||||
|
||||
scfg: scfg@1570000 {
|
||||
compatible = "fsl,ls1043a-scfg", "syscon";
|
||||
reg = <0x0 0x1570000 0x0 0x10000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
crypto: crypto@1700000 {
|
||||
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
|
||||
"fsl,sec-v4.0";
|
||||
fsl,sec-era = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x1700000 0x100000>;
|
||||
reg = <0x00 0x1700000 0x0 0x100000>;
|
||||
interrupts = <0 75 0x4>;
|
||||
|
||||
sec_jr0: jr@10000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x10000 0x10000>;
|
||||
interrupts = <0 71 0x4>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@20000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x20000 0x10000>;
|
||||
interrupts = <0 72 0x4>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@30000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <0 73 0x4>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@40000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x40000 0x10000>;
|
||||
interrupts = <0 74 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
dcfg: dcfg@1ee0000 {
|
||||
compatible = "fsl,ls1043a-dcfg", "syscon";
|
||||
reg = <0x0 0x1ee0000 0x0 0x1000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
ifc: ifc@1530000 {
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
reg = <0x0 0x1530000 0x0 0x10000>;
|
||||
big-endian;
|
||||
interrupts = <0 43 0x4>;
|
||||
};
|
||||
|
||||
qspi: quadspi@1550000 {
|
||||
compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x1550000 0x0 0x10000>,
|
||||
<0x0 0x40000000 0x0 0x4000000>;
|
||||
reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
interrupts = <0 99 0x4>;
|
||||
clock-names = "qspi_en", "qspi";
|
||||
clocks = <&clockgen 4 0>, <&clockgen 4 0>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc: esdhc@1560000 {
|
||||
compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
|
||||
reg = <0x0 0x1560000 0x0 0x10000>;
|
||||
interrupts = <0 62 0x4>;
|
||||
clock-frequency = <0>;
|
||||
voltage-ranges = <1800 1800 3300 3300>;
|
||||
sdhci,auto-cmd12;
|
||||
big-endian;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
ddr: memory-controller@1080000 {
|
||||
compatible = "fsl,qoriq-memory-controller";
|
||||
reg = <0x0 0x1080000 0x0 0x1000>;
|
||||
interrupts = <0 144 0x4>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
tmu: tmu@1f00000 {
|
||||
compatible = "fsl,qoriq-tmu";
|
||||
reg = <0x0 0x1f00000 0x0 0x10000>;
|
||||
interrupts = <0 33 0x4>;
|
||||
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
|
||||
fsl,tmu-calibration = <0x00000000 0x00000026
|
||||
0x00000001 0x0000002d
|
||||
0x00000002 0x00000032
|
||||
0x00000003 0x00000039
|
||||
0x00000004 0x0000003f
|
||||
0x00000005 0x00000046
|
||||
0x00000006 0x0000004d
|
||||
0x00000007 0x00000054
|
||||
0x00000008 0x0000005a
|
||||
0x00000009 0x00000061
|
||||
0x0000000a 0x0000006a
|
||||
0x0000000b 0x00000071
|
||||
|
||||
0x00010000 0x00000025
|
||||
0x00010001 0x0000002c
|
||||
0x00010002 0x00000035
|
||||
0x00010003 0x0000003d
|
||||
0x00010004 0x00000045
|
||||
0x00010005 0x0000004e
|
||||
0x00010006 0x00000057
|
||||
0x00010007 0x00000061
|
||||
0x00010008 0x0000006b
|
||||
0x00010009 0x00000076
|
||||
|
||||
0x00020000 0x00000029
|
||||
0x00020001 0x00000033
|
||||
0x00020002 0x0000003d
|
||||
0x00020003 0x00000049
|
||||
0x00020004 0x00000056
|
||||
0x00020005 0x00000061
|
||||
0x00020006 0x0000006d
|
||||
|
||||
0x00030000 0x00000021
|
||||
0x00030001 0x0000002a
|
||||
0x00030002 0x0000003c
|
||||
0x00030003 0x0000004e>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
#include "fsl-tmu.dtsi"
|
||||
|
||||
qman: qman@1880000 {
|
||||
compatible = "fsl,qman";
|
||||
reg = <0x0 0x1880000 0x0 0x10000>;
|
||||
interrupts = <0 45 0x4>;
|
||||
memory-region = <&qman_fqd &qman_pfdr>;
|
||||
};
|
||||
|
||||
bman: bman@1890000 {
|
||||
compatible = "fsl,bman";
|
||||
reg = <0x0 0x1890000 0x0 0x10000>;
|
||||
interrupts = <0 45 0x4>;
|
||||
memory-region = <&bman_fbpr>;
|
||||
};
|
||||
|
||||
bportals: bman-portals@508000000 {
|
||||
ranges = <0x0 0x5 0x08000000 0x8000000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@500000000 {
|
||||
ranges = <0x0 0x5 0x00000000 0x8000000>;
|
||||
};
|
||||
|
||||
dspi0: dspi@2100000 {
|
||||
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2100000 0x0 0x10000>;
|
||||
interrupts = <0 64 0x4>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 0>;
|
||||
spi-num-chipselects = <5>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dspi1: dspi@2110000 {
|
||||
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2110000 0x0 0x10000>;
|
||||
interrupts = <0 65 0x4>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 0>;
|
||||
spi-num-chipselects = <5>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@2180000 {
|
||||
compatible = "fsl,vf610-i2c", "fsl,ls1043a-vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2180000 0x0 0x10000>;
|
||||
interrupts = <0 56 0x4>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 0>;
|
||||
dmas = <&edma0 1 39>,
|
||||
<&edma0 1 38>;
|
||||
dma-names = "tx", "rx";
|
||||
scl-gpios = <&gpio4 12 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@2190000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2190000 0x0 0x10000>;
|
||||
interrupts = <0 57 0x4>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@21a0000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x21a0000 0x0 0x10000>;
|
||||
interrupts = <0 58 0x4>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@21b0000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x21b0000 0x0 0x10000>;
|
||||
interrupts = <0 59 0x4>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
duart0: serial@21c0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0500 0x0 0x100>;
|
||||
interrupts = <0 54 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
};
|
||||
|
||||
duart1: serial@21c0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0600 0x0 0x100>;
|
||||
interrupts = <0 54 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
};
|
||||
|
||||
duart2: serial@21d0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0500 0x0 0x100>;
|
||||
interrupts = <0 55 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
};
|
||||
|
||||
duart3: serial@21d0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0600 0x0 0x100>;
|
||||
interrupts = <0 55 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
};
|
||||
|
||||
gpio1: gpio@2300000 {
|
||||
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2300000 0x0 0x10000>;
|
||||
interrupts = <0 66 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@2310000 {
|
||||
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2310000 0x0 0x10000>;
|
||||
interrupts = <0 67 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@2320000 {
|
||||
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2320000 0x0 0x10000>;
|
||||
interrupts = <0 68 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@2330000 {
|
||||
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2330000 0x0 0x10000>;
|
||||
interrupts = <0 134 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
sys {
|
||||
label = "sys";
|
||||
gpios = <&gpio4 12 1>;
|
||||
linux,default-trigger = "timer";
|
||||
};
|
||||
|
||||
lte_0 {
|
||||
label = "lte_0";
|
||||
gpios = <&gpio4 13 1>;
|
||||
};
|
||||
|
||||
lte_1 {
|
||||
label = "lte_1";
|
||||
gpios = <&gpio1 20 1>;
|
||||
};
|
||||
|
||||
lte_2 {
|
||||
label = "lte_2";
|
||||
gpios = <&gpio1 21 1>;
|
||||
};
|
||||
|
||||
wifi {
|
||||
label = "wifi";
|
||||
gpios = <&gpio4 10 1>;
|
||||
};
|
||||
|
||||
cloud {
|
||||
label = "cloud";
|
||||
gpios = <&gpio4 11 1>;
|
||||
};
|
||||
|
||||
lte {
|
||||
label = "lte";
|
||||
gpios = <&gpio2 10 1>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys-polled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
poll-interval = <20>;
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&gpio2 27 1>;
|
||||
linux,code = <0x198>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
uqe: uqe@2400000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
compatible = "fsl,qe", "simple-bus";
|
||||
ranges = <0x0 0x0 0x2400000 0x40000>;
|
||||
reg = <0x0 0x2400000 0x0 0x480>;
|
||||
brg-frequency = <100000000>;
|
||||
bus-frequency = <200000000>;
|
||||
|
||||
fsl,qe-num-riscs = <1>;
|
||||
fsl,qe-num-snums = <28>;
|
||||
|
||||
qeic: qeic@80 {
|
||||
compatible = "fsl,qe-ic";
|
||||
reg = <0x80 0x80>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <0 77 0x04 0 77 0x04>;
|
||||
};
|
||||
|
||||
si1: si@700 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,ls1043-qe-si",
|
||||
"fsl,t1040-qe-si";
|
||||
reg = <0x700 0x80>;
|
||||
};
|
||||
|
||||
siram1: siram@1000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ls1043-qe-siram",
|
||||
"fsl,t1040-qe-siram";
|
||||
reg = <0x1000 0x800>;
|
||||
};
|
||||
|
||||
ucc@2000 {
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@2200 {
|
||||
cell-index = <3>;
|
||||
reg = <0x2200 0x200>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x10000 0x6000>;
|
||||
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0x6000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lpuart0: serial@2950000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2950000 0x0 0x1000>;
|
||||
interrupts = <0 48 0x4>;
|
||||
clocks = <&clockgen 0 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart1: serial@2960000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2960000 0x0 0x1000>;
|
||||
interrupts = <0 49 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart2: serial@2970000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2970000 0x0 0x1000>;
|
||||
interrupts = <0 50 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart3: serial@2980000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2980000 0x0 0x1000>;
|
||||
interrupts = <0 51 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart4: serial@2990000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2990000 0x0 0x1000>;
|
||||
interrupts = <0 52 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart5: serial@29a0000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x29a0000 0x0 0x1000>;
|
||||
interrupts = <0 53 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ftm0: ftm0@29d0000 {
|
||||
compatible = "fsl,ls1043a-ftm-alarm";
|
||||
reg = <0x0 0x29d0000 0x0 0x10000>,
|
||||
<0x0 0x1ee2140 0x0 0x4>;
|
||||
reg-names = "ftm", "pmctrl";
|
||||
interrupts = <0 86 0x4>;
|
||||
big-endian;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wdog0: wdog@2ad0000 {
|
||||
compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x0 0x2ad0000 0x0 0x10000>;
|
||||
interrupts = <0 83 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "wdog";
|
||||
big-endian;
|
||||
};
|
||||
|
||||
edma0: edma@2c00000 {
|
||||
#dma-cells = <2>;
|
||||
compatible = "fsl,vf610-edma";
|
||||
reg = <0x0 0x2c00000 0x0 0x10000>,
|
||||
<0x0 0x2c10000 0x0 0x10000>,
|
||||
<0x0 0x2c20000 0x0 0x10000>;
|
||||
interrupts = <0 103 0x4>,
|
||||
<0 103 0x4>;
|
||||
interrupt-names = "edma-tx", "edma-err";
|
||||
dma-channels = <32>;
|
||||
big-endian;
|
||||
clock-names = "dmamux0", "dmamux1";
|
||||
clocks = <&clockgen 4 0>,
|
||||
<&clockgen 4 0>;
|
||||
};
|
||||
|
||||
usb0: usb3@2f00000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x2f00000 0x0 0x10000>;
|
||||
interrupts = <0 60 0x4>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
usb1: usb3@3000000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3000000 0x0 0x10000>;
|
||||
interrupts = <0 61 0x4>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
usb2: usb3@3100000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3100000 0x0 0x10000>;
|
||||
interrupts = <0 63 0x4>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
sata: sata@3200000 {
|
||||
compatible = "fsl,ls1043a-ahci";
|
||||
reg = <0x0 0x3200000 0x0 0x10000>,
|
||||
<0x0 0x20140520 0x0 0x4>;
|
||||
reg-names = "ahci", "sata-ecc";
|
||||
interrupts = <0 69 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
qdma: qdma@8380000 {
|
||||
compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
|
||||
reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
|
||||
<0x0 0x8390000 0x0 0x10000>, /* Status regs */
|
||||
<0x0 0x83a0000 0x0 0x40000>; /* Block regs */
|
||||
interrupts = <0 152 0x4>,
|
||||
<0 39 0x4>,
|
||||
<0 40 0x4>,
|
||||
<0 41 0x4>,
|
||||
<0 42 0x4>;
|
||||
interrupt-names = "qdma-error", "qdma-queue0",
|
||||
"qdma-queue1", "qdma-queue2", "qdma-queue3";
|
||||
channels = <8>;
|
||||
block-number = <1>;
|
||||
block-offset = <0x10000>;
|
||||
queues = <2>;
|
||||
status-sizes = <64>;
|
||||
queue-sizes = <64 64>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
msi1: msi-controller1@1571000 {
|
||||
compatible = "fsl,ls1043a-msi";
|
||||
reg = <0x0 0x1571000 0x0 0x8>;
|
||||
msi-controller;
|
||||
interrupts = <0 116 0x4>;
|
||||
};
|
||||
|
||||
msi2: msi-controller2@1572000 {
|
||||
compatible = "fsl,ls1043a-msi";
|
||||
reg = <0x0 0x1572000 0x0 0x8>;
|
||||
msi-controller;
|
||||
interrupts = <0 126 0x4>;
|
||||
};
|
||||
|
||||
msi3: msi-controller3@1573000 {
|
||||
compatible = "fsl,ls1043a-msi";
|
||||
reg = <0x0 0x1573000 0x0 0x8>;
|
||||
msi-controller;
|
||||
interrupts = <0 160 0x4>;
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
||||
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 117 0x4>, /* PME interrupt */
|
||||
<0 118 0x4>; /* aer interrupt */
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <4>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
|
||||
<0000 0 0 2 &gic 0 111 0x4>,
|
||||
<0000 0 0 3 &gic 0 112 0x4>,
|
||||
<0000 0 0 4 &gic 0 113 0x4>;
|
||||
};
|
||||
|
||||
pcie@3500000 {
|
||||
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
||||
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 127 0x4>,
|
||||
<0 128 0x4>;
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
|
||||
<0000 0 0 2 &gic 0 121 0x4>,
|
||||
<0000 0 0 3 &gic 0 122 0x4>,
|
||||
<0000 0 0 4 &gic 0 123 0x4>;
|
||||
};
|
||||
|
||||
pcie@3600000 {
|
||||
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
||||
0x50 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 161 0x4>,
|
||||
<0 162 0x4>;
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
|
||||
<0000 0 0 2 &gic 0 155 0x4>,
|
||||
<0000 0 0 3 &gic 0 156 0x4>,
|
||||
<0000 0 0 4 &gic 0 157 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
#include "qoriq-qman-portals.dtsi"
|
||||
#include "qoriq-bman-portals.dtsi"
|
||||
|
||||
&thermal_zones {
|
||||
thermal-zone0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone5 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,831 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
|
||||
*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Mingkai Hu <mingkai.hu@nxp.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
compatible = "fsl,ls1046a";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
crypto = &crypto;
|
||||
fman0 = &fman0;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
ethernet4 = &enet4;
|
||||
ethernet5 = &enet5;
|
||||
ethernet6 = &enet6;
|
||||
ethernet7 = &enet7;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cooling_map0: cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x1>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x2>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x3>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
l2: l2-cache {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
/*
|
||||
* PSCI node is not added default, U-boot will add missing
|
||||
* parts if it determines to use PSCI.
|
||||
*/
|
||||
entry-method = "arm,psci";
|
||||
|
||||
CPU_PH20: cpu-ph20 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "PH20";
|
||||
arm,psci-suspend-param = <0x0>;
|
||||
entry-latency-us = <1000>;
|
||||
exit-latency-us = <1000>;
|
||||
min-residency-us = <3000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
sysclk: sysclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible ="syscon-reboot";
|
||||
regmap = <&dcfg>;
|
||||
offset = <0xb0>;
|
||||
mask = <0x02>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>,
|
||||
<&cpu1>,
|
||||
<&cpu2>,
|
||||
<&cpu3>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1400000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x1410000 0 0x10000>, /* GICD */
|
||||
<0x0 0x1420000 0 0x20000>, /* GICC */
|
||||
<0x0 0x1440000 0 0x20000>, /* GICH */
|
||||
<0x0 0x1460000 0 0x20000>; /* GICV */
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
|
||||
|
||||
ddr: memory-controller@1080000 {
|
||||
compatible = "fsl,qoriq-memory-controller";
|
||||
reg = <0x0 0x1080000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
ifc: ifc@1530000 {
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
reg = <0x0 0x1530000 0x0 0x10000>;
|
||||
big-endian;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
qspi: quadspi@1550000 {
|
||||
compatible = "fsl,ls1021a-qspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x1550000 0x0 0x10000>,
|
||||
<0x0 0x40000000 0x0 0x10000000>;
|
||||
reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "qspi_en", "qspi";
|
||||
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc: esdhc@1560000 {
|
||||
compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
|
||||
reg = <0x0 0x1560000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 2 1>;
|
||||
voltage-ranges = <1800 1800 3300 3300>;
|
||||
sdhci,auto-cmd12;
|
||||
big-endian;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
scfg: scfg@1570000 {
|
||||
compatible = "fsl,ls1046a-scfg", "syscon";
|
||||
reg = <0x0 0x1570000 0x0 0x10000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
crypto: crypto@1700000 {
|
||||
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
|
||||
"fsl,sec-v4.0";
|
||||
fsl,sec-era = <8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x1700000 0x100000>;
|
||||
reg = <0x00 0x1700000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
sec_jr0: jr@10000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x10000 0x10000>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@20000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x20000 0x10000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@30000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@40000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x40000 0x10000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
qman: qman@1880000 {
|
||||
compatible = "fsl,qman";
|
||||
reg = <0x0 0x1880000 0x0 0x10000>;
|
||||
interrupts = <0 45 0x4>;
|
||||
memory-region = <&qman_fqd &qman_pfdr>;
|
||||
|
||||
};
|
||||
|
||||
bman: bman@1890000 {
|
||||
compatible = "fsl,bman";
|
||||
reg = <0x0 0x1890000 0x0 0x10000>;
|
||||
interrupts = <0 45 0x4>;
|
||||
memory-region = <&bman_fbpr>;
|
||||
|
||||
};
|
||||
|
||||
qportals: qman-portals@500000000 {
|
||||
ranges = <0x0 0x5 0x00000000 0x8000000>;
|
||||
};
|
||||
|
||||
bportals: bman-portals@508000000 {
|
||||
ranges = <0x0 0x5 0x08000000 0x8000000>;
|
||||
};
|
||||
|
||||
dcfg: dcfg@1ee0000 {
|
||||
compatible = "fsl,ls1046a-dcfg", "syscon";
|
||||
reg = <0x0 0x1ee0000 0x0 0x1000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
clockgen: clocking@1ee1000 {
|
||||
compatible = "fsl,ls1046a-clockgen";
|
||||
reg = <0x0 0x1ee1000 0x0 0x1000>;
|
||||
#clock-cells = <2>;
|
||||
clocks = <&sysclk>;
|
||||
};
|
||||
|
||||
tmu: tmu@1f00000 {
|
||||
compatible = "fsl,qoriq-tmu";
|
||||
reg = <0x0 0x1f00000 0x0 0x10000>;
|
||||
interrupts = <0 33 0x4>;
|
||||
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
|
||||
fsl,tmu-calibration =
|
||||
/* Calibration data group 1 */
|
||||
<0x00000000 0x00000026
|
||||
0x00000001 0x0000002d
|
||||
0x00000002 0x00000032
|
||||
0x00000003 0x00000039
|
||||
0x00000004 0x0000003f
|
||||
0x00000005 0x00000046
|
||||
0x00000006 0x0000004d
|
||||
0x00000007 0x00000054
|
||||
0x00000008 0x0000005a
|
||||
0x00000009 0x00000061
|
||||
0x0000000a 0x0000006a
|
||||
0x0000000b 0x00000071
|
||||
/* Calibration data group 2 */
|
||||
0x00010000 0x00000025
|
||||
0x00010001 0x0000002c
|
||||
0x00010002 0x00000035
|
||||
0x00010003 0x0000003d
|
||||
0x00010004 0x00000045
|
||||
0x00010005 0x0000004e
|
||||
0x00010006 0x00000057
|
||||
0x00010007 0x00000061
|
||||
0x00010008 0x0000006b
|
||||
0x00010009 0x00000076
|
||||
/* Calibration data group 3 */
|
||||
0x00020000 0x00000029
|
||||
0x00020001 0x00000033
|
||||
0x00020002 0x0000003d
|
||||
0x00020003 0x00000049
|
||||
0x00020004 0x00000056
|
||||
0x00020005 0x00000061
|
||||
0x00020006 0x0000006d
|
||||
/* Calibration data group 4 */
|
||||
0x00030000 0x00000021
|
||||
0x00030001 0x0000002a
|
||||
0x00030002 0x0000003c
|
||||
0x00030003 0x0000004e>;
|
||||
big-endian;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
#include "fsl-tmu.dtsi"
|
||||
|
||||
dspi: dspi@2100000 {
|
||||
compatible = "fsl,ls1021a-v1.0-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2100000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 1>;
|
||||
spi-num-chipselects = <5>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@2180000 {
|
||||
compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2180000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
dmas = <&edma0 1 39>,
|
||||
<&edma0 1 38>;
|
||||
dma-names = "tx", "rx";
|
||||
scl-gpios = <&gpio3 12 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@2190000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2190000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@21a0000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x21a0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@21b0000 {
|
||||
compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x21b0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
scl-gpios = <&gpio3 12 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
duart0: serial@21c0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0500 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
duart1: serial@21c0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0600 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
duart2: serial@21d0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0500 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
duart3: serial@21d0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0600 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
gpio0: gpio@2300000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2300000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@2310000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2310000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@2320000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2320000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@2330000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2330000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
sys {
|
||||
label = "sys";
|
||||
gpios = <&gpio3 12 1>;
|
||||
linux,default-trigger = "timer";
|
||||
};
|
||||
|
||||
lte_0 {
|
||||
label = "lte_0";
|
||||
gpios = <&gpio0 18 1>;
|
||||
};
|
||||
|
||||
lte_1 {
|
||||
label = "lte_1";
|
||||
gpios = <&gpio0 22 1>;
|
||||
};
|
||||
|
||||
lte_2 {
|
||||
label = "lte_2";
|
||||
gpios = <&gpio0 16 1>;
|
||||
};
|
||||
|
||||
wifi {
|
||||
label = "wifi";
|
||||
gpios = <&gpio3 13 1>;
|
||||
};
|
||||
|
||||
lte {
|
||||
label = "lte";
|
||||
gpios = <&gpio0 21 0>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys-polled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
poll-interval = <20>;
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&gpio0 21 1>;
|
||||
linux,code = <0x198>;
|
||||
};
|
||||
};
|
||||
|
||||
lpuart0: serial@2950000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2950000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart1: serial@2960000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2960000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart2: serial@2970000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2970000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart3: serial@2980000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2980000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart4: serial@2990000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2990000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart5: serial@29a0000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x29a0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ftm0: ftm0@29d0000 {
|
||||
compatible = "fsl,ls1046a-ftm-alarm";
|
||||
reg = <0x0 0x29d0000 0x0 0x10000>,
|
||||
<0x0 0x1ee2140 0x0 0x4>;
|
||||
reg-names = "ftm", "pmctrl";
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
wdog0: watchdog@2ad0000 {
|
||||
compatible = "fsl,imx21-wdt";
|
||||
reg = <0x0 0x2ad0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
edma0: edma@2c00000 {
|
||||
#dma-cells = <2>;
|
||||
compatible = "fsl,vf610-edma";
|
||||
reg = <0x0 0x2c00000 0x0 0x10000>,
|
||||
<0x0 0x2c10000 0x0 0x10000>,
|
||||
<0x0 0x2c20000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma-tx", "edma-err";
|
||||
dma-channels = <32>;
|
||||
big-endian;
|
||||
clock-names = "dmamux0", "dmamux1";
|
||||
clocks = <&clockgen 4 1>,
|
||||
<&clockgen 4 1>;
|
||||
};
|
||||
|
||||
usb0: usb@2f00000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x2f00000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
usb1: usb@3000000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3000000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
usb2: usb@3100000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3100000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
sata: sata@3200000 {
|
||||
compatible = "fsl,ls1046a-ahci";
|
||||
reg = <0x0 0x3200000 0x0 0x10000>,
|
||||
<0x0 0x20140520 0x0 0x4>;
|
||||
reg-names = "ahci", "sata-ecc";
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
qdma: qdma@8380000 {
|
||||
compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
|
||||
reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
|
||||
<0x0 0x8390000 0x0 0x10000>, /* Status regs */
|
||||
<0x0 0x83a0000 0x0 0x40000>; /* Block regs */
|
||||
interrupts = <0 153 0x4>,
|
||||
<0 39 0x4>,
|
||||
<0 40 0x4>,
|
||||
<0 41 0x4>,
|
||||
<0 42 0x4>;
|
||||
interrupt-names = "qdma-error", "qdma-queue0",
|
||||
"qdma-queue1", "qdma-queue2", "qdma-queue3";
|
||||
channels = <8>;
|
||||
block-number = <1>;
|
||||
block-offset = <0x10000>;
|
||||
queues = <2>;
|
||||
status-sizes = <64>;
|
||||
queue-sizes = <64 64>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
msi1: msi-controller@1580000 {
|
||||
compatible = "fsl,ls1046a-msi";
|
||||
msi-controller;
|
||||
reg = <0x0 0x1580000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
msi2: msi-controller@1590000 {
|
||||
compatible = "fsl,ls1046a-msi";
|
||||
msi-controller;
|
||||
reg = <0x0 0x1590000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
msi3: msi-controller@15a0000 {
|
||||
compatible = "fsl,ls1046a-msi";
|
||||
msi-controller;
|
||||
reg = <0x0 0x15a0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
||||
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <4>;
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <6>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pcie@3500000 {
|
||||
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
||||
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <2>;
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <6>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pcie@3600000 {
|
||||
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
||||
0x50 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <2>;
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <6>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
serdes1: serdes@1ea0000 {
|
||||
reg = <0x0 0x1ea0000 0 0x00002000>;
|
||||
compatible = "fsl,serdes-10g";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
bman_fbpr: bman-fbpr {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
qman_fqd: qman-fqd {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x800000>;
|
||||
alignment = <0 0x800000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
qman_pfdr: qman-pfdr {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "qoriq-qman-portals.dtsi"
|
||||
#include "qoriq-bman-portals.dtsi"
|
||||
|
||||
&thermal_zones {
|
||||
thermal-zone0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone4 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,794 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
|
||||
*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Mingkai Hu <mingkai.hu@nxp.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
compatible = "fsl,ls1046a";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
crypto = &crypto;
|
||||
fman0 = &fman0;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
ethernet4 = &enet4;
|
||||
ethernet5 = &enet5;
|
||||
ethernet6 = &enet6;
|
||||
ethernet7 = &enet7;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cooling_map0: cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x0>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x1>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x2>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x3>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
l2: l2-cache {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
/*
|
||||
* PSCI node is not added default, U-boot will add missing
|
||||
* parts if it determines to use PSCI.
|
||||
*/
|
||||
entry-method = "arm,psci";
|
||||
|
||||
CPU_PH20: cpu-ph20 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "PH20";
|
||||
arm,psci-suspend-param = <0x0>;
|
||||
entry-latency-us = <1000>;
|
||||
exit-latency-us = <1000>;
|
||||
min-residency-us = <3000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
sysclk: sysclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible ="syscon-reboot";
|
||||
regmap = <&dcfg>;
|
||||
offset = <0xb0>;
|
||||
mask = <0x02>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>,
|
||||
<&cpu1>,
|
||||
<&cpu2>,
|
||||
<&cpu3>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1400000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x1410000 0 0x10000>, /* GICD */
|
||||
<0x0 0x1420000 0 0x20000>, /* GICC */
|
||||
<0x0 0x1440000 0 0x20000>, /* GICH */
|
||||
<0x0 0x1460000 0 0x20000>; /* GICV */
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
|
||||
IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
|
||||
|
||||
ddr: memory-controller@1080000 {
|
||||
compatible = "fsl,qoriq-memory-controller";
|
||||
reg = <0x0 0x1080000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
ifc: ifc@1530000 {
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
reg = <0x0 0x1530000 0x0 0x10000>;
|
||||
big-endian;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
qspi: quadspi@1550000 {
|
||||
compatible = "fsl,ls1021a-qspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x1550000 0x0 0x10000>,
|
||||
<0x0 0x40000000 0x0 0x10000000>;
|
||||
reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "qspi_en", "qspi";
|
||||
clocks = <&clockgen 4 1>, <&clockgen 4 1>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc: esdhc@1560000 {
|
||||
compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
|
||||
reg = <0x0 0x1560000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 2 1>;
|
||||
voltage-ranges = <1800 1800 3300 3300>;
|
||||
sdhci,auto-cmd12;
|
||||
big-endian;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
scfg: scfg@1570000 {
|
||||
compatible = "fsl,ls1046a-scfg", "syscon";
|
||||
reg = <0x0 0x1570000 0x0 0x10000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
crypto: crypto@1700000 {
|
||||
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
|
||||
"fsl,sec-v4.0";
|
||||
fsl,sec-era = <8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x1700000 0x100000>;
|
||||
reg = <0x00 0x1700000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
sec_jr0: jr@10000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x10000 0x10000>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@20000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x20000 0x10000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@30000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@40000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x40000 0x10000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
qman: qman@1880000 {
|
||||
compatible = "fsl,qman";
|
||||
reg = <0x0 0x1880000 0x0 0x10000>;
|
||||
interrupts = <0 45 0x4>;
|
||||
memory-region = <&qman_fqd &qman_pfdr>;
|
||||
|
||||
};
|
||||
|
||||
bman: bman@1890000 {
|
||||
compatible = "fsl,bman";
|
||||
reg = <0x0 0x1890000 0x0 0x10000>;
|
||||
interrupts = <0 45 0x4>;
|
||||
memory-region = <&bman_fbpr>;
|
||||
|
||||
};
|
||||
|
||||
qportals: qman-portals@500000000 {
|
||||
ranges = <0x0 0x5 0x00000000 0x8000000>;
|
||||
};
|
||||
|
||||
bportals: bman-portals@508000000 {
|
||||
ranges = <0x0 0x5 0x08000000 0x8000000>;
|
||||
};
|
||||
|
||||
dcfg: dcfg@1ee0000 {
|
||||
compatible = "fsl,ls1046a-dcfg", "syscon";
|
||||
reg = <0x0 0x1ee0000 0x0 0x1000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
clockgen: clocking@1ee1000 {
|
||||
compatible = "fsl,ls1046a-clockgen";
|
||||
reg = <0x0 0x1ee1000 0x0 0x1000>;
|
||||
#clock-cells = <2>;
|
||||
clocks = <&sysclk>;
|
||||
};
|
||||
|
||||
tmu: tmu@1f00000 {
|
||||
compatible = "fsl,qoriq-tmu";
|
||||
reg = <0x0 0x1f00000 0x0 0x10000>;
|
||||
interrupts = <0 33 0x4>;
|
||||
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
|
||||
fsl,tmu-calibration =
|
||||
/* Calibration data group 1 */
|
||||
<0x00000000 0x00000026
|
||||
0x00000001 0x0000002d
|
||||
0x00000002 0x00000032
|
||||
0x00000003 0x00000039
|
||||
0x00000004 0x0000003f
|
||||
0x00000005 0x00000046
|
||||
0x00000006 0x0000004d
|
||||
0x00000007 0x00000054
|
||||
0x00000008 0x0000005a
|
||||
0x00000009 0x00000061
|
||||
0x0000000a 0x0000006a
|
||||
0x0000000b 0x00000071
|
||||
/* Calibration data group 2 */
|
||||
0x00010000 0x00000025
|
||||
0x00010001 0x0000002c
|
||||
0x00010002 0x00000035
|
||||
0x00010003 0x0000003d
|
||||
0x00010004 0x00000045
|
||||
0x00010005 0x0000004e
|
||||
0x00010006 0x00000057
|
||||
0x00010007 0x00000061
|
||||
0x00010008 0x0000006b
|
||||
0x00010009 0x00000076
|
||||
/* Calibration data group 3 */
|
||||
0x00020000 0x00000029
|
||||
0x00020001 0x00000033
|
||||
0x00020002 0x0000003d
|
||||
0x00020003 0x00000049
|
||||
0x00020004 0x00000056
|
||||
0x00020005 0x00000061
|
||||
0x00020006 0x0000006d
|
||||
/* Calibration data group 4 */
|
||||
0x00030000 0x00000021
|
||||
0x00030001 0x0000002a
|
||||
0x00030002 0x0000003c
|
||||
0x00030003 0x0000004e>;
|
||||
big-endian;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
#include "fsl-tmu.dtsi"
|
||||
|
||||
dspi: dspi@2100000 {
|
||||
compatible = "fsl,ls1021a-v1.0-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2100000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 1>;
|
||||
spi-num-chipselects = <5>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@2180000 {
|
||||
compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2180000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
dmas = <&edma0 1 39>,
|
||||
<&edma0 1 38>;
|
||||
dma-names = "tx", "rx";
|
||||
scl-gpios = <&gpio3 12 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@2190000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2190000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@21a0000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x21a0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@21b0000 {
|
||||
compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x21b0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
scl-gpios = <&gpio3 12 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
duart0: serial@21c0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0500 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
duart1: serial@21c0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0600 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
duart2: serial@21d0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0500 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
duart3: serial@21d0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0600 0x0 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
gpio0: gpio@2300000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2300000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@2310000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2310000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@2320000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2320000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@2330000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2330000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio-hc {
|
||||
compatible = "gpio-leds";
|
||||
sys {
|
||||
label = "sys";
|
||||
gpios = <&gpio3 12 1>;
|
||||
linux,default-trigger = "timer";
|
||||
};
|
||||
};
|
||||
|
||||
lpuart0: serial@2950000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2950000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart1: serial@2960000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2960000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart2: serial@2970000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2970000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart3: serial@2980000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2980000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart4: serial@2990000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2990000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart5: serial@29a0000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x29a0000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ftm0: ftm0@29d0000 {
|
||||
compatible = "fsl,ls1046a-ftm-alarm";
|
||||
reg = <0x0 0x29d0000 0x0 0x10000>,
|
||||
<0x0 0x1ee2140 0x0 0x4>;
|
||||
reg-names = "ftm", "pmctrl";
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
wdog0: watchdog@2ad0000 {
|
||||
compatible = "fsl,imx21-wdt";
|
||||
reg = <0x0 0x2ad0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
edma0: edma@2c00000 {
|
||||
#dma-cells = <2>;
|
||||
compatible = "fsl,vf610-edma";
|
||||
reg = <0x0 0x2c00000 0x0 0x10000>,
|
||||
<0x0 0x2c10000 0x0 0x10000>,
|
||||
<0x0 0x2c20000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma-tx", "edma-err";
|
||||
dma-channels = <32>;
|
||||
big-endian;
|
||||
clock-names = "dmamux0", "dmamux1";
|
||||
clocks = <&clockgen 4 1>,
|
||||
<&clockgen 4 1>;
|
||||
};
|
||||
|
||||
usb0: usb@2f00000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x2f00000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
usb1: usb@3000000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3000000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
usb2: usb@3100000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3100000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
sata: sata@3200000 {
|
||||
compatible = "fsl,ls1046a-ahci";
|
||||
reg = <0x0 0x3200000 0x0 0x10000>,
|
||||
<0x0 0x20140520 0x0 0x4>;
|
||||
reg-names = "ahci", "sata-ecc";
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
};
|
||||
|
||||
qdma: qdma@8380000 {
|
||||
compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
|
||||
reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
|
||||
<0x0 0x8390000 0x0 0x10000>, /* Status regs */
|
||||
<0x0 0x83a0000 0x0 0x40000>; /* Block regs */
|
||||
interrupts = <0 153 0x4>,
|
||||
<0 39 0x4>,
|
||||
<0 40 0x4>,
|
||||
<0 41 0x4>,
|
||||
<0 42 0x4>;
|
||||
interrupt-names = "qdma-error", "qdma-queue0",
|
||||
"qdma-queue1", "qdma-queue2", "qdma-queue3";
|
||||
channels = <8>;
|
||||
block-number = <1>;
|
||||
block-offset = <0x10000>;
|
||||
queues = <2>;
|
||||
status-sizes = <64>;
|
||||
queue-sizes = <64 64>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
msi1: msi-controller@1580000 {
|
||||
compatible = "fsl,ls1046a-msi";
|
||||
msi-controller;
|
||||
reg = <0x0 0x1580000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
msi2: msi-controller@1590000 {
|
||||
compatible = "fsl,ls1046a-msi";
|
||||
msi-controller;
|
||||
reg = <0x0 0x1590000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
msi3: msi-controller@15a0000 {
|
||||
compatible = "fsl,ls1046a-msi";
|
||||
msi-controller;
|
||||
reg = <0x0 0x15a0000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
||||
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <4>;
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <6>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pcie@3500000 {
|
||||
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
||||
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <2>;
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <6>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pcie@3600000 {
|
||||
compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
||||
0x50 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <2>;
|
||||
num-ib-windows = <6>;
|
||||
num-ob-windows = <6>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
serdes1: serdes@1ea0000 {
|
||||
reg = <0x0 0x1ea0000 0 0x00002000>;
|
||||
compatible = "fsl,serdes-10g";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
bman_fbpr: bman-fbpr {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
qman_fqd: qman-fqd {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x800000>;
|
||||
alignment = <0 0x800000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
qman_pfdr: qman-pfdr {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "qoriq-qman-portals.dtsi"
|
||||
#include "qoriq-bman-portals.dtsi"
|
||||
|
||||
&thermal_zones {
|
||||
thermal-zone0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone4 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,597 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1012A family SoC.
|
||||
*
|
||||
* Copyright 2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
|
||||
/ {
|
||||
compatible = "fsl,ls1012a";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
crypto = &crypto;
|
||||
rtic_a = &rtic_a;
|
||||
rtic_b = &rtic_b;
|
||||
rtic_c = &rtic_c;
|
||||
rtic_d = &rtic_d;
|
||||
sec_mon = &sec_mon;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cooling_map0: cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
#cooling-cells = <2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
/*
|
||||
* PSCI node is not added default, U-boot will add missing
|
||||
* parts if it determines to use PSCI.
|
||||
*/
|
||||
entry-method = "arm,psci";
|
||||
|
||||
CPU_PH20: cpu-ph20 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "PH20";
|
||||
arm,psci-suspend-param = <0x0>;
|
||||
entry-latency-us = <1000>;
|
||||
exit-latency-us = <1000>;
|
||||
min-residency-us = <3000>;
|
||||
};
|
||||
};
|
||||
|
||||
sysclk: sysclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
coreclk: coreclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "coreclk";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
|
||||
<1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
|
||||
<1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
|
||||
<1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1400000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x1401000 0 0x1000>, /* GICD */
|
||||
<0x0 0x1402000 0 0x2000>, /* GICC */
|
||||
<0x0 0x1404000 0 0x2000>, /* GICH */
|
||||
<0x0 0x1406000 0 0x2000>; /* GICV */
|
||||
interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&dcfg>;
|
||||
offset = <0xb0>;
|
||||
mask = <0x02>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
esdhc0: esdhc@1560000 {
|
||||
compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
|
||||
reg = <0x0 0x1560000 0x0 0x10000>;
|
||||
interrupts = <0 62 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
voltage-ranges = <1800 1800 3300 3300>;
|
||||
sdhci,auto-cmd12;
|
||||
big-endian;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scfg: scfg@1570000 {
|
||||
compatible = "fsl,ls1012a-scfg", "syscon";
|
||||
reg = <0x0 0x1570000 0x0 0x10000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
esdhc1: esdhc@1580000 {
|
||||
compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
|
||||
reg = <0x0 0x1580000 0x0 0x10000>;
|
||||
interrupts = <0 65 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
voltage-ranges = <1800 1800 3300 3300>;
|
||||
sdhci,auto-cmd12;
|
||||
big-endian;
|
||||
broken-cd;
|
||||
bus-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
crypto: crypto@1700000 {
|
||||
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
|
||||
"fsl,sec-v4.0";
|
||||
fsl,sec-era = <8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x1700000 0x100000>;
|
||||
reg = <0x00 0x1700000 0x0 0x100000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
sec_jr0: jr@10000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x10000 0x10000>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@20000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x20000 0x10000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@30000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@40000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x40000 0x10000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
rtic@60000 {
|
||||
compatible = "fsl,sec-v5.4-rtic",
|
||||
"fsl,sec-v5.0-rtic",
|
||||
"fsl,sec-v4.0-rtic";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x60000 0x100 0x60e00 0x18>;
|
||||
ranges = <0x0 0x60100 0x500>;
|
||||
|
||||
rtic_a: rtic-a@0 {
|
||||
compatible = "fsl,sec-v5.4-rtic-memory",
|
||||
"fsl,sec-v5.0-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x00 0x20 0x100 0x100>;
|
||||
};
|
||||
|
||||
rtic_b: rtic-b@20 {
|
||||
compatible = "fsl,sec-v5.4-rtic-memory",
|
||||
"fsl,sec-v5.0-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x20 0x20 0x200 0x100>;
|
||||
};
|
||||
|
||||
rtic_c: rtic-c@40 {
|
||||
compatible = "fsl,sec-v5.4-rtic-memory",
|
||||
"fsl,sec-v5.0-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x40 0x20 0x300 0x100>;
|
||||
};
|
||||
|
||||
rtic_d: rtic-d@60 {
|
||||
compatible = "fsl,sec-v5.4-rtic-memory",
|
||||
"fsl,sec-v5.0-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x60 0x20 0x400 0x100>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sec_mon: sec_mon@1e90000 {
|
||||
compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
|
||||
"fsl,sec-v4.0-mon";
|
||||
reg = <0x0 0x1e90000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
dcfg: dcfg@1ee0000 {
|
||||
compatible = "fsl,ls1012a-dcfg",
|
||||
"syscon";
|
||||
reg = <0x0 0x1ee0000 0x0 0x1000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
clockgen: clocking@1ee1000 {
|
||||
compatible = "fsl,ls1012a-clockgen";
|
||||
reg = <0x0 0x1ee1000 0x0 0x1000>;
|
||||
#clock-cells = <2>;
|
||||
clocks = <&sysclk &coreclk>;
|
||||
clock-names = "sysclk", "coreclk";
|
||||
};
|
||||
|
||||
tmu: tmu@1f00000 {
|
||||
compatible = "fsl,qoriq-tmu";
|
||||
reg = <0x0 0x1f00000 0x0 0x10000>;
|
||||
interrupts = <0 33 0x4>;
|
||||
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
|
||||
fsl,tmu-calibration = <0x00000000 0x00000026
|
||||
0x00000001 0x0000002d
|
||||
0x00000002 0x00000032
|
||||
0x00000003 0x00000039
|
||||
0x00000004 0x0000003f
|
||||
0x00000005 0x00000046
|
||||
0x00000006 0x0000004d
|
||||
0x00000007 0x00000054
|
||||
0x00000008 0x0000005a
|
||||
0x00000009 0x00000061
|
||||
0x0000000a 0x0000006a
|
||||
0x0000000b 0x00000071
|
||||
|
||||
0x00010000 0x00000025
|
||||
0x00010001 0x0000002c
|
||||
0x00010002 0x00000035
|
||||
0x00010003 0x0000003d
|
||||
0x00010004 0x00000045
|
||||
0x00010005 0x0000004e
|
||||
0x00010006 0x00000057
|
||||
0x00010007 0x00000061
|
||||
0x00010008 0x0000006b
|
||||
0x00010009 0x00000076
|
||||
|
||||
0x00020000 0x00000029
|
||||
0x00020001 0x00000033
|
||||
0x00020002 0x0000003d
|
||||
0x00020003 0x00000049
|
||||
0x00020004 0x00000056
|
||||
0x00020005 0x00000061
|
||||
0x00020006 0x0000006d
|
||||
|
||||
0x00030000 0x00000021
|
||||
0x00030001 0x0000002a
|
||||
0x00030002 0x0000003c
|
||||
0x00030003 0x0000004e>;
|
||||
big-endian;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
#include "fsl-tmu.dtsi"
|
||||
|
||||
ftm0: ftm0@29d0000 {
|
||||
compatible = "fsl,ls1012a-ftm-alarm";
|
||||
reg = <0x0 0x29d0000 0x0 0x10000>,
|
||||
<0x0 0x1ee2140 0x0 0x4>;
|
||||
reg-names = "ftm", "pmctrl";
|
||||
interrupts = <0 86 0x4>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
i2c0: i2c@2180000 {
|
||||
compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2180000 0x0 0x10000>;
|
||||
interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 3>;
|
||||
scl-gpios = <&gpio0 13 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@2190000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2190000 0x0 0x10000>;
|
||||
interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dspi: dspi@2100000 {
|
||||
compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2100000 0x0 0x10000>;
|
||||
interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 0>;
|
||||
spi-num-chipselects = <5>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
duart0: serial@21c0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0500 0x0 0x100>;
|
||||
interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
duart1: serial@21c0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0600 0x0 0x100>;
|
||||
interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio@2300000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2300000 0x0 0x10000>;
|
||||
interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio@2310000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2310000 0x0 0x10000>;
|
||||
interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
sys {
|
||||
label = "sys";
|
||||
gpios = <&gpio0 27 1>;
|
||||
linux,default-trigger = "timer";
|
||||
};
|
||||
|
||||
lte_0 {
|
||||
label = "lte_0";
|
||||
gpios = <&gpio0 28 1>;
|
||||
};
|
||||
|
||||
lte_1 {
|
||||
label = "lte_1";
|
||||
gpios = <&gpio0 29 1>;
|
||||
};
|
||||
|
||||
lte_2 {
|
||||
label = "lte_2";
|
||||
gpios = <&gpio0 24 1>;
|
||||
};
|
||||
|
||||
wifi {
|
||||
label = "wifi";
|
||||
gpios = <&gpio0 3 1>;
|
||||
};
|
||||
|
||||
cloud {
|
||||
label = "cloud";
|
||||
gpios = <&gpio0 13 1>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys-polled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
poll-interval = <20>;
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&gpio0 21 1>;
|
||||
linux,code = <0x198>;
|
||||
};
|
||||
};
|
||||
|
||||
wdog0: wdog@2ad0000 {
|
||||
compatible = "fsl,ls1012a-wdt",
|
||||
"fsl,imx21-wdt";
|
||||
reg = <0x0 0x2ad0000 0x0 0x10000>;
|
||||
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
qspi: quadspi@1550000 {
|
||||
compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x1550000 0x0 0x10000>,
|
||||
<0x0 0x40000000 0x0 0x10000000>;
|
||||
reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "qspi_en", "qspi";
|
||||
clocks = <&clockgen 4 0>, <&clockgen 4 0>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai1: sai@2b50000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,vf610-sai";
|
||||
reg = <0x0 0x2b50000 0x0 0x10000>;
|
||||
interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>,
|
||||
<&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&edma0 1 47>,
|
||||
<&edma0 1 46>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sai2: sai@2b60000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "fsl,vf610-sai";
|
||||
reg = <0x0 0x2b60000 0x0 0x10000>;
|
||||
interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 3>, <&clockgen 4 3>,
|
||||
<&clockgen 4 3>, <&clockgen 4 3>;
|
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
||||
dma-names = "tx", "rx";
|
||||
dmas = <&edma0 1 45>,
|
||||
<&edma0 1 44>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
edma0: edma@2c00000 {
|
||||
#dma-cells = <2>;
|
||||
compatible = "fsl,vf610-edma";
|
||||
reg = <0x0 0x2c00000 0x0 0x10000>,
|
||||
<0x0 0x2c10000 0x0 0x10000>,
|
||||
<0x0 0x2c20000 0x0 0x10000>;
|
||||
interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "edma-tx", "edma-err";
|
||||
dma-channels = <32>;
|
||||
big-endian;
|
||||
clock-names = "dmamux0", "dmamux1";
|
||||
clocks = <&clockgen 4 3>,
|
||||
<&clockgen 4 3>;
|
||||
};
|
||||
|
||||
usb0: usb3@2f00000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x2f00000 0x0 0x10000>;
|
||||
interrupts = <0 60 0x4>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
sata: sata@3200000 {
|
||||
compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
|
||||
reg = <0x0 0x3200000 0x0 0x10000>,
|
||||
<0x0 0x20140520 0x0 0x4>;
|
||||
reg-names = "ahci", "sata-ecc";
|
||||
interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
dma-coherent;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb1: usb2@8600000 {
|
||||
compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
|
||||
reg = <0x0 0x8600000 0x0 0x1000>;
|
||||
interrupts = <0 139 0x4>;
|
||||
dr_mode = "host";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
msi: msi-controller1@1572000 {
|
||||
compatible = "fsl,ls1012a-msi";
|
||||
reg = <0x0 0x1572000 0x0 0x8>;
|
||||
msi-controller;
|
||||
interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pcie: pcie@3400000 {
|
||||
compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
||||
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 118 0x4>, /* AER interrupt */
|
||||
<0 117 0x4>; /* PME interrupt */
|
||||
interrupt-names = "aer", "pme";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
num-lanes = <4>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rcpm: rcpm@1ee2000 {
|
||||
compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
|
||||
reg = <0x0 0x1ee2000 0x0 0x1000>;
|
||||
fsl,#rcpm-wakeup-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
pfe_reserved: packetbuffer@83400000 {
|
||||
reg = <0 0x83400000 0 0xc00000>;
|
||||
};
|
||||
};
|
||||
|
||||
pfe: pfe@04000000 {
|
||||
compatible = "fsl,pfe";
|
||||
reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
|
||||
<0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
|
||||
reg-names = "pfe", "pfe-ddr";
|
||||
fsl,pfe-num-interfaces = <0x2>;
|
||||
interrupts = <0 172 0x4>, /* HIF interrupt */
|
||||
<0 173 0x4>, /*HIF_NOCPY interrupt */
|
||||
<0 174 0x4>; /* WoL interrupt */
|
||||
interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
|
||||
memory-region = <&pfe_reserved>;
|
||||
fsl,pfe-scfg = <&scfg 0>;
|
||||
fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "pfe";
|
||||
|
||||
status = "okay";
|
||||
pfe_mac0: ethernet@0 {
|
||||
};
|
||||
|
||||
pfe_mac1: ethernet@1 {
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&thermal_zones {
|
||||
thermal-zone0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,897 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
|
||||
*
|
||||
* Copyright 2014-2015 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Mingkai Hu <Mingkai.hu@freescale.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/thermal/thermal.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
compatible = "fsl,ls1043a";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
aliases {
|
||||
fman0 = &fman0;
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
ethernet2 = &enet2;
|
||||
ethernet3 = &enet3;
|
||||
ethernet4 = &enet4;
|
||||
ethernet5 = &enet5;
|
||||
ethernet6 = &enet6;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/*
|
||||
* We expect the enable-method for cpu's to be "psci", but this
|
||||
* is dependent on the SoC FW, which will fill this in.
|
||||
*
|
||||
* Currently supported enable-method is psci v0.2
|
||||
*/
|
||||
cooling_map0: cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
#cooling-cells = <2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x2>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x3>;
|
||||
clocks = <&clockgen 1 0>;
|
||||
next-level-cache = <&l2>;
|
||||
cpu-idle-states = <&CPU_PH20>;
|
||||
};
|
||||
|
||||
l2: l2-cache {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
idle-states {
|
||||
/*
|
||||
* PSCI node is not added default, U-boot will add missing
|
||||
* parts if it determines to use PSCI.
|
||||
*/
|
||||
entry-method = "arm,psci";
|
||||
|
||||
CPU_PH20: cpu-ph20 {
|
||||
compatible = "arm,idle-state";
|
||||
idle-state-name = "PH20";
|
||||
arm,psci-suspend-param = <0x0>;
|
||||
entry-latency-us = <1000>;
|
||||
exit-latency-us = <1000>;
|
||||
min-residency-us = <3000>;
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0 0x80000000>;
|
||||
/* DRAM space 1, size: 2GiB DRAM */
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
bman_fbpr: bman-fbpr {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x1000000>;
|
||||
alignment = <0 0x1000000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
qman_fqd: qman-fqd {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x400000>;
|
||||
alignment = <0 0x400000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
qman_pfdr: qman-pfdr {
|
||||
compatible = "shared-dma-pool";
|
||||
size = <0 0x2000000>;
|
||||
alignment = <0 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
sysclk: sysclk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
clock-output-names = "sysclk";
|
||||
};
|
||||
|
||||
reboot {
|
||||
compatible ="syscon-reboot";
|
||||
regmap = <&dcfg>;
|
||||
offset = <0xb0>;
|
||||
mask = <0x02>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <1 13 0xf08>, /* Physical Secure PPI */
|
||||
<1 14 0xf08>, /* Physical Non-Secure PPI */
|
||||
<1 11 0xf08>, /* Virtual PPI */
|
||||
<1 10 0xf08>; /* Hypervisor PPI */
|
||||
fsl,erratum-a008585;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <0 106 0x4>,
|
||||
<0 107 0x4>,
|
||||
<0 95 0x4>,
|
||||
<0 97 0x4>;
|
||||
interrupt-affinity = <&cpu0>,
|
||||
<&cpu1>,
|
||||
<&cpu2>,
|
||||
<&cpu3>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1400000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0x0 0x1401000 0 0x1000>, /* GICD */
|
||||
<0x0 0x1402000 0 0x2000>, /* GICC */
|
||||
<0x0 0x1404000 0 0x2000>, /* GICH */
|
||||
<0x0 0x1406000 0 0x2000>; /* GICV */
|
||||
interrupts = <1 9 0xf08>;
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
|
||||
|
||||
clockgen: clocking@1ee1000 {
|
||||
compatible = "fsl,ls1043a-clockgen";
|
||||
reg = <0x0 0x1ee1000 0x0 0x1000>;
|
||||
#clock-cells = <2>;
|
||||
clocks = <&sysclk>;
|
||||
};
|
||||
|
||||
scfg: scfg@1570000 {
|
||||
compatible = "fsl,ls1043a-scfg", "syscon";
|
||||
reg = <0x0 0x1570000 0x0 0x10000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
crypto: crypto@1700000 {
|
||||
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
|
||||
"fsl,sec-v4.0";
|
||||
fsl,sec-era = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x00 0x1700000 0x100000>;
|
||||
reg = <0x00 0x1700000 0x0 0x100000>;
|
||||
interrupts = <0 75 0x4>;
|
||||
|
||||
sec_jr0: jr@10000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x10000 0x10000>;
|
||||
interrupts = <0 71 0x4>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@20000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x20000 0x10000>;
|
||||
interrupts = <0 72 0x4>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@30000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x30000 0x10000>;
|
||||
interrupts = <0 73 0x4>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@40000 {
|
||||
compatible = "fsl,sec-v5.4-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x40000 0x10000>;
|
||||
interrupts = <0 74 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
dcfg: dcfg@1ee0000 {
|
||||
compatible = "fsl,ls1043a-dcfg", "syscon";
|
||||
reg = <0x0 0x1ee0000 0x0 0x1000>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
ifc: ifc@1530000 {
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
reg = <0x0 0x1530000 0x0 0x10000>;
|
||||
big-endian;
|
||||
interrupts = <0 43 0x4>;
|
||||
};
|
||||
|
||||
qspi: quadspi@1550000 {
|
||||
compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x1550000 0x0 0x10000>,
|
||||
<0x0 0x40000000 0x0 0x4000000>;
|
||||
reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
interrupts = <0 99 0x4>;
|
||||
clock-names = "qspi_en", "qspi";
|
||||
clocks = <&clockgen 4 0>, <&clockgen 4 0>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc: esdhc@1560000 {
|
||||
compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
|
||||
reg = <0x0 0x1560000 0x0 0x10000>;
|
||||
interrupts = <0 62 0x4>;
|
||||
clock-frequency = <0>;
|
||||
voltage-ranges = <1800 1800 3300 3300>;
|
||||
sdhci,auto-cmd12;
|
||||
big-endian;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
ddr: memory-controller@1080000 {
|
||||
compatible = "fsl,qoriq-memory-controller";
|
||||
reg = <0x0 0x1080000 0x0 0x1000>;
|
||||
interrupts = <0 144 0x4>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
tmu: tmu@1f00000 {
|
||||
compatible = "fsl,qoriq-tmu";
|
||||
reg = <0x0 0x1f00000 0x0 0x10000>;
|
||||
interrupts = <0 33 0x4>;
|
||||
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
|
||||
fsl,tmu-calibration = <0x00000000 0x00000026
|
||||
0x00000001 0x0000002d
|
||||
0x00000002 0x00000032
|
||||
0x00000003 0x00000039
|
||||
0x00000004 0x0000003f
|
||||
0x00000005 0x00000046
|
||||
0x00000006 0x0000004d
|
||||
0x00000007 0x00000054
|
||||
0x00000008 0x0000005a
|
||||
0x00000009 0x00000061
|
||||
0x0000000a 0x0000006a
|
||||
0x0000000b 0x00000071
|
||||
|
||||
0x00010000 0x00000025
|
||||
0x00010001 0x0000002c
|
||||
0x00010002 0x00000035
|
||||
0x00010003 0x0000003d
|
||||
0x00010004 0x00000045
|
||||
0x00010005 0x0000004e
|
||||
0x00010006 0x00000057
|
||||
0x00010007 0x00000061
|
||||
0x00010008 0x0000006b
|
||||
0x00010009 0x00000076
|
||||
|
||||
0x00020000 0x00000029
|
||||
0x00020001 0x00000033
|
||||
0x00020002 0x0000003d
|
||||
0x00020003 0x00000049
|
||||
0x00020004 0x00000056
|
||||
0x00020005 0x00000061
|
||||
0x00020006 0x0000006d
|
||||
|
||||
0x00030000 0x00000021
|
||||
0x00030001 0x0000002a
|
||||
0x00030002 0x0000003c
|
||||
0x00030003 0x0000004e>;
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
#include "fsl-tmu.dtsi"
|
||||
|
||||
qman: qman@1880000 {
|
||||
compatible = "fsl,qman";
|
||||
reg = <0x0 0x1880000 0x0 0x10000>;
|
||||
interrupts = <0 45 0x4>;
|
||||
memory-region = <&qman_fqd &qman_pfdr>;
|
||||
};
|
||||
|
||||
bman: bman@1890000 {
|
||||
compatible = "fsl,bman";
|
||||
reg = <0x0 0x1890000 0x0 0x10000>;
|
||||
interrupts = <0 45 0x4>;
|
||||
memory-region = <&bman_fbpr>;
|
||||
};
|
||||
|
||||
bportals: bman-portals@508000000 {
|
||||
ranges = <0x0 0x5 0x08000000 0x8000000>;
|
||||
};
|
||||
|
||||
qportals: qman-portals@500000000 {
|
||||
ranges = <0x0 0x5 0x00000000 0x8000000>;
|
||||
};
|
||||
|
||||
dspi0: dspi@2100000 {
|
||||
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2100000 0x0 0x10000>;
|
||||
interrupts = <0 64 0x4>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 0>;
|
||||
spi-num-chipselects = <5>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dspi1: dspi@2110000 {
|
||||
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2110000 0x0 0x10000>;
|
||||
interrupts = <0 65 0x4>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 0>;
|
||||
spi-num-chipselects = <5>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@2180000 {
|
||||
compatible = "fsl,vf610-i2c", "fsl,ls1043a-vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2180000 0x0 0x10000>;
|
||||
interrupts = <0 56 0x4>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 0>;
|
||||
dmas = <&edma0 1 39>,
|
||||
<&edma0 1 38>;
|
||||
dma-names = "tx", "rx";
|
||||
scl-gpios = <&gpio4 12 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@2190000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x2190000 0x0 0x10000>;
|
||||
interrupts = <0 57 0x4>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@21a0000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x21a0000 0x0 0x10000>;
|
||||
interrupts = <0 58 0x4>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c3: i2c@21b0000 {
|
||||
compatible = "fsl,vf610-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0 0x21b0000 0x0 0x10000>;
|
||||
interrupts = <0 59 0x4>;
|
||||
clock-names = "i2c";
|
||||
clocks = <&clockgen 4 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
duart0: serial@21c0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0500 0x0 0x100>;
|
||||
interrupts = <0 54 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
};
|
||||
|
||||
duart1: serial@21c0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x00 0x21c0600 0x0 0x100>;
|
||||
interrupts = <0 54 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
};
|
||||
|
||||
duart2: serial@21d0500 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0500 0x0 0x100>;
|
||||
interrupts = <0 55 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
};
|
||||
|
||||
duart3: serial@21d0600 {
|
||||
compatible = "fsl,ns16550", "ns16550a";
|
||||
reg = <0x0 0x21d0600 0x0 0x100>;
|
||||
interrupts = <0 55 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
};
|
||||
|
||||
gpio1: gpio@2300000 {
|
||||
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2300000 0x0 0x10000>;
|
||||
interrupts = <0 66 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio@2310000 {
|
||||
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2310000 0x0 0x10000>;
|
||||
interrupts = <0 67 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio@2320000 {
|
||||
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2320000 0x0 0x10000>;
|
||||
interrupts = <0 68 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio4: gpio@2330000 {
|
||||
compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
|
||||
reg = <0x0 0x2330000 0x0 0x10000>;
|
||||
interrupts = <0 134 0x4>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
sys {
|
||||
label = "sys";
|
||||
gpios = <&gpio4 12 1>;
|
||||
linux,default-trigger = "timer";
|
||||
};
|
||||
|
||||
lte_0 {
|
||||
label = "lte_0";
|
||||
gpios = <&gpio4 11 1>;
|
||||
};
|
||||
|
||||
lte_1 {
|
||||
label = "lte_1";
|
||||
gpios = <&gpio4 10 1>;
|
||||
};
|
||||
|
||||
lte_2 {
|
||||
label = "lte_2";
|
||||
gpios = <&gpio1 22 1>;
|
||||
};
|
||||
|
||||
wifi {
|
||||
label = "wifi";
|
||||
gpios = <&gpio4 13 1>;
|
||||
};
|
||||
|
||||
cloud {
|
||||
label = "cloud";
|
||||
gpios = <&gpio1 16 1>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys-polled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
poll-interval = <20>;
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&gpio1 21 1>;
|
||||
linux,code = <0x198>;
|
||||
};
|
||||
};
|
||||
|
||||
uqe: uqe@2400000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "qe";
|
||||
compatible = "fsl,qe", "simple-bus";
|
||||
ranges = <0x0 0x0 0x2400000 0x40000>;
|
||||
reg = <0x0 0x2400000 0x0 0x480>;
|
||||
brg-frequency = <100000000>;
|
||||
bus-frequency = <200000000>;
|
||||
|
||||
fsl,qe-num-riscs = <1>;
|
||||
fsl,qe-num-snums = <28>;
|
||||
|
||||
qeic: qeic@80 {
|
||||
compatible = "fsl,qe-ic";
|
||||
reg = <0x80 0x80>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <0 77 0x04 0 77 0x04>;
|
||||
};
|
||||
|
||||
si1: si@700 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,ls1043-qe-si",
|
||||
"fsl,t1040-qe-si";
|
||||
reg = <0x700 0x80>;
|
||||
};
|
||||
|
||||
siram1: siram@1000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ls1043-qe-siram",
|
||||
"fsl,t1040-qe-siram";
|
||||
reg = <0x1000 0x800>;
|
||||
};
|
||||
|
||||
ucc@2000 {
|
||||
cell-index = <1>;
|
||||
reg = <0x2000 0x200>;
|
||||
interrupts = <32>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
ucc@2200 {
|
||||
cell-index = <3>;
|
||||
reg = <0x2200 0x200>;
|
||||
interrupts = <34>;
|
||||
interrupt-parent = <&qeic>;
|
||||
};
|
||||
|
||||
muram@10000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,qe-muram", "fsl,cpm-muram";
|
||||
ranges = <0x0 0x10000 0x6000>;
|
||||
|
||||
data-only@0 {
|
||||
compatible = "fsl,qe-muram-data",
|
||||
"fsl,cpm-muram-data";
|
||||
reg = <0x0 0x6000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
lpuart0: serial@2950000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2950000 0x0 0x1000>;
|
||||
interrupts = <0 48 0x4>;
|
||||
clocks = <&clockgen 0 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart1: serial@2960000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2960000 0x0 0x1000>;
|
||||
interrupts = <0 49 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart2: serial@2970000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2970000 0x0 0x1000>;
|
||||
interrupts = <0 50 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart3: serial@2980000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2980000 0x0 0x1000>;
|
||||
interrupts = <0 51 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart4: serial@2990000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x2990000 0x0 0x1000>;
|
||||
interrupts = <0 52 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lpuart5: serial@29a0000 {
|
||||
compatible = "fsl,ls1021a-lpuart";
|
||||
reg = <0x0 0x29a0000 0x0 0x1000>;
|
||||
interrupts = <0 53 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "ipg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ftm0: ftm0@29d0000 {
|
||||
compatible = "fsl,ls1043a-ftm-alarm";
|
||||
reg = <0x0 0x29d0000 0x0 0x10000>,
|
||||
<0x0 0x1ee2140 0x0 0x4>;
|
||||
reg-names = "ftm", "pmctrl";
|
||||
interrupts = <0 86 0x4>;
|
||||
big-endian;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
wdog0: wdog@2ad0000 {
|
||||
compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x0 0x2ad0000 0x0 0x10000>;
|
||||
interrupts = <0 83 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
clock-names = "wdog";
|
||||
big-endian;
|
||||
};
|
||||
|
||||
edma0: edma@2c00000 {
|
||||
#dma-cells = <2>;
|
||||
compatible = "fsl,vf610-edma";
|
||||
reg = <0x0 0x2c00000 0x0 0x10000>,
|
||||
<0x0 0x2c10000 0x0 0x10000>,
|
||||
<0x0 0x2c20000 0x0 0x10000>;
|
||||
interrupts = <0 103 0x4>,
|
||||
<0 103 0x4>;
|
||||
interrupt-names = "edma-tx", "edma-err";
|
||||
dma-channels = <32>;
|
||||
big-endian;
|
||||
clock-names = "dmamux0", "dmamux1";
|
||||
clocks = <&clockgen 4 0>,
|
||||
<&clockgen 4 0>;
|
||||
};
|
||||
|
||||
usb0: usb3@2f00000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x2f00000 0x0 0x10000>;
|
||||
interrupts = <0 60 0x4>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
usb1: usb3@3000000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3000000 0x0 0x10000>;
|
||||
interrupts = <0 61 0x4>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
usb2: usb3@3100000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0x3100000 0x0 0x10000>;
|
||||
interrupts = <0 63 0x4>;
|
||||
dr_mode = "host";
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
snps,dis_rxdet_inp3_quirk;
|
||||
usb3-lpm-capable;
|
||||
snps,dis-u1u2-when-u3-quirk;
|
||||
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
||||
};
|
||||
|
||||
sata: sata@3200000 {
|
||||
compatible = "fsl,ls1043a-ahci";
|
||||
reg = <0x0 0x3200000 0x0 0x10000>,
|
||||
<0x0 0x20140520 0x0 0x4>;
|
||||
reg-names = "ahci", "sata-ecc";
|
||||
interrupts = <0 69 0x4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
qdma: qdma@8380000 {
|
||||
compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
|
||||
reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
|
||||
<0x0 0x8390000 0x0 0x10000>, /* Status regs */
|
||||
<0x0 0x83a0000 0x0 0x40000>; /* Block regs */
|
||||
interrupts = <0 152 0x4>,
|
||||
<0 39 0x4>,
|
||||
<0 40 0x4>,
|
||||
<0 41 0x4>,
|
||||
<0 42 0x4>;
|
||||
interrupt-names = "qdma-error", "qdma-queue0",
|
||||
"qdma-queue1", "qdma-queue2", "qdma-queue3";
|
||||
channels = <8>;
|
||||
block-number = <1>;
|
||||
block-offset = <0x10000>;
|
||||
queues = <2>;
|
||||
status-sizes = <64>;
|
||||
queue-sizes = <64 64>;
|
||||
big-endian;
|
||||
};
|
||||
|
||||
msi1: msi-controller1@1571000 {
|
||||
compatible = "fsl,ls1043a-msi";
|
||||
reg = <0x0 0x1571000 0x0 0x8>;
|
||||
msi-controller;
|
||||
interrupts = <0 116 0x4>;
|
||||
};
|
||||
|
||||
msi2: msi-controller2@1572000 {
|
||||
compatible = "fsl,ls1043a-msi";
|
||||
reg = <0x0 0x1572000 0x0 0x8>;
|
||||
msi-controller;
|
||||
interrupts = <0 126 0x4>;
|
||||
};
|
||||
|
||||
msi3: msi-controller3@1573000 {
|
||||
compatible = "fsl,ls1043a-msi";
|
||||
reg = <0x0 0x1573000 0x0 0x8>;
|
||||
msi-controller;
|
||||
interrupts = <0 160 0x4>;
|
||||
};
|
||||
|
||||
pcie@3400000 {
|
||||
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
||||
0x40 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 117 0x4>, /* PME interrupt */
|
||||
<0 118 0x4>; /* aer interrupt */
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <4>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
|
||||
<0000 0 0 2 &gic 0 111 0x4>,
|
||||
<0000 0 0 3 &gic 0 112 0x4>,
|
||||
<0000 0 0 4 &gic 0 113 0x4>;
|
||||
};
|
||||
|
||||
pcie@3500000 {
|
||||
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
||||
0x48 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 127 0x4>,
|
||||
<0 128 0x4>;
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
|
||||
<0000 0 0 2 &gic 0 121 0x4>,
|
||||
<0000 0 0 3 &gic 0 122 0x4>,
|
||||
<0000 0 0 4 &gic 0 123 0x4>;
|
||||
};
|
||||
|
||||
pcie@3600000 {
|
||||
compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
|
||||
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
||||
0x50 0x00000000 0x0 0x00002000>; /* configuration space */
|
||||
reg-names = "regs", "config";
|
||||
interrupts = <0 161 0x4>,
|
||||
<0 162 0x4>;
|
||||
interrupt-names = "pme", "aer";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
dma-coherent;
|
||||
num-lanes = <2>;
|
||||
bus-range = <0x0 0xff>;
|
||||
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
|
||||
0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
||||
msi-parent = <&msi1>, <&msi2>, <&msi3>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
|
||||
<0000 0 0 2 &gic 0 155 0x4>,
|
||||
<0000 0 0 3 &gic 0 156 0x4>,
|
||||
<0000 0 0 4 &gic 0 157 0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
#include "qoriq-qman-portals.dtsi"
|
||||
#include "qoriq-bman-portals.dtsi"
|
||||
|
||||
&thermal_zones {
|
||||
thermal-zone0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
thermal-zone5 {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* QorIQ BMan SDK Portals device tree nodes
|
||||
*
|
||||
* Copyright 2011-2016 Freescale Semiconductor Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
*/
|
||||
|
||||
&bportals {
|
||||
bman-portal@0 {
|
||||
cell-index = <0>;
|
||||
};
|
||||
|
||||
bman-portal@10000 {
|
||||
cell-index = <1>;
|
||||
};
|
||||
|
||||
bman-portal@20000 {
|
||||
cell-index = <2>;
|
||||
};
|
||||
|
||||
bman-portal@30000 {
|
||||
cell-index = <3>;
|
||||
};
|
||||
|
||||
bman-portal@40000 {
|
||||
cell-index = <4>;
|
||||
};
|
||||
|
||||
bman-portal@50000 {
|
||||
cell-index = <5>;
|
||||
};
|
||||
|
||||
bman-portal@60000 {
|
||||
cell-index = <6>;
|
||||
};
|
||||
|
||||
bman-portal@70000 {
|
||||
cell-index = <7>;
|
||||
};
|
||||
|
||||
bman-portal@80000 {
|
||||
cell-index = <8>;
|
||||
};
|
||||
|
||||
bman-portal@90000 {
|
||||
cell-index = <9>;
|
||||
};
|
||||
|
||||
bman-bpids@0 {
|
||||
compatible = "fsl,bpid-range";
|
||||
fsl,bpid-range = <32 32>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* QorIQ BMan Portals device tree
|
||||
*
|
||||
* Copyright 2011-2016 Freescale Semiconductor Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
&bportals {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
bman-portal@0 {
|
||||
/*
|
||||
* bootloader fix-ups are expected to provide the
|
||||
* "fsl,bman-portal-<hardware revision>" compatible
|
||||
*/
|
||||
compatible = "fsl,bman-portal";
|
||||
reg = <0x0 0x4000>, <0x4000000 0x4000>;
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
bman-portal@10000 {
|
||||
compatible = "fsl,bman-portal";
|
||||
reg = <0x10000 0x4000>, <0x4010000 0x4000>;
|
||||
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
bman-portal@20000 {
|
||||
compatible = "fsl,bman-portal";
|
||||
reg = <0x20000 0x4000>, <0x4020000 0x4000>;
|
||||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
bman-portal@30000 {
|
||||
compatible = "fsl,bman-portal";
|
||||
reg = <0x30000 0x4000>, <0x4030000 0x4000>;
|
||||
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
bman-portal@40000 {
|
||||
compatible = "fsl,bman-portal";
|
||||
reg = <0x40000 0x4000>, <0x4040000 0x4000>;
|
||||
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
bman-portal@50000 {
|
||||
compatible = "fsl,bman-portal";
|
||||
reg = <0x50000 0x4000>, <0x4050000 0x4000>;
|
||||
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
bman-portal@60000 {
|
||||
compatible = "fsl,bman-portal";
|
||||
reg = <0x60000 0x4000>, <0x4060000 0x4000>;
|
||||
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
bman-portal@70000 {
|
||||
compatible = "fsl,bman-portal";
|
||||
reg = <0x70000 0x4000>, <0x4070000 0x4000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
bman-portal@80000 {
|
||||
compatible = "fsl,bman-portal";
|
||||
reg = <0x80000 0x4000>, <0x4080000 0x4000>;
|
||||
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
bman-portal@90000 {
|
||||
compatible = "fsl,bman-portal";
|
||||
reg = <0x90000 0x4000>, <0x4090000 0x4000>;
|
||||
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,97 @@
|
|||
/*
|
||||
* QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
|
||||
*
|
||||
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
fsldpaa: fsl,dpaa {
|
||||
compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa";
|
||||
ethernet@0 {
|
||||
compatible = "fsl,dpa-ethernet";
|
||||
fsl,fman-mac = <&enet0>;
|
||||
dma-coherent;
|
||||
};
|
||||
ethernet@1 {
|
||||
compatible = "fsl,dpa-ethernet";
|
||||
fsl,fman-mac = <&enet1>;
|
||||
dma-coherent;
|
||||
};
|
||||
ethernet@2 {
|
||||
compatible = "fsl,dpa-ethernet";
|
||||
fsl,fman-mac = <&enet2>;
|
||||
dma-coherent;
|
||||
};
|
||||
ethernet@3 {
|
||||
compatible = "fsl,dpa-ethernet";
|
||||
fsl,fman-mac = <&enet3>;
|
||||
dma-coherent;
|
||||
};
|
||||
ethernet@4 {
|
||||
compatible = "fsl,dpa-ethernet";
|
||||
fsl,fman-mac = <&enet4>;
|
||||
dma-coherent;
|
||||
};
|
||||
ethernet@5 {
|
||||
compatible = "fsl,dpa-ethernet";
|
||||
fsl,fman-mac = <&enet5>;
|
||||
dma-coherent;
|
||||
};
|
||||
ethernet@8 {
|
||||
compatible = "fsl,dpa-ethernet";
|
||||
fsl,fman-mac = <&enet6>;
|
||||
dma-coherent;
|
||||
};
|
||||
ethernet@6 {
|
||||
compatible = "fsl,im-ethernet";
|
||||
fsl,fman-mac = <&enet2>;
|
||||
dma-coherent;
|
||||
fpmevt-sel = <0>;
|
||||
};
|
||||
ethernet@7 {
|
||||
compatible = "fsl,im-ethernet";
|
||||
fsl,fman-mac = <&enet3>;
|
||||
dma-coherent;
|
||||
fpmevt-sel = <1>;
|
||||
};
|
||||
ethernet@10 {
|
||||
compatible = "fsl,im-ethernet";
|
||||
fsl,fman-mac = <&enet4>;
|
||||
dma-coherent;
|
||||
fpmevt-sel = <2>;
|
||||
};
|
||||
ethernet@11 {
|
||||
compatible = "fsl,im-ethernet";
|
||||
fsl,fman-mac = <&enet5>;
|
||||
dma-coherent;
|
||||
fpmevt-sel = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* QorIQ FMan v3 10g port #0 device tree
|
||||
*
|
||||
* Copyright 2012-2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
fman@1a00000 {
|
||||
fman0_rx_0x10: port@90000 {
|
||||
cell-index = <0x10>;
|
||||
compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
|
||||
reg = <0x90000 0x1000>;
|
||||
fsl,fman-10g-port;
|
||||
};
|
||||
|
||||
fman0_tx_0x30: port@b0000 {
|
||||
cell-index = <0x30>;
|
||||
compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
|
||||
reg = <0xb0000 0x1000>;
|
||||
fsl,fman-10g-port;
|
||||
fsl,qman-channel-id = <0x800>;
|
||||
};
|
||||
|
||||
mac9: ethernet@f0000 {
|
||||
cell-index = <0x8>;
|
||||
compatible = "fsl,fman-memac";
|
||||
reg = <0xf0000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
|
||||
pcsphy-handle = <&pcsphy6>;
|
||||
};
|
||||
|
||||
mdio9: mdio@f1000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xf1000 0x1000>;
|
||||
|
||||
pcsphy6: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* QorIQ FMan v3 10g port #1 device tree
|
||||
*
|
||||
* Copyright 2012-2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
fman@1a00000 {
|
||||
fman0_rx_0x11: port@91000 {
|
||||
cell-index = <0x11>;
|
||||
compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
|
||||
reg = <0x91000 0x1000>;
|
||||
fsl,fman-10g-port;
|
||||
};
|
||||
|
||||
fman0_tx_0x31: port@b1000 {
|
||||
cell-index = <0x31>;
|
||||
compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
|
||||
reg = <0xb1000 0x1000>;
|
||||
fsl,fman-10g-port;
|
||||
fsl,qman-channel-id = <0x801>;
|
||||
};
|
||||
|
||||
mac10: ethernet@f2000 {
|
||||
cell-index = <0x9>;
|
||||
compatible = "fsl,fman-memac";
|
||||
reg = <0xf2000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
|
||||
pcsphy-handle = <&pcsphy7>;
|
||||
};
|
||||
|
||||
mdio10: mdio@f3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xf3000 0x1000>;
|
||||
|
||||
pcsphy7: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* QorIQ FMan v3 1g port #0 device tree
|
||||
*
|
||||
* Copyright 2012-2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
fman@1a00000 {
|
||||
fman0_rx_0x08: port@88000 {
|
||||
cell-index = <0x8>;
|
||||
compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
|
||||
reg = <0x88000 0x1000>;
|
||||
};
|
||||
|
||||
fman0_tx_0x28: port@a8000 {
|
||||
cell-index = <0x28>;
|
||||
compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
|
||||
reg = <0xa8000 0x1000>;
|
||||
fsl,qman-channel-id = <0x802>;
|
||||
};
|
||||
|
||||
ethernet@e0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,fman-memac";
|
||||
reg = <0xe0000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
|
||||
ptp-timer = <&ptp_timer0>;
|
||||
pcsphy-handle = <&pcsphy0>;
|
||||
};
|
||||
|
||||
mdio@e1000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe1000 0x1000>;
|
||||
|
||||
pcsphy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* QorIQ FMan v3 1g port #1 device tree
|
||||
*
|
||||
* Copyright 2012-2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
fman@1a00000 {
|
||||
fman0_rx_0x09: port@89000 {
|
||||
cell-index = <0x9>;
|
||||
compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
|
||||
reg = <0x89000 0x1000>;
|
||||
};
|
||||
|
||||
fman0_tx_0x29: port@a9000 {
|
||||
cell-index = <0x29>;
|
||||
compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
|
||||
reg = <0xa9000 0x1000>;
|
||||
fsl,qman-channel-id = <0x803>;
|
||||
};
|
||||
|
||||
ethernet@e2000 {
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,fman-memac";
|
||||
reg = <0xe2000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
|
||||
ptp-timer = <&ptp_timer0>;
|
||||
pcsphy-handle = <&pcsphy1>;
|
||||
};
|
||||
|
||||
mdio@e3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe3000 0x1000>;
|
||||
|
||||
pcsphy1: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* QorIQ FMan v3 1g port #2 device tree
|
||||
*
|
||||
* Copyright 2012-2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
fman@1a00000 {
|
||||
fman0_rx_0x0a: port@8a000 {
|
||||
cell-index = <0xa>;
|
||||
compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
|
||||
reg = <0x8a000 0x1000>;
|
||||
};
|
||||
|
||||
fman0_tx_0x2a: port@aa000 {
|
||||
cell-index = <0x2a>;
|
||||
compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
|
||||
reg = <0xaa000 0x1000>;
|
||||
fsl,qman-channel-id = <0x804>;
|
||||
};
|
||||
|
||||
ethernet@e4000 {
|
||||
cell-index = <2>;
|
||||
compatible = "fsl,fman-memac";
|
||||
reg = <0xe4000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
|
||||
ptp-timer = <&ptp_timer0>;
|
||||
pcsphy-handle = <&pcsphy2>;
|
||||
};
|
||||
|
||||
mdio@e5000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe5000 0x1000>;
|
||||
|
||||
pcsphy2: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* QorIQ FMan v3 1g port #3 device tree
|
||||
*
|
||||
* Copyright 2012-2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
fman@1a00000 {
|
||||
fman0_rx_0x0b: port@8b000 {
|
||||
cell-index = <0xb>;
|
||||
compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
|
||||
reg = <0x8b000 0x1000>;
|
||||
};
|
||||
|
||||
fman0_tx_0x2b: port@ab000 {
|
||||
cell-index = <0x2b>;
|
||||
compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
|
||||
reg = <0xab000 0x1000>;
|
||||
fsl,qman-channel-id = <0x805>;
|
||||
};
|
||||
|
||||
ethernet@e6000 {
|
||||
cell-index = <3>;
|
||||
compatible = "fsl,fman-memac";
|
||||
reg = <0xe6000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
|
||||
ptp-timer = <&ptp_timer0>;
|
||||
pcsphy-handle = <&pcsphy3>;
|
||||
};
|
||||
|
||||
mdio@e7000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe7000 0x1000>;
|
||||
|
||||
pcsphy3: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* QorIQ FMan v3 1g port #4 device tree
|
||||
*
|
||||
* Copyright 2012-2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
fman@1a00000 {
|
||||
fman0_rx_0x0c: port@8c000 {
|
||||
cell-index = <0xc>;
|
||||
compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
|
||||
reg = <0x8c000 0x1000>;
|
||||
};
|
||||
|
||||
fman0_tx_0x2c: port@ac000 {
|
||||
cell-index = <0x2c>;
|
||||
compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
|
||||
reg = <0xac000 0x1000>;
|
||||
fsl,qman-channel-id = <0x806>;
|
||||
};
|
||||
|
||||
ethernet@e8000 {
|
||||
cell-index = <4>;
|
||||
compatible = "fsl,fman-memac";
|
||||
reg = <0xe8000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
|
||||
ptp-timer = <&ptp_timer0>;
|
||||
pcsphy-handle = <&pcsphy4>;
|
||||
};
|
||||
|
||||
mdio@e9000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xe9000 0x1000>;
|
||||
|
||||
pcsphy4: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* QorIQ FMan v3 1g port #5 device tree
|
||||
*
|
||||
* Copyright 2012-2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
fman@1a00000 {
|
||||
fman0_rx_0x0d: port@8d000 {
|
||||
cell-index = <0xd>;
|
||||
compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
|
||||
reg = <0x8d000 0x1000>;
|
||||
};
|
||||
|
||||
fman0_tx_0x2d: port@ad000 {
|
||||
cell-index = <0x2d>;
|
||||
compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
|
||||
reg = <0xad000 0x1000>;
|
||||
fsl,qman-channel-id = <0x807>;
|
||||
};
|
||||
|
||||
ethernet@ea000 {
|
||||
cell-index = <5>;
|
||||
compatible = "fsl,fman-memac";
|
||||
reg = <0xea000 0x1000>;
|
||||
fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
|
||||
ptp-timer = <&ptp_timer0>;
|
||||
pcsphy-handle = <&pcsphy5>;
|
||||
};
|
||||
|
||||
mdio@eb000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xeb000 0x1000>;
|
||||
|
||||
pcsphy5: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* QorIQ FMan v3 OH ports device tree
|
||||
*
|
||||
* Copyright 2012-2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
*/
|
||||
|
||||
fman@1a00000 {
|
||||
|
||||
fman0_oh1: port@82000 {
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,fman-port-oh";
|
||||
reg = <0x82000 0x1000>;
|
||||
};
|
||||
|
||||
fman0_oh2: port@83000 {
|
||||
cell-index = <1>;
|
||||
compatible = "fsl,fman-port-oh";
|
||||
reg = <0x83000 0x1000>;
|
||||
};
|
||||
|
||||
fman0_oh3: port@84000 {
|
||||
cell-index = <2>;
|
||||
compatible = "fsl,fman-port-oh";
|
||||
reg = <0x84000 0x1000>;
|
||||
};
|
||||
|
||||
fman0_oh4: port@85000 {
|
||||
cell-index = <3>;
|
||||
compatible = "fsl,fman-port-oh";
|
||||
reg = <0x85000 0x1000>;
|
||||
};
|
||||
|
||||
fman0_oh5: port@86000 {
|
||||
cell-index = <4>;
|
||||
compatible = "fsl,fman-port-oh";
|
||||
reg = <0x86000 0x1000>;
|
||||
};
|
||||
|
||||
fman0_oh6: port@87000 {
|
||||
cell-index = <5>;
|
||||
compatible = "fsl,fman-port-oh";
|
||||
reg = <0x87000 0x1000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* QorIQ FMan v3 device tree
|
||||
*
|
||||
* Copyright 2012-2015 Freescale Semiconductor Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
fman0: fman@1a00000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <0>;
|
||||
compatible = "fsl,fman";
|
||||
ranges = <0x0 0x0 0x1a00000 0xfe000>;
|
||||
reg = <0x0 0x1a00000 0x0 0xfe000>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 3 0>;
|
||||
clock-names = "fmanclk";
|
||||
fsl,qman-channel-range = <0x800 0x10>;
|
||||
ptimer-handle = <&ptp_timer0>;
|
||||
|
||||
cc {
|
||||
compatible = "fsl,fman-cc";
|
||||
};
|
||||
|
||||
muram@0 {
|
||||
compatible = "fsl,fman-muram";
|
||||
reg = <0x0 0x60000>;
|
||||
};
|
||||
|
||||
bmi@80000 {
|
||||
compatible = "fsl,fman-bmi";
|
||||
reg = <0x80000 0x400>;
|
||||
};
|
||||
|
||||
qmi@80400 {
|
||||
compatible = "fsl,fman-qmi";
|
||||
reg = <0x80400 0x400>;
|
||||
};
|
||||
|
||||
fman0_oh_0x2: port@82000 {
|
||||
cell-index = <0x2>;
|
||||
compatible = "fsl,fman-v3-port-oh";
|
||||
reg = <0x82000 0x1000>;
|
||||
fsl,qman-channel-id = <0x809>;
|
||||
};
|
||||
|
||||
fman0_oh_0x3: port@83000 {
|
||||
cell-index = <0x3>;
|
||||
compatible = "fsl,fman-v3-port-oh";
|
||||
reg = <0x83000 0x1000>;
|
||||
fsl,qman-channel-id = <0x80a>;
|
||||
};
|
||||
|
||||
fman0_oh_0x4: port@84000 {
|
||||
cell-index = <0x4>;
|
||||
compatible = "fsl,fman-v3-port-oh";
|
||||
reg = <0x84000 0x1000>;
|
||||
fsl,qman-channel-id = <0x80b>;
|
||||
};
|
||||
|
||||
fman0_oh_0x5: port@85000 {
|
||||
cell-index = <0x5>;
|
||||
compatible = "fsl,fman-v3-port-oh";
|
||||
reg = <0x85000 0x1000>;
|
||||
fsl,qman-channel-id = <0x80c>;
|
||||
};
|
||||
|
||||
fman0_oh_0x6: port@86000 {
|
||||
cell-index = <0x6>;
|
||||
compatible = "fsl,fman-v3-port-oh";
|
||||
reg = <0x86000 0x1000>;
|
||||
fsl,qman-channel-id = <0x80d>;
|
||||
};
|
||||
|
||||
fman0_oh_0x7: port@87000 {
|
||||
cell-index = <0x7>;
|
||||
compatible = "fsl,fman-v3-port-oh";
|
||||
reg = <0x87000 0x1000>;
|
||||
fsl,qman-channel-id = <0x80e>;
|
||||
};
|
||||
|
||||
policer@c0000 {
|
||||
compatible = "fsl,fman-policer";
|
||||
reg = <0xc0000 0x1000>;
|
||||
};
|
||||
|
||||
keygen@c1000 {
|
||||
compatible = "fsl,fman-keygen";
|
||||
reg = <0xc1000 0x1000>;
|
||||
};
|
||||
|
||||
dma@c2000 {
|
||||
compatible = "fsl,fman-dma";
|
||||
reg = <0xc2000 0x1000>;
|
||||
};
|
||||
|
||||
fpm@c3000 {
|
||||
compatible = "fsl,fman-fpm";
|
||||
reg = <0xc3000 0x1000>;
|
||||
};
|
||||
|
||||
parser@c7000 {
|
||||
compatible = "fsl,fman-parser";
|
||||
reg = <0xc7000 0x1000>;
|
||||
};
|
||||
|
||||
vsps@dc000 {
|
||||
compatible = "fsl,fman-vsps";
|
||||
reg = <0xdc000 0x1000>;
|
||||
};
|
||||
|
||||
mdio0: mdio@fc000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xfc000 0x1000>;
|
||||
};
|
||||
|
||||
xmdio0: mdio@fd000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
|
||||
reg = <0xfd000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
ptp_timer0: ptp-timer@1afe000 {
|
||||
compatible = "fsl,fman-ptp-timer";
|
||||
reg = <0x0 0x1afe000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clockgen 3 0>;
|
||||
};
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* QorIQ QMan SDK Portals device tree nodes
|
||||
*
|
||||
* Copyright 2011-2016 Freescale Semiconductor Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
*/
|
||||
|
||||
&qportals {
|
||||
qman-fqids@0 {
|
||||
compatible = "fsl,fqid-range";
|
||||
fsl,fqid-range = <256 256>;
|
||||
};
|
||||
|
||||
qman-fqids@1 {
|
||||
compatible = "fsl,fqid-range";
|
||||
fsl,fqid-range = <32768 32768>;
|
||||
};
|
||||
|
||||
qman-pools@0 {
|
||||
compatible = "fsl,pool-channel-range";
|
||||
fsl,pool-channel-range = <0x401 0xf>;
|
||||
};
|
||||
|
||||
qman-cgrids@0 {
|
||||
compatible = "fsl,cgrid-range";
|
||||
fsl,cgrid-range = <0 256>;
|
||||
};
|
||||
|
||||
qman-ceetm@0 {
|
||||
compatible = "fsl,qman-ceetm";
|
||||
fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
|
||||
fsl,ceetm-sp-range = <0 16>;
|
||||
fsl,ceetm-lni-range = <0 8>;
|
||||
fsl,ceetm-channel-range = <0 32>;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* QorIQ QMan Portals device tree
|
||||
*
|
||||
* Copyright 2011-2016 Freescale Semiconductor Inc.
|
||||
*
|
||||
*/
|
||||
|
||||
&qportals {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
qportal0: qman-portal@0 {
|
||||
/*
|
||||
* bootloader fix-ups are expected to provide the
|
||||
* "fsl,bman-portal-<hardware revision>" compatible
|
||||
*/
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x0 0x4000>, <0x4000000 0x4000>;
|
||||
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cell-index = <0>;
|
||||
};
|
||||
|
||||
qportal1: qman-portal@10000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x10000 0x4000>, <0x4010000 0x4000>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cell-index = <1>;
|
||||
};
|
||||
|
||||
qportal2: qman-portal@20000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x20000 0x4000>, <0x4020000 0x4000>;
|
||||
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cell-index = <2>;
|
||||
};
|
||||
|
||||
qportal3: qman-portal@30000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x30000 0x4000>, <0x4030000 0x4000>;
|
||||
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cell-index = <3>;
|
||||
};
|
||||
|
||||
qportal4: qman-portal@40000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x40000 0x4000>, <0x4040000 0x4000>;
|
||||
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cell-index = <4>;
|
||||
};
|
||||
|
||||
qportal5: qman-portal@50000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x50000 0x4000>, <0x4050000 0x4000>;
|
||||
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cell-index = <5>;
|
||||
};
|
||||
|
||||
qportal6: qman-portal@60000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x60000 0x4000>, <0x4060000 0x4000>;
|
||||
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cell-index = <6>;
|
||||
};
|
||||
|
||||
qportal7: qman-portal@70000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x70000 0x4000>, <0x4070000 0x4000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cell-index = <7>;
|
||||
};
|
||||
|
||||
qportal8: qman-portal@80000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x80000 0x4000>, <0x4080000 0x4000>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cell-index = <8>;
|
||||
};
|
||||
|
||||
qportal9: qman-portal@90000 {
|
||||
compatible = "fsl,qman-portal";
|
||||
reg = <0x90000 0x4000>, <0x4090000 0x4000>;
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cell-index = <9>;
|
||||
};
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,109 @@
|
|||
#uio
|
||||
CONFIG_UIO=y
|
||||
CONFIG_UIO_CIF=y
|
||||
CONFIG_UIO_PDRV_GENIRQ=y
|
||||
CONFIG_UIO_DMEM_GENIRQ=y
|
||||
CONFIG_UIO_AEC=y
|
||||
CONFIG_UIO_SERCOS3=y
|
||||
CONFIG_UIO_PCI_GENERIC=y
|
||||
CONFIG_UIO_NETX=y
|
||||
CONFIG_UIO_MF624=y
|
||||
# general options
|
||||
CONFIG_LOCALVERSION_AUTO=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULE_FORCE_LOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=262144
|
||||
CONFIG_PID_IN_CONTEXTIDR=y
|
||||
CONFIG_EXPERT=y
|
||||
CONFIG_CHECKPOINT_RESTORE=y
|
||||
# virtualization
|
||||
CONFIG_VHOST_NET=y
|
||||
CONFIG_KVM_ARM_MAX_VCPUS=8
|
||||
# network and misc
|
||||
CONFIG_INET_ESP=y
|
||||
CONFIG_XFRM_USER=y
|
||||
CONFIG_NET_KEY=y
|
||||
CONFIG_CRYPTO_USER=y
|
||||
CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
CONFIG_EXT3_FS_POSIX_ACL=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXT4_FS_SECURITY=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
CONFIG_BLK_DEV_THROTTLING=y
|
||||
CONFIG_CFQ_GROUP_IOSCHED=y
|
||||
CONFIG_TMPFS_XATTR=y
|
||||
CONFIG_NETFILTER_ADVANCED=y
|
||||
CONFIG_BRIDGE_NETFILTER=y
|
||||
CONFIG_NETFILTER_NETLINK=y
|
||||
CONFIG_NETFILTER_XTABLES=y
|
||||
CONFIG_NETFILTER_XT_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
|
||||
CONFIG_NETFILTER_XT_NAT=y
|
||||
CONFIG_NF_CONNTRACK=y
|
||||
CONFIG_NF_CONNTRACK_MARK=y
|
||||
CONFIG_NF_CONNTRACK_PROCFS=y
|
||||
CONFIG_NF_NAT=y
|
||||
CONFIG_NF_NAT_NEEDED=y
|
||||
CONFIG_NF_TABLES=y
|
||||
CONFIG_NFT_CT=y
|
||||
CONFIG_NFT_RBTREE=y
|
||||
CONFIG_NFT_MASQ=y
|
||||
CONFIG_NFT_NAT=y
|
||||
CONFIG_NFT_COMPAT=y
|
||||
CONFIG_NF_DEFRAG_IPV4=y
|
||||
CONFIG_NF_CONNTRACK_IPV4=y
|
||||
CONFIG_NF_CONNTRACK_PROC_COMPAT=y
|
||||
CONFIG_NF_TABLES_IPV4=y
|
||||
CONFIG_NF_NAT_IPV4=y
|
||||
CONFIG_NF_NAT_MASQUERADE_IPV4=y
|
||||
CONFIG_IP_NF_IPTABLES=y
|
||||
CONFIG_IP_NF_FILTER=y
|
||||
CONFIG_IP_NF_NAT=y
|
||||
CONFIG_IP_NF_TARGET_MASQUERADE=y
|
||||
CONFIG_IP_NF_MANGLE=y
|
||||
CONFIG_NF_TABLES_BRIDGE=y
|
||||
CONFIG_BRIDGE_NF_EBTABLES=y
|
||||
CONFIG_BRIDGE_EBT_T_NAT=y
|
||||
CONFIG_BRIDGE_EBT_DNAT=y
|
||||
CONFIG_BRIDGE_EBT_SNAT=y
|
||||
CONFIG_UNIX_DIAG=y
|
||||
CONFIG_PACKET_DIAG=y
|
||||
CONFIG_NETLINK_DIAG=y
|
||||
CONFIG_NETFILTER_XT_MATCH_COMMENT=y
|
||||
|
||||
# disable unneeded options and override default options set by defconfig to deduce the size of modules
|
||||
# CONFIG_DRM is not set
|
||||
# CONFIG_USB_NET_DRIVERS is not set
|
||||
# CONFIG_NET_VENDOR_STMICRO is not set
|
||||
# CONFIG_MEDIA_SUPPORT is not set
|
||||
# CONFIG_BACKLIGHT_GENERIC is not set
|
||||
# CONFIG_TEGRA_HOST1X is not set
|
||||
# CONFIG_BT is not set
|
||||
# CONFIG_CFG80211 is not set
|
||||
# CONFIG_MAC80211 is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_NF_NAT_IPV6=y
|
||||
CONFIG_NF_NAT_MASQUERADE_IPV6=y
|
||||
CONFIG_NF_REJECT_IPV6=y
|
||||
CONFIG_IPV6_SIT=y
|
||||
CONFIG_NF_LOG_IPV6=y
|
||||
CONFIG_NF_CONNTRACK_IPV6=y
|
||||
CONFIG_VLAN_8021Q=y
|
||||
CONFIG_BRIDGE=y
|
||||
CONFIG_MACVLAN=y
|
||||
CONFIG_MACVTAP=y
|
||||
CONFIG_BTRFS_FS=y
|
||||
CONFIG_FUSE_FS=y
|
||||
|
||||
# lxc
|
||||
CONFIG_UNIX_DIAG=y
|
||||
CONFIG_PACKET_DIAG=y
|
||||
CONFIG_NETLINK_DIAG=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
|
||||
# docker
|
||||
CONFIG_OVERLAY_FS=y
|
||||
|
|
@ -0,0 +1,607 @@
|
|||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_AUDIT=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_IRQ_TIME_ACCOUNTING=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BSD_PROCESS_ACCT_V3=y
|
||||
CONFIG_TASKSTATS=y
|
||||
CONFIG_TASK_DELAY_ACCT=y
|
||||
CONFIG_TASK_XACCT=y
|
||||
CONFIG_TASK_IO_ACCOUNTING=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_NUMA_BALANCING=y
|
||||
CONFIG_MEMCG=y
|
||||
CONFIG_MEMCG_SWAP=y
|
||||
CONFIG_BLK_CGROUP=y
|
||||
CONFIG_CGROUP_PIDS=y
|
||||
CONFIG_CGROUP_HUGETLB=y
|
||||
CONFIG_CPUSETS=y
|
||||
CONFIG_CGROUP_DEVICE=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_CGROUP_PERF=y
|
||||
CONFIG_USER_NS=y
|
||||
CONFIG_SCHED_AUTOGROUP=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_JUMP_LABEL=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
CONFIG_ARCH_SUNXI=y
|
||||
CONFIG_ARCH_ALPINE=y
|
||||
CONFIG_ARCH_BCM2835=y
|
||||
CONFIG_ARCH_BCM_IPROC=y
|
||||
CONFIG_ARCH_BERLIN=y
|
||||
CONFIG_ARCH_BRCMSTB=y
|
||||
CONFIG_ARCH_EXYNOS=y
|
||||
CONFIG_ARCH_LAYERSCAPE=y
|
||||
CONFIG_ARCH_LG1K=y
|
||||
CONFIG_ARCH_HISI=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_ARCH_MESON=y
|
||||
CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_ARCH_QCOM=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_ARCH_SEATTLE=y
|
||||
CONFIG_ARCH_RENESAS=y
|
||||
CONFIG_ARCH_R8A7795=y
|
||||
CONFIG_ARCH_R8A7796=y
|
||||
CONFIG_ARCH_STRATIX10=y
|
||||
CONFIG_ARCH_TEGRA=y
|
||||
CONFIG_ARCH_SPRD=y
|
||||
CONFIG_ARCH_THUNDER=y
|
||||
CONFIG_ARCH_THUNDER2=y
|
||||
CONFIG_ARCH_UNIPHIER=y
|
||||
CONFIG_ARCH_VEXPRESS=y
|
||||
CONFIG_ARCH_XGENE=y
|
||||
CONFIG_ARCH_ZX=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_HOTPLUG_PCI_PCIE=y
|
||||
CONFIG_PCI_IOV=y
|
||||
CONFIG_HOTPLUG_PCI=y
|
||||
CONFIG_HOTPLUG_PCI_ACPI=y
|
||||
CONFIG_PCI_LAYERSCAPE=y
|
||||
CONFIG_PCI_HISI=y
|
||||
CONFIG_PCIE_QCOM=y
|
||||
CONFIG_PCIE_KIRIN=y
|
||||
CONFIG_PCIE_ARMADA_8K=y
|
||||
CONFIG_PCI_AARDVARK=y
|
||||
CONFIG_PCIE_RCAR=y
|
||||
CONFIG_PCIE_ROCKCHIP=m
|
||||
CONFIG_PCI_HOST_GENERIC=y
|
||||
CONFIG_PCI_XGENE=y
|
||||
CONFIG_ARM64_VA_BITS_48=y
|
||||
CONFIG_SCHED_MC=y
|
||||
CONFIG_NUMA=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_KSM=y
|
||||
CONFIG_TRANSPARENT_HUGEPAGE=y
|
||||
CONFIG_CMA=y
|
||||
CONFIG_SECCOMP=y
|
||||
CONFIG_KEXEC=y
|
||||
CONFIG_CRASH_DUMP=y
|
||||
CONFIG_XEN=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_COMPAT=y
|
||||
CONFIG_HIBERNATION=y
|
||||
CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
|
||||
CONFIG_ARM_CPUIDLE=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
|
||||
CONFIG_ARM_SCPI_CPUFREQ=y
|
||||
CONFIG_ACPI_CPPC_CPUFREQ=m
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_MULTICAST=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_IPV6=m
|
||||
CONFIG_NETFILTER=y
|
||||
CONFIG_NF_CONNTRACK=m
|
||||
CONFIG_NF_CONNTRACK_EVENTS=y
|
||||
CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
|
||||
CONFIG_NETFILTER_XT_TARGET_LOG=m
|
||||
CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
|
||||
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
|
||||
CONFIG_NF_CONNTRACK_IPV4=m
|
||||
CONFIG_IP_NF_IPTABLES=m
|
||||
CONFIG_IP_NF_FILTER=m
|
||||
CONFIG_IP_NF_TARGET_REJECT=m
|
||||
CONFIG_IP_NF_NAT=m
|
||||
CONFIG_IP_NF_TARGET_MASQUERADE=m
|
||||
CONFIG_IP_NF_MANGLE=m
|
||||
CONFIG_NF_CONNTRACK_IPV6=m
|
||||
CONFIG_IP6_NF_IPTABLES=m
|
||||
CONFIG_IP6_NF_FILTER=m
|
||||
CONFIG_IP6_NF_TARGET_REJECT=m
|
||||
CONFIG_IP6_NF_MANGLE=m
|
||||
CONFIG_IP6_NF_NAT=m
|
||||
CONFIG_IP6_NF_TARGET_MASQUERADE=m
|
||||
CONFIG_BRIDGE=m
|
||||
CONFIG_BRIDGE_VLAN_FILTERING=y
|
||||
CONFIG_VLAN_8021Q=m
|
||||
CONFIG_VLAN_8021Q_GVRP=y
|
||||
CONFIG_VLAN_8021Q_MVRP=y
|
||||
CONFIG_BPF_JIT=y
|
||||
CONFIG_BT=m
|
||||
CONFIG_BT_HIDP=m
|
||||
# CONFIG_BT_HS is not set
|
||||
# CONFIG_BT_LE is not set
|
||||
CONFIG_BT_LEDS=y
|
||||
# CONFIG_BT_DEBUGFS is not set
|
||||
CONFIG_BT_HCIUART=m
|
||||
CONFIG_BT_HCIUART_LL=y
|
||||
CONFIG_CFG80211=m
|
||||
CONFIG_MAC80211=m
|
||||
CONFIG_MAC80211_LEDS=y
|
||||
CONFIG_RFKILL=m
|
||||
CONFIG_NET_9P=y
|
||||
CONFIG_NET_9P_VIRTIO=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_DENALI_DT=y
|
||||
CONFIG_MTD_SPI_NOR=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NBD=m
|
||||
CONFIG_VIRTIO_BLK=y
|
||||
CONFIG_BLK_DEV_NVME=m
|
||||
CONFIG_SRAM=y
|
||||
CONFIG_EEPROM_AT25=m
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_SCSI_SAS_ATA=y
|
||||
CONFIG_SCSI_HISI_SAS=y
|
||||
CONFIG_SCSI_HISI_SAS_PCI=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_SATA_AHCI=y
|
||||
CONFIG_SATA_AHCI_PLATFORM=y
|
||||
CONFIG_AHCI_CEVA=y
|
||||
CONFIG_AHCI_MVEBU=y
|
||||
CONFIG_AHCI_XGENE=y
|
||||
CONFIG_AHCI_QORIQ=y
|
||||
CONFIG_SATA_SIL24=y
|
||||
CONFIG_SATA_RCAR=y
|
||||
CONFIG_PATA_PLATFORM=y
|
||||
CONFIG_PATA_OF_PLATFORM=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_MACVLAN=m
|
||||
CONFIG_MACVTAP=m
|
||||
CONFIG_TUN=y
|
||||
CONFIG_VETH=m
|
||||
CONFIG_VIRTIO_NET=y
|
||||
CONFIG_AMD_XGBE=y
|
||||
CONFIG_NET_XGENE=y
|
||||
CONFIG_MACB=y
|
||||
CONFIG_HNS_DSAF=y
|
||||
CONFIG_HNS_ENET=y
|
||||
CONFIG_E1000E=y
|
||||
CONFIG_IGB=y
|
||||
CONFIG_IGBVF=y
|
||||
CONFIG_MVNETA=y
|
||||
CONFIG_MVPP2=y
|
||||
CONFIG_SKY2=y
|
||||
CONFIG_QCOM_EMAC=m
|
||||
CONFIG_RAVB=y
|
||||
CONFIG_SMC91X=y
|
||||
CONFIG_SMSC911X=y
|
||||
CONFIG_STMMAC_ETH=m
|
||||
CONFIG_MDIO_BUS_MUX_MMIOREG=y
|
||||
CONFIG_AT803X_PHY=m
|
||||
CONFIG_MARVELL_PHY=m
|
||||
CONFIG_MESON_GXL_PHY=m
|
||||
CONFIG_MICREL_PHY=y
|
||||
CONFIG_REALTEK_PHY=m
|
||||
CONFIG_ROCKCHIP_PHY=y
|
||||
CONFIG_USB_PEGASUS=m
|
||||
CONFIG_USB_RTL8150=m
|
||||
CONFIG_USB_RTL8152=m
|
||||
CONFIG_USB_USBNET=m
|
||||
CONFIG_USB_NET_DM9601=m
|
||||
CONFIG_USB_NET_SR9800=m
|
||||
CONFIG_USB_NET_SMSC75XX=m
|
||||
CONFIG_USB_NET_SMSC95XX=m
|
||||
CONFIG_USB_NET_PLUSB=m
|
||||
CONFIG_USB_NET_MCS7830=m
|
||||
CONFIG_BRCMFMAC=m
|
||||
CONFIG_WL18XX=m
|
||||
CONFIG_WLCORE_SDIO=m
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
CONFIG_KEYBOARD_ADC=m
|
||||
CONFIG_KEYBOARD_CROS_EC=y
|
||||
CONFIG_KEYBOARD_GPIO=y
|
||||
CONFIG_INPUT_MISC=y
|
||||
CONFIG_INPUT_PM8941_PWRKEY=y
|
||||
CONFIG_INPUT_HISI_POWERKEY=y
|
||||
# CONFIG_SERIO_SERPORT is not set
|
||||
CONFIG_SERIO_AMBAKMI=y
|
||||
CONFIG_LEGACY_PTY_COUNT=16
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_8250_BCM2835AUX=y
|
||||
CONFIG_SERIAL_8250_DW=y
|
||||
CONFIG_SERIAL_8250_MT6577=y
|
||||
CONFIG_SERIAL_8250_UNIPHIER=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIAL_AMBA_PL011=y
|
||||
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
|
||||
CONFIG_SERIAL_MESON=y
|
||||
CONFIG_SERIAL_MESON_CONSOLE=y
|
||||
CONFIG_SERIAL_SAMSUNG=y
|
||||
CONFIG_SERIAL_SAMSUNG_CONSOLE=y
|
||||
CONFIG_SERIAL_TEGRA=y
|
||||
CONFIG_SERIAL_SH_SCI=y
|
||||
CONFIG_SERIAL_SH_SCI_NR_UARTS=11
|
||||
CONFIG_SERIAL_SH_SCI_CONSOLE=y
|
||||
CONFIG_SERIAL_MSM=y
|
||||
CONFIG_SERIAL_MSM_CONSOLE=y
|
||||
CONFIG_SERIAL_XILINX_PS_UART=y
|
||||
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
|
||||
CONFIG_SERIAL_MVEBU_UART=y
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
CONFIG_SERIAL_DEV_CTRL_TTYPORT=y
|
||||
CONFIG_VIRTIO_CONSOLE=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_I2C_BCM2835=m
|
||||
CONFIG_I2C_DESIGNWARE_PLATFORM=y
|
||||
CONFIG_I2C_IMX=y
|
||||
CONFIG_I2C_MESON=y
|
||||
CONFIG_I2C_MV64XXX=y
|
||||
CONFIG_I2C_PXA=y
|
||||
CONFIG_I2C_QUP=y
|
||||
CONFIG_I2C_RK3X=y
|
||||
CONFIG_I2C_SH_MOBILE=y
|
||||
CONFIG_I2C_TEGRA=y
|
||||
CONFIG_I2C_UNIPHIER_F=y
|
||||
CONFIG_I2C_RCAR=y
|
||||
CONFIG_I2C_CROS_EC_TUNNEL=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_MESON_SPICC=m
|
||||
CONFIG_SPI_MESON_SPIFC=m
|
||||
CONFIG_SPI_BCM2835=m
|
||||
CONFIG_SPI_BCM2835AUX=m
|
||||
CONFIG_SPI_ORION=y
|
||||
CONFIG_SPI_PL022=y
|
||||
CONFIG_SPI_QUP=y
|
||||
CONFIG_SPI_ROCKCHIP=y
|
||||
CONFIG_SPI_S3C64XX=y
|
||||
CONFIG_SPI_SPIDEV=m
|
||||
CONFIG_SPMI=y
|
||||
CONFIG_PINCTRL_IPQ8074=y
|
||||
CONFIG_PINCTRL_SINGLE=y
|
||||
CONFIG_PINCTRL_MAX77620=y
|
||||
CONFIG_PINCTRL_MSM8916=y
|
||||
CONFIG_PINCTRL_MSM8994=y
|
||||
CONFIG_PINCTRL_MSM8996=y
|
||||
CONFIG_PINCTRL_QDF2XXX=y
|
||||
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_GPIO_PL061=y
|
||||
CONFIG_GPIO_RCAR=y
|
||||
CONFIG_GPIO_XGENE=y
|
||||
CONFIG_GPIO_XGENE_SB=y
|
||||
CONFIG_GPIO_PCA953X=y
|
||||
CONFIG_GPIO_PCA953X_IRQ=y
|
||||
CONFIG_GPIO_MAX77620=y
|
||||
CONFIG_POWER_RESET_MSM=y
|
||||
CONFIG_POWER_RESET_XGENE=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
CONFIG_SYSCON_REBOOT_MODE=y
|
||||
CONFIG_BATTERY_BQ27XXX=y
|
||||
CONFIG_SENSORS_ARM_SCPI=y
|
||||
CONFIG_SENSORS_LM90=m
|
||||
CONFIG_SENSORS_INA2XX=m
|
||||
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
|
||||
CONFIG_CPU_THERMAL=y
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_BRCMSTB_THERMAL=m
|
||||
CONFIG_EXYNOS_THERMAL=y
|
||||
CONFIG_ROCKCHIP_THERMAL=m
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_S3C2410_WATCHDOG=y
|
||||
CONFIG_MESON_GXBB_WATCHDOG=m
|
||||
CONFIG_MESON_WATCHDOG=m
|
||||
CONFIG_RENESAS_WDT=y
|
||||
CONFIG_UNIPHIER_WATCHDOG=y
|
||||
CONFIG_BCM2835_WDT=y
|
||||
CONFIG_MFD_AXP20X_RSB=y
|
||||
CONFIG_MFD_CROS_EC=y
|
||||
CONFIG_MFD_CROS_EC_I2C=y
|
||||
CONFIG_MFD_CROS_EC_SPI=y
|
||||
CONFIG_MFD_EXYNOS_LPASS=m
|
||||
CONFIG_MFD_HI6421_PMIC=y
|
||||
CONFIG_MFD_HI655X_PMIC=y
|
||||
CONFIG_MFD_MAX77620=y
|
||||
CONFIG_MFD_SPMI_PMIC=y
|
||||
CONFIG_MFD_RK808=y
|
||||
CONFIG_MFD_SEC_CORE=y
|
||||
CONFIG_REGULATOR_AXP20X=y
|
||||
CONFIG_REGULATOR_FAN53555=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_GPIO=y
|
||||
CONFIG_REGULATOR_HI6421V530=y
|
||||
CONFIG_REGULATOR_HI655X=y
|
||||
CONFIG_REGULATOR_MAX77620=y
|
||||
CONFIG_REGULATOR_PWM=y
|
||||
CONFIG_REGULATOR_QCOM_SMD_RPM=y
|
||||
CONFIG_REGULATOR_QCOM_SPMI=y
|
||||
CONFIG_REGULATOR_RK808=y
|
||||
CONFIG_REGULATOR_S2MPS11=y
|
||||
CONFIG_MEDIA_SUPPORT=m
|
||||
CONFIG_MEDIA_CAMERA_SUPPORT=y
|
||||
CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
|
||||
CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
|
||||
CONFIG_MEDIA_CONTROLLER=y
|
||||
CONFIG_MEDIA_RC_SUPPORT=y
|
||||
CONFIG_RC_CORE=m
|
||||
CONFIG_RC_DEVICES=y
|
||||
CONFIG_RC_DECODERS=y
|
||||
CONFIG_IR_MESON=m
|
||||
CONFIG_VIDEO_V4L2_SUBDEV_API=y
|
||||
# CONFIG_DVB_NET is not set
|
||||
CONFIG_V4L_MEM2MEM_DRIVERS=y
|
||||
CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m
|
||||
CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
|
||||
CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
|
||||
CONFIG_VIDEO_RENESAS_FCP=m
|
||||
CONFIG_VIDEO_RENESAS_VSP1=m
|
||||
CONFIG_DRM=m
|
||||
CONFIG_DRM_NOUVEAU=m
|
||||
CONFIG_DRM_EXYNOS=m
|
||||
CONFIG_DRM_EXYNOS5433_DECON=y
|
||||
CONFIG_DRM_EXYNOS7_DECON=y
|
||||
CONFIG_DRM_EXYNOS_DSI=y
|
||||
# CONFIG_DRM_EXYNOS_DP is not set
|
||||
CONFIG_DRM_EXYNOS_HDMI=y
|
||||
CONFIG_DRM_EXYNOS_MIC=y
|
||||
CONFIG_DRM_ROCKCHIP=m
|
||||
CONFIG_ROCKCHIP_ANALOGIX_DP=y
|
||||
CONFIG_ROCKCHIP_CDN_DP=y
|
||||
CONFIG_ROCKCHIP_DW_HDMI=y
|
||||
CONFIG_ROCKCHIP_DW_MIPI_DSI=y
|
||||
CONFIG_ROCKCHIP_INNO_HDMI=y
|
||||
CONFIG_DRM_RCAR_DU=m
|
||||
CONFIG_DRM_RCAR_LVDS=y
|
||||
CONFIG_DRM_RCAR_VSP=y
|
||||
CONFIG_DRM_TEGRA=m
|
||||
CONFIG_DRM_PANEL_SIMPLE=m
|
||||
CONFIG_DRM_I2C_ADV7511=m
|
||||
CONFIG_DRM_VC4=m
|
||||
CONFIG_DRM_HISI_KIRIN=m
|
||||
CONFIG_DRM_MESON=m
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_ARMCLCD=y
|
||||
CONFIG_BACKLIGHT_GENERIC=m
|
||||
CONFIG_BACKLIGHT_PWM=m
|
||||
CONFIG_BACKLIGHT_LP855X=m
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
CONFIG_LOGO=y
|
||||
# CONFIG_LOGO_LINUX_MONO is not set
|
||||
# CONFIG_LOGO_LINUX_VGA16 is not set
|
||||
CONFIG_SOUND=y
|
||||
CONFIG_SND=y
|
||||
CONFIG_SND_SOC=y
|
||||
CONFIG_SND_BCM2835_SOC_I2S=m
|
||||
CONFIG_SND_SOC_SAMSUNG=y
|
||||
CONFIG_SND_SOC_RCAR=m
|
||||
CONFIG_SND_SOC_AK4613=m
|
||||
CONFIG_SND_SIMPLE_CARD=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_OTG=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_TEGRA=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_MSM=y
|
||||
CONFIG_USB_EHCI_EXYNOS=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_EXYNOS=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_RENESAS_USBHS=m
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC2=y
|
||||
CONFIG_USB_CHIPIDEA=y
|
||||
CONFIG_USB_CHIPIDEA_UDC=y
|
||||
CONFIG_USB_CHIPIDEA_HOST=y
|
||||
CONFIG_USB_ISP1760=y
|
||||
CONFIG_USB_HSIC_USB3503=y
|
||||
CONFIG_NOP_USB_XCEIV=y
|
||||
CONFIG_USB_MSM_OTG=y
|
||||
CONFIG_USB_QCOM_8X16_PHY=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_RENESAS_USBHS_UDC=m
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK_MINORS=32
|
||||
CONFIG_MMC_ARMMMCI=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_ACPI=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_SDHCI_OF_ARASAN=y
|
||||
CONFIG_MMC_SDHCI_OF_ESDHC=y
|
||||
CONFIG_MMC_SDHCI_CADENCE=y
|
||||
CONFIG_MMC_SDHCI_TEGRA=y
|
||||
CONFIG_MMC_MESON_GX=y
|
||||
CONFIG_MMC_SDHCI_MSM=y
|
||||
CONFIG_MMC_SPI=y
|
||||
CONFIG_MMC_SDHI=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_EXYNOS=y
|
||||
CONFIG_MMC_DW_K3=y
|
||||
CONFIG_MMC_DW_ROCKCHIP=y
|
||||
CONFIG_MMC_SUNXI=y
|
||||
CONFIG_MMC_BCM2835=y
|
||||
CONFIG_MMC_SDHCI_XENON=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_PWM=y
|
||||
CONFIG_LEDS_SYSCON=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_LEDS_TRIGGER_CPU=y
|
||||
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
|
||||
CONFIG_EDAC=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_MAX77686=y
|
||||
CONFIG_RTC_DRV_RK808=m
|
||||
CONFIG_RTC_DRV_S5M=y
|
||||
CONFIG_RTC_DRV_DS3232=y
|
||||
CONFIG_RTC_DRV_EFI=y
|
||||
CONFIG_RTC_DRV_S3C=y
|
||||
CONFIG_RTC_DRV_PL031=y
|
||||
CONFIG_RTC_DRV_SUN6I=y
|
||||
CONFIG_RTC_DRV_TEGRA=y
|
||||
CONFIG_RTC_DRV_XGENE=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_DMA_BCM2835=m
|
||||
CONFIG_K3_DMA=y
|
||||
CONFIG_MV_XOR_V2=y
|
||||
CONFIG_PL330_DMA=y
|
||||
CONFIG_TEGRA20_APB_DMA=y
|
||||
CONFIG_QCOM_BAM_DMA=y
|
||||
CONFIG_QCOM_HIDMA_MGMT=y
|
||||
CONFIG_QCOM_HIDMA=y
|
||||
CONFIG_RCAR_DMAC=y
|
||||
CONFIG_VFIO=y
|
||||
CONFIG_VFIO_PCI=y
|
||||
CONFIG_VIRTIO_PCI=y
|
||||
CONFIG_VIRTIO_BALLOON=y
|
||||
CONFIG_VIRTIO_MMIO=y
|
||||
CONFIG_XEN_GNTDEV=y
|
||||
CONFIG_XEN_GRANT_DEV_ALLOC=y
|
||||
CONFIG_COMMON_CLK_RK808=y
|
||||
CONFIG_COMMON_CLK_SCPI=y
|
||||
CONFIG_COMMON_CLK_CS2000_CP=y
|
||||
CONFIG_COMMON_CLK_S2MPS11=y
|
||||
CONFIG_CLK_QORIQ=y
|
||||
CONFIG_COMMON_CLK_PWM=y
|
||||
CONFIG_COMMON_CLK_QCOM=y
|
||||
CONFIG_QCOM_CLK_SMD_RPM=y
|
||||
CONFIG_IPQ_GCC_8074=y
|
||||
CONFIG_MSM_GCC_8916=y
|
||||
CONFIG_MSM_GCC_8994=y
|
||||
CONFIG_MSM_MMCC_8996=y
|
||||
CONFIG_HWSPINLOCK=y
|
||||
CONFIG_HWSPINLOCK_QCOM=y
|
||||
CONFIG_ARM_MHU=y
|
||||
CONFIG_PLATFORM_MHU=y
|
||||
CONFIG_BCM2835_MBOX=y
|
||||
CONFIG_HI6220_MBOX=y
|
||||
CONFIG_ROCKCHIP_IOMMU=y
|
||||
CONFIG_ARM_SMMU=y
|
||||
CONFIG_ARM_SMMU_V3=y
|
||||
CONFIG_RPMSG_QCOM_SMD=y
|
||||
CONFIG_RASPBERRYPI_POWER=y
|
||||
CONFIG_QCOM_SMEM=y
|
||||
CONFIG_QCOM_SMD_RPM=y
|
||||
CONFIG_QCOM_SMP2P=y
|
||||
CONFIG_QCOM_SMSM=y
|
||||
CONFIG_ROCKCHIP_PM_DOMAINS=y
|
||||
CONFIG_ARCH_TEGRA_132_SOC=y
|
||||
CONFIG_ARCH_TEGRA_210_SOC=y
|
||||
CONFIG_ARCH_TEGRA_186_SOC=y
|
||||
CONFIG_EXTCON_USB_GPIO=y
|
||||
CONFIG_IIO=y
|
||||
CONFIG_EXYNOS_ADC=y
|
||||
CONFIG_ROCKCHIP_SARADC=m
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_BCM2835=m
|
||||
CONFIG_PWM_CROS_EC=m
|
||||
CONFIG_PWM_MESON=m
|
||||
CONFIG_PWM_ROCKCHIP=y
|
||||
CONFIG_PWM_SAMSUNG=y
|
||||
CONFIG_PWM_TEGRA=m
|
||||
CONFIG_PHY_RCAR_GEN3_USB2=y
|
||||
CONFIG_PHY_HI6220_USB=y
|
||||
CONFIG_PHY_SUN4I_USB=y
|
||||
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
|
||||
CONFIG_PHY_ROCKCHIP_EMMC=y
|
||||
CONFIG_PHY_ROCKCHIP_PCIE=m
|
||||
CONFIG_PHY_XGENE=y
|
||||
CONFIG_PHY_TEGRA_XUSB=y
|
||||
CONFIG_QCOM_L2_PMU=y
|
||||
CONFIG_QCOM_L3_PMU=y
|
||||
CONFIG_TEE=y
|
||||
CONFIG_OPTEE=y
|
||||
CONFIG_ARM_SCPI_PROTOCOL=y
|
||||
CONFIG_RASPBERRYPI_FIRMWARE=y
|
||||
CONFIG_EFI_CAPSULE_LOADER=y
|
||||
CONFIG_ACPI=y
|
||||
CONFIG_ACPI_APEI=y
|
||||
CONFIG_ACPI_APEI_GHES=y
|
||||
CONFIG_ACPI_APEI_PCIEAER=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_BTRFS_FS=m
|
||||
CONFIG_BTRFS_FS_POSIX_ACL=y
|
||||
CONFIG_FANOTIFY=y
|
||||
CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
|
||||
CONFIG_QUOTA=y
|
||||
CONFIG_AUTOFS4_FS=y
|
||||
CONFIG_FUSE_FS=m
|
||||
CONFIG_CUSE=m
|
||||
CONFIG_OVERLAY_FS=m
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_CONFIGFS_FS=y
|
||||
CONFIG_EFIVAR_FS=y
|
||||
CONFIG_SQUASHFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_NFS_V4_1=y
|
||||
CONFIG_NFS_V4_2=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_9P_FS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
CONFIG_KVM=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_LOCKUP_DETECTOR=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_MEMTEST=y
|
||||
CONFIG_SECURITY=y
|
||||
CONFIG_CRYPTO_ECHAINIV=y
|
||||
CONFIG_CRYPTO_ANSI_CPRNG=y
|
||||
CONFIG_ARM64_CRYPTO=y
|
||||
CONFIG_CRYPTO_SHA256_ARM64=m
|
||||
CONFIG_CRYPTO_SHA512_ARM64=m
|
||||
CONFIG_CRYPTO_SHA1_ARM64_CE=y
|
||||
CONFIG_CRYPTO_SHA2_ARM64_CE=y
|
||||
CONFIG_CRYPTO_GHASH_ARM64_CE=y
|
||||
CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
|
||||
CONFIG_CRYPTO_CRC32_ARM64_CE=m
|
||||
CONFIG_CRYPTO_AES_ARM64=m
|
||||
CONFIG_CRYPTO_AES_ARM64_CE=m
|
||||
CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
|
||||
CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
|
||||
CONFIG_CRYPTO_AES_ARM64_NEON_BLK=m
|
||||
CONFIG_CRYPTO_CHACHA20_NEON=m
|
||||
CONFIG_CRYPTO_AES_ARM64_BS=m
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
# LTTng options
|
||||
CONFIG_FUNCTION_TRACER=y
|
||||
CONFIG_HAVE_FUNCTION_TRACER=y
|
||||
CONFIG_NOP_TRACER=y
|
||||
CONFIG_STACKTRACE=y
|
||||
CONFIG_RING_BUFFER=y
|
||||
CONFIG_EVENT_TRACING=y
|
||||
CONFIG_CONTEXT_SWITCH_TRACER=y
|
||||
CONFIG_TRACING=y
|
||||
CONFIG_GENERIC_TRACER=y
|
||||
CONFIG_TRACING_SUPPORT=y
|
||||
CONFIG_FTRACE=y
|
||||
CONFIG_DYNAMIC_FTRACE=y
|
||||
CONFIG_TRACEPOINTS=y
|
||||
CONFIG_CONTEXT_SWITCH_TRACER=y
|
||||
CONFIG_TRACE_CLOCK=y
|
||||
CONFIG_BINARY_PRINTF=y
|
||||
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
|
||||
CONFIG_PERF_EVENTS=y
|
||||
CONFIG_KPROBES=y
|
||||
CONFIG_KRETPROBES=y
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -209,6 +209,4 @@ source "drivers/tee/Kconfig"
|
|||
|
||||
source "drivers/mux/Kconfig"
|
||||
|
||||
source "drivers/hctel/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -183,6 +183,3 @@ obj-$(CONFIG_FPGA) += fpga/
|
|||
obj-$(CONFIG_FSI) += fsi/
|
||||
obj-$(CONFIG_TEE) += tee/
|
||||
obj-$(CONFIG_MULTIPLEXER) += mux/
|
||||
|
||||
|
||||
obj-$(CONFIG_HCTEL) += hctel/
|
||||
|
|
@ -1064,7 +1064,6 @@ static void init_aead_job(struct aead_request *req,
|
|||
if (unlikely(req->src != req->dst)) {
|
||||
if (edesc->dst_nents == 1) {
|
||||
dst_dma = sg_dma_address(req->dst);
|
||||
out_options = 0;
|
||||
} else {
|
||||
dst_dma = edesc->sec4_sg_dma +
|
||||
sec4_sg_index *
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
/*
|
||||
* crypto alg
|
||||
*/
|
||||
#define CAAM_CRA_PRIORITY 4000
|
||||
#define CAAM_CRA_PRIORITY 2000
|
||||
/* max key is sum of AES_MAX_KEY_SIZE, max split key size */
|
||||
#define CAAM_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + \
|
||||
SHA512_DIGEST_SIZE * 2)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,178 @@
|
|||
/*
|
||||
* Copyright 2009 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "aux.h"
|
||||
#include "pad.h"
|
||||
|
||||
static int
|
||||
nvkm_i2c_aux_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
|
||||
{
|
||||
struct nvkm_i2c_aux *aux = container_of(adap, typeof(*aux), i2c);
|
||||
struct i2c_msg *msg = msgs;
|
||||
int ret, mcnt = num;
|
||||
|
||||
ret = nvkm_i2c_aux_acquire(aux);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
while (mcnt--) {
|
||||
u8 remaining = msg->len;
|
||||
u8 *ptr = msg->buf;
|
||||
|
||||
while (remaining) {
|
||||
u8 cnt = (remaining > 16) ? 16 : remaining;
|
||||
u8 cmd;
|
||||
|
||||
if (msg->flags & I2C_M_RD)
|
||||
cmd = 1;
|
||||
else
|
||||
cmd = 0;
|
||||
|
||||
if (mcnt || remaining > 16)
|
||||
cmd |= 4; /* MOT */
|
||||
|
||||
ret = aux->func->xfer(aux, true, cmd, msg->addr, ptr, &cnt);
|
||||
if (ret < 0) {
|
||||
nvkm_i2c_aux_release(aux);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ptr += cnt;
|
||||
remaining -= cnt;
|
||||
}
|
||||
|
||||
msg++;
|
||||
}
|
||||
|
||||
nvkm_i2c_aux_release(aux);
|
||||
return num;
|
||||
}
|
||||
|
||||
static u32
|
||||
nvkm_i2c_aux_i2c_func(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
||||
}
|
||||
|
||||
static const struct i2c_algorithm
|
||||
nvkm_i2c_aux_i2c_algo = {
|
||||
.master_xfer = nvkm_i2c_aux_i2c_xfer,
|
||||
.functionality = nvkm_i2c_aux_i2c_func
|
||||
};
|
||||
|
||||
void
|
||||
nvkm_i2c_aux_monitor(struct nvkm_i2c_aux *aux, bool monitor)
|
||||
{
|
||||
struct nvkm_i2c_pad *pad = aux->pad;
|
||||
AUX_TRACE(aux, "monitor: %s", monitor ? "yes" : "no");
|
||||
if (monitor)
|
||||
nvkm_i2c_pad_mode(pad, NVKM_I2C_PAD_AUX);
|
||||
else
|
||||
nvkm_i2c_pad_mode(pad, NVKM_I2C_PAD_OFF);
|
||||
}
|
||||
|
||||
void
|
||||
nvkm_i2c_aux_release(struct nvkm_i2c_aux *aux)
|
||||
{
|
||||
struct nvkm_i2c_pad *pad = aux->pad;
|
||||
AUX_TRACE(aux, "release");
|
||||
nvkm_i2c_pad_release(pad);
|
||||
mutex_unlock(&aux->mutex);
|
||||
}
|
||||
|
||||
int
|
||||
nvkm_i2c_aux_acquire(struct nvkm_i2c_aux *aux)
|
||||
{
|
||||
struct nvkm_i2c_pad *pad = aux->pad;
|
||||
int ret;
|
||||
AUX_TRACE(aux, "acquire");
|
||||
mutex_lock(&aux->mutex);
|
||||
ret = nvkm_i2c_pad_acquire(pad, NVKM_I2C_PAD_AUX);
|
||||
if (ret)
|
||||
mutex_unlock(&aux->mutex);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
nvkm_i2c_aux_xfer(struct nvkm_i2c_aux *aux, bool retry, u8 type,
|
||||
u32 addr, u8 *data, u8 *size)
|
||||
{
|
||||
if (!*size && !aux->func->address_only) {
|
||||
AUX_ERR(aux, "address-only transaction dropped");
|
||||
return -ENOSYS;
|
||||
}
|
||||
return aux->func->xfer(aux, retry, type, addr, data, size);
|
||||
}
|
||||
|
||||
int
|
||||
nvkm_i2c_aux_lnk_ctl(struct nvkm_i2c_aux *aux, int nr, int bw, bool ef)
|
||||
{
|
||||
if (aux->func->lnk_ctl)
|
||||
return aux->func->lnk_ctl(aux, nr, bw, ef);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
void
|
||||
nvkm_i2c_aux_del(struct nvkm_i2c_aux **paux)
|
||||
{
|
||||
struct nvkm_i2c_aux *aux = *paux;
|
||||
if (aux && !WARN_ON(!aux->func)) {
|
||||
AUX_TRACE(aux, "dtor");
|
||||
list_del(&aux->head);
|
||||
i2c_del_adapter(&aux->i2c);
|
||||
kfree(*paux);
|
||||
*paux = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
nvkm_i2c_aux_ctor(const struct nvkm_i2c_aux_func *func,
|
||||
struct nvkm_i2c_pad *pad, int id,
|
||||
struct nvkm_i2c_aux *aux)
|
||||
{
|
||||
struct nvkm_device *device = pad->i2c->subdev.device;
|
||||
|
||||
aux->func = func;
|
||||
aux->pad = pad;
|
||||
aux->id = id;
|
||||
mutex_init(&aux->mutex);
|
||||
list_add_tail(&aux->head, &pad->i2c->aux);
|
||||
AUX_TRACE(aux, "ctor");
|
||||
|
||||
snprintf(aux->i2c.name, sizeof(aux->i2c.name), "nvkm-%s-aux-%04x",
|
||||
dev_name(device->dev), id);
|
||||
aux->i2c.owner = THIS_MODULE;
|
||||
aux->i2c.dev.parent = device->dev;
|
||||
aux->i2c.algo = &nvkm_i2c_aux_i2c_algo;
|
||||
return i2c_add_adapter(&aux->i2c);
|
||||
}
|
||||
|
||||
int
|
||||
nvkm_i2c_aux_new_(const struct nvkm_i2c_aux_func *func,
|
||||
struct nvkm_i2c_pad *pad, int id,
|
||||
struct nvkm_i2c_aux **paux)
|
||||
{
|
||||
if (!(*paux = kzalloc(sizeof(**paux), GFP_KERNEL)))
|
||||
return -ENOMEM;
|
||||
return nvkm_i2c_aux_ctor(func, pad, id, *paux);
|
||||
}
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef __NVKM_I2C_AUX_H__
|
||||
#define __NVKM_I2C_AUX_H__
|
||||
#include "pad.h"
|
||||
|
||||
struct nvkm_i2c_aux_func {
|
||||
bool address_only;
|
||||
int (*xfer)(struct nvkm_i2c_aux *, bool retry, u8 type,
|
||||
u32 addr, u8 *data, u8 *size);
|
||||
int (*lnk_ctl)(struct nvkm_i2c_aux *, int link_nr, int link_bw,
|
||||
bool enhanced_framing);
|
||||
};
|
||||
|
||||
int nvkm_i2c_aux_ctor(const struct nvkm_i2c_aux_func *, struct nvkm_i2c_pad *,
|
||||
int id, struct nvkm_i2c_aux *);
|
||||
int nvkm_i2c_aux_new_(const struct nvkm_i2c_aux_func *, struct nvkm_i2c_pad *,
|
||||
int id, struct nvkm_i2c_aux **);
|
||||
void nvkm_i2c_aux_del(struct nvkm_i2c_aux **);
|
||||
int nvkm_i2c_aux_xfer(struct nvkm_i2c_aux *, bool retry, u8 type,
|
||||
u32 addr, u8 *data, u8 *size);
|
||||
|
||||
int g94_i2c_aux_new_(const struct nvkm_i2c_aux_func *, struct nvkm_i2c_pad *,
|
||||
int, u8, struct nvkm_i2c_aux **);
|
||||
|
||||
int g94_i2c_aux_new(struct nvkm_i2c_pad *, int, u8, struct nvkm_i2c_aux **);
|
||||
int g94_i2c_aux_xfer(struct nvkm_i2c_aux *, bool, u8, u32, u8 *, u8 *);
|
||||
int gf119_i2c_aux_new(struct nvkm_i2c_pad *, int, u8, struct nvkm_i2c_aux **);
|
||||
int gm200_i2c_aux_new(struct nvkm_i2c_pad *, int, u8, struct nvkm_i2c_aux **);
|
||||
|
||||
#define AUX_MSG(b,l,f,a...) do { \
|
||||
struct nvkm_i2c_aux *_aux = (b); \
|
||||
nvkm_##l(&_aux->pad->i2c->subdev, "aux %04x: "f"\n", _aux->id, ##a); \
|
||||
} while(0)
|
||||
#define AUX_ERR(b,f,a...) AUX_MSG((b), error, f, ##a)
|
||||
#define AUX_DBG(b,f,a...) AUX_MSG((b), debug, f, ##a)
|
||||
#define AUX_TRACE(b,f,a...) AUX_MSG((b), trace, f, ##a)
|
||||
#endif
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
config HCTEL
|
||||
tristate "HCTEL drivers"
|
||||
|
||||
config HCEN104_LED
|
||||
bool "hcen104 LED drivers"
|
||||
depends on HCTEL
|
||||
|
||||
config HCEN1002_LED
|
||||
bool "hcen1002 LED drivers"
|
||||
depends on HCTEL && !HCEN104_LED
|
||||
|
|
@ -1,10 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
#
|
||||
# Makefile for the Linux kernel device drivers.
|
||||
#
|
||||
# 15 Sep 2000, Christoph Hellwig <hch@infradead.org>
|
||||
# Rewritten to use lists instead of if-statements.
|
||||
#
|
||||
|
||||
obj-$(CONFIG_HCEN104_LED) += hcen104_led/
|
||||
obj-$(CONFIG_HCEN1002_LED) += hcen1002_led/
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
config HCEN1002_LED
|
||||
tristate "hcen1002 LED drivers"
|
||||
depends on HCTEL
|
||||
depends on !HCEN104_LED
|
||||
|
|
@ -1 +0,0 @@
|
|||
obj-$(CONFIG_HCEN1002_LED) += hcen1002_led.o
|
||||
|
|
@ -1,152 +0,0 @@
|
|||
#include<linux/module.h>
|
||||
#include<linux/init.h>
|
||||
|
||||
#include <linux/miscdevice.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/slab.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/cdev.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ctype.h>
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/leds.h>
|
||||
|
||||
#define GPIO1_NUM 480
|
||||
#define GPIO2_NUM 448
|
||||
#define GPIO4_NUM 384
|
||||
|
||||
#define GPIO_EN1002(a, b) (a + b)
|
||||
|
||||
#define IGSFP0_NEXIST GPIO_EN1002(GPIO1_NUM, 23) //GPIO1_23
|
||||
//#define IGSFP0_SCL GPIO_EN1002(GPIO1_NUM, 26)
|
||||
//#define IGSFP0_SDA GPIO_EN1002(GPIO1_NUM, 25)
|
||||
#define IGSFP0_DISABLE GPIO_EN1002(GPIO1_NUM, 24)
|
||||
#define IGSFP1_DISABLE GPIO_EN1002(GPIO1_NUM, 27)
|
||||
//#define IGSFP1_SDA GPIO_EN1002(GPIO1_NUM, 28)
|
||||
#define IGSFP1_NEXIST GPIO_EN1002(GPIO1_NUM, 29)
|
||||
#define CPU_LED GPIO_EN1002(GPIO4_NUM, 12)
|
||||
|
||||
#define LTE_LED_0 GPIO_EN1002(GPIO4_NUM, 13)
|
||||
#define LTE_LED_1 GPIO_EN1002(GPIO1_NUM, 21)
|
||||
#define LTE_LED_2 GPIO_EN1002(GPIO1_NUM, 20)
|
||||
|
||||
#define LTE_PWR_EN GPIO_EN1002(GPIO1_NUM, 19)
|
||||
#define WIFI_PWR_EN GPIO_EN1002(GPIO1_NUM, 22)
|
||||
#define WIFI_PWR_USB_EN GPIO_EN1002(GPIO1_NUM, 18)
|
||||
|
||||
#define GPIO_RST GPIO_EN1002(GPIO2_NUM, 27)
|
||||
|
||||
#define LED_WIFI_5G GPIO_EN1002(GPIO4_NUM, 10)
|
||||
#define CLOUD_LED GPIO_EN1002(GPIO4_NUM, 11)
|
||||
|
||||
static struct gpio_led gpio_leds[] = {
|
||||
{
|
||||
.name = "sys",
|
||||
.default_trigger = "timer",
|
||||
.gpio = CPU_LED,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON, // 默认LED亮
|
||||
.active_low = 1, // 低电平亮
|
||||
},
|
||||
{
|
||||
.name = "cloud",
|
||||
//.default_trigger = "timer",
|
||||
.gpio = CLOUD_LED,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "lte_0",
|
||||
.gpio = LTE_LED_0,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "lte_1",
|
||||
.gpio = LTE_LED_2,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "lte_2",
|
||||
.gpio = LTE_LED_1,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
.active_low = 1,
|
||||
},
|
||||
/*
|
||||
{
|
||||
.name = "lte_pwr",
|
||||
.gpio = LTE_PWR_EN,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
.active_low = 0,
|
||||
},
|
||||
|
||||
{
|
||||
.name = "wifi_pwr_5g",
|
||||
.gpio = WIFI_PWR_EN,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.name = "wifi_pwr_2.4g",
|
||||
.gpio = WIFI_PWR_USB_EN,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
.active_low = 0,
|
||||
},
|
||||
*/
|
||||
{
|
||||
.name = "wifi_5g",
|
||||
.gpio = LED_WIFI_5G,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
.active_low = 1,
|
||||
},
|
||||
/*
|
||||
{
|
||||
.name = "wifi_2.4g",
|
||||
.gpio = LED_WIFI_24G,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
.active_low = 0,
|
||||
},
|
||||
*/
|
||||
};
|
||||
|
||||
static struct gpio_led_platform_data gpio_led_info = {
|
||||
.leds = gpio_leds,
|
||||
.num_leds = ARRAY_SIZE(gpio_leds),
|
||||
};
|
||||
|
||||
static struct platform_device leds_gpio = {
|
||||
.name = "leds-gpio",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &gpio_led_info,
|
||||
//.release = en1002_led_drv_release, //old kernel do not need,but 4.14 need
|
||||
},
|
||||
};
|
||||
|
||||
static int __init en1002_led_drv_init(void)
|
||||
{
|
||||
platform_device_register(&leds_gpio);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit en1002_led_drv_exit(void)
|
||||
{
|
||||
platform_device_unregister(&leds_gpio);
|
||||
}
|
||||
|
||||
module_init(en1002_led_drv_init);
|
||||
module_exit(en1002_led_drv_exit);
|
||||
|
||||
MODULE_AUTHOR("liji");
|
||||
MODULE_DESCRIPTION("en1002 led ctrl");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
config HCEN104_LED
|
||||
tristate "hcen104 customized drivers"
|
||||
depends on HCTEL
|
||||
depends on !HCEN1002_LED
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
|
||||
obj-$(CONFIG_HCEN104_LED) += hcen104_led.o
|
||||
|
|
@ -1,112 +0,0 @@
|
|||
#include<linux/module.h>
|
||||
#include<linux/init.h>
|
||||
|
||||
#include <linux/miscdevice.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/slab.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/cdev.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ctype.h>
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/leds.h>
|
||||
|
||||
#define GPIO1_NUM 480
|
||||
#define GPIO2_NUM 448
|
||||
#define GPIO4_NUM 384
|
||||
|
||||
#define GPIO_EN104(a, b) (a + b)
|
||||
|
||||
#define CPU_LED GPIO_EN104(GPIO4_NUM, 12)
|
||||
#define LTE_PWR_EN GPIO_EN104(GPIO1_NUM, 18)
|
||||
#define LTE_LED_0 GPIO_EN104(GPIO4_NUM, 11)
|
||||
#define LTE_LED_1 GPIO_EN104(GPIO4_NUM, 10)
|
||||
#define LTE_LED_2 GPIO_EN104(GPIO1_NUM, 22)
|
||||
#define WIFI_LED GPIO_EN104(GPIO4_NUM, 13)
|
||||
#define GPIO_RST GPIO_EN104(GPIO1_NUM, 21)
|
||||
#define CLOUD_LED GPIO_EN104(GPIO1_NUM, 16)
|
||||
|
||||
|
||||
|
||||
static struct gpio_led gpio_leds[] = {
|
||||
{
|
||||
.name = "sys",
|
||||
.default_trigger = "timer",
|
||||
.gpio = CPU_LED,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON, // 默认LED亮
|
||||
.active_low = 1, // 低电平亮
|
||||
},
|
||||
{
|
||||
.name = "cloud",
|
||||
//.default_trigger = "timer",
|
||||
.gpio = CLOUD_LED,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "lte_0",
|
||||
.gpio = LTE_LED_0,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "lte_1",
|
||||
.gpio = LTE_LED_1,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "lte_2",
|
||||
.gpio = LTE_LED_2,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "wifi",
|
||||
.gpio = WIFI_LED,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
.active_low = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_led_platform_data gpio_led_info = {
|
||||
.leds = gpio_leds,
|
||||
.num_leds = ARRAY_SIZE(gpio_leds),
|
||||
};
|
||||
|
||||
static struct platform_device leds_gpio = {
|
||||
.name = "leds-gpio",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &gpio_led_info,
|
||||
//.release = en104_led_drv_release, //old kernel do not need,but 4.14 need
|
||||
},
|
||||
};
|
||||
|
||||
static int __init en104_led_drv_init(void)
|
||||
{
|
||||
platform_device_register(&leds_gpio);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit en104_led_drv_exit(void)
|
||||
{
|
||||
platform_device_unregister(&leds_gpio);
|
||||
}
|
||||
|
||||
module_init(en104_led_drv_init);
|
||||
module_exit(en104_led_drv_exit);
|
||||
|
||||
MODULE_AUTHOR("liji");
|
||||
MODULE_DESCRIPTION("en104 led ctrl");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -1,152 +0,0 @@
|
|||
#include<linux/module.h>
|
||||
#include<linux/init.h>
|
||||
|
||||
#include <linux/miscdevice.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/slab.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/cdev.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/ctype.h>
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/leds.h>
|
||||
|
||||
#define GPIO1_NUM 480
|
||||
#define GPIO2_NUM 448
|
||||
#define GPIO4_NUM 384
|
||||
|
||||
#define GPIO_EN1002(a, b) (a + b)
|
||||
|
||||
#define IGSFP0_NEXIST GPIO_EN1002(GPIO1_NUM, 23) //GPIO1_23
|
||||
//#define IGSFP0_SCL GPIO_EN1002(GPIO1_NUM, 26)
|
||||
//#define IGSFP0_SDA GPIO_EN1002(GPIO1_NUM, 25)
|
||||
#define IGSFP0_DISABLE GPIO_EN1002(GPIO1_NUM, 24)
|
||||
#define IGSFP1_DISABLE GPIO_EN1002(GPIO1_NUM, 27)
|
||||
//#define IGSFP1_SDA GPIO_EN1002(GPIO1_NUM, 28)
|
||||
#define IGSFP1_NEXIST GPIO_EN1002(GPIO1_NUM, 29)
|
||||
#define CPU_LED GPIO_EN1002(GPIO4_NUM, 12)
|
||||
|
||||
#define LTE_LED_0 GPIO_EN1002(GPIO4_NUM, 13)
|
||||
#define LTE_LED_1 GPIO_EN1002(GPIO1_NUM, 21)
|
||||
#define LTE_LED_2 GPIO_EN1002(GPIO1_NUM, 20)
|
||||
|
||||
#define LTE_PWR_EN GPIO_EN1002(GPIO1_NUM, 19)
|
||||
#define WIFI_PWR_EN GPIO_EN1002(GPIO1_NUM, 22)
|
||||
#define WIFI_PWR_USB_EN GPIO_EN1002(GPIO1_NUM, 18)
|
||||
|
||||
#define GPIO_RST GPIO_EN1002(GPIO2_NUM, 27)
|
||||
|
||||
#define LED_WIFI_5G GPIO_EN1002(GPIO4_NUM, 10)
|
||||
#define CLOUD_LED GPIO_EN1002(GPIO4_NUM, 11)
|
||||
|
||||
static struct gpio_led gpio_leds[] = {
|
||||
{
|
||||
.name = "sys",
|
||||
.default_trigger = "timer",
|
||||
.gpio = CPU_LED,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON, // 默认LED亮
|
||||
.active_low = 1, // 低电平亮
|
||||
},
|
||||
{
|
||||
.name = "cloud",
|
||||
//.default_trigger = "timer",
|
||||
.gpio = CLOUD_LED,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "lte_0",
|
||||
.gpio = LTE_LED_0,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "lte_1",
|
||||
.gpio = LTE_LED_2,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
.active_low = 1,
|
||||
},
|
||||
{
|
||||
.name = "lte_2",
|
||||
.gpio = LTE_LED_1,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
.active_low = 1,
|
||||
},
|
||||
/*
|
||||
{
|
||||
.name = "lte_pwr",
|
||||
.gpio = LTE_PWR_EN,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
.active_low = 0,
|
||||
},
|
||||
|
||||
{
|
||||
.name = "wifi_pwr_5g",
|
||||
.gpio = WIFI_PWR_EN,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
.active_low = 0,
|
||||
},
|
||||
{
|
||||
.name = "wifi_pwr_2.4g",
|
||||
.gpio = WIFI_PWR_USB_EN,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
.active_low = 0,
|
||||
},
|
||||
*/
|
||||
{
|
||||
.name = "wifi_5g",
|
||||
.gpio = LED_WIFI_5G,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_OFF,
|
||||
.active_low = 1,
|
||||
},
|
||||
/*
|
||||
{
|
||||
.name = "wifi_2.4g",
|
||||
.gpio = LED_WIFI_24G,
|
||||
.default_state = LEDS_GPIO_DEFSTATE_ON,
|
||||
.active_low = 0,
|
||||
},
|
||||
*/
|
||||
};
|
||||
|
||||
static struct gpio_led_platform_data gpio_led_info = {
|
||||
.leds = gpio_leds,
|
||||
.num_leds = ARRAY_SIZE(gpio_leds),
|
||||
};
|
||||
|
||||
static struct platform_device leds_gpio = {
|
||||
.name = "leds-gpio",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &gpio_led_info,
|
||||
//.release = en1002_led_drv_release, //old kernel do not need,but 4.14 need
|
||||
},
|
||||
};
|
||||
|
||||
static int __init en1002_led_drv_init(void)
|
||||
{
|
||||
platform_device_register(&leds_gpio);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __exit en1002_led_drv_exit(void)
|
||||
{
|
||||
platform_device_unregister(&leds_gpio);
|
||||
}
|
||||
|
||||
module_init(en1002_led_drv_init);
|
||||
module_exit(en1002_led_drv_exit);
|
||||
|
||||
MODULE_AUTHOR("liji");
|
||||
MODULE_DESCRIPTION("en1002 led ctrl");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -698,7 +698,7 @@ config I2C_MESON
|
|||
|
||||
config I2C_MPC
|
||||
tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx"
|
||||
depends on PPC
|
||||
depends on PPC || ARCH_LAYERSCAPE
|
||||
help
|
||||
If you say yes to this option, support will be included for the
|
||||
built-in I2C interface on the MPC107, Tsi107, MPC512x, MPC52xx,
|
||||
|
|
|
|||
|
|
@ -1181,8 +1181,6 @@ static int __init __cold dpa_load(void)
|
|||
#ifndef CONFIG_PPC
|
||||
/* Detect if the current SoC requires the 4K alignment workaround */
|
||||
dpaa_errata_a010022 = soc_has_errata_a010022();
|
||||
dpaa_errata_a010022 = false;
|
||||
pr_err("Turned off dpaa_errata_a010022: %d\n", dpaa_errata_a010022);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_DPAA_DBG_LOOP
|
||||
|
|
|
|||
|
|
@ -340,12 +340,15 @@ static int __cold mac_probe(struct platform_device *_of_dev)
|
|||
mac_dev->speed = phy2speed[mac_dev->phy_if];
|
||||
mac_dev->max_speed = mac_dev->speed;
|
||||
mac_dev->if_support = DTSEC_SUPPORTED;
|
||||
|
||||
/*add by liji -- 20190708 to support half-duplex*/
|
||||
#if 0
|
||||
/* We don't support half-duplex in SGMII mode */
|
||||
if (strstr(char_prop, "sgmii") || strstr(char_prop, "qsgmii") ||
|
||||
strstr(char_prop, "sgmii-2500"))
|
||||
mac_dev->if_support &= ~(SUPPORTED_10baseT_Half |
|
||||
SUPPORTED_100baseT_Half);
|
||||
|
||||
#endif
|
||||
/* Gigabit support (no half-duplex) */
|
||||
if (mac_dev->max_speed == SPEED_1000 ||
|
||||
mac_dev->max_speed == SPEED_2500)
|
||||
|
|
|
|||
|
|
@ -40,6 +40,10 @@
|
|||
#include <asm/irq.h>
|
||||
#include <linux/uaccess.h>
|
||||
|
||||
/*add by liji -- add phy id */
|
||||
#define MARVELL_PHY_ID_88E1512 0x01410dd1
|
||||
#define MARVELL_PHY_ID_88E1543 0x01410ea2
|
||||
|
||||
#define MII_MARVELL_PHY_PAGE 22
|
||||
#define MII_MARVELL_COPPER_PAGE 0x00
|
||||
#define MII_MARVELL_FIBER_PAGE 0x01
|
||||
|
|
@ -674,8 +678,17 @@ static int marvell_config_init(struct phy_device *phydev)
|
|||
/*add by liji to modify 1543 led*/
|
||||
if(phydev->phy_id == MARVELL_PHY_ID_88E1543)
|
||||
{
|
||||
int oldpage;
|
||||
|
||||
marvell_set_page(phydev, MII_MARVELL_LED_PAGE);
|
||||
phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_1543_DEF);
|
||||
|
||||
/*modify sgmii vod*/
|
||||
oldpage = marvell_get_page(phydev);
|
||||
marvell_set_page(phydev, 1);
|
||||
phy_write(phydev, 0x1a, 0x44);
|
||||
|
||||
marvell_set_page(phydev, oldpage);
|
||||
}
|
||||
|
||||
/* Set registers from marvell,reg-init DT property */
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,547 +0,0 @@
|
|||
/*
|
||||
* SPI master driver using generic bitbanged GPIO
|
||||
*
|
||||
* Copyright (C) 2006,2008 David Brownell
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_gpio.h>
|
||||
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/spi_bitbang.h>
|
||||
#include <linux/spi/spi_gpio.h>
|
||||
|
||||
|
||||
/*
|
||||
* This bitbanging SPI master driver should help make systems usable
|
||||
* when a native hardware SPI engine is not available, perhaps because
|
||||
* its driver isn't yet working or because the I/O pins it requires
|
||||
* are used for other purposes.
|
||||
*
|
||||
* platform_device->driver_data ... points to spi_gpio
|
||||
*
|
||||
* spi->controller_state ... reserved for bitbang framework code
|
||||
* spi->controller_data ... holds chipselect GPIO
|
||||
*
|
||||
* spi->master->dev.driver_data ... points to spi_gpio->bitbang
|
||||
*/
|
||||
|
||||
struct spi_gpio {
|
||||
struct spi_bitbang bitbang;
|
||||
struct spi_gpio_platform_data pdata;
|
||||
struct platform_device *pdev;
|
||||
unsigned long cs_gpios[0];
|
||||
};
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Because the overhead of going through four GPIO procedure calls
|
||||
* per transferred bit can make performance a problem, this code
|
||||
* is set up so that you can use it in either of two ways:
|
||||
*
|
||||
* - The slow generic way: set up platform_data to hold the GPIO
|
||||
* numbers used for MISO/MOSI/SCK, and issue procedure calls for
|
||||
* each of them. This driver can handle several such busses.
|
||||
*
|
||||
* - The quicker inlined way: only helps with platform GPIO code
|
||||
* that inlines operations for constant GPIOs. This can give
|
||||
* you tight (fast!) inner loops, but each such bus needs a
|
||||
* new driver. You'll define a new C file, with Makefile and
|
||||
* Kconfig support; the C code can be a total of six lines:
|
||||
*
|
||||
* #define DRIVER_NAME "myboard_spi2"
|
||||
* #define SPI_MISO_GPIO 119
|
||||
* #define SPI_MOSI_GPIO 120
|
||||
* #define SPI_SCK_GPIO 121
|
||||
* #define SPI_N_CHIPSEL 4
|
||||
* #include "spi-gpio.c"
|
||||
*/
|
||||
|
||||
#ifndef DRIVER_NAME
|
||||
#define DRIVER_NAME "spi_gpio"
|
||||
|
||||
#define GENERIC_BITBANG /* vs tight inlines */
|
||||
|
||||
/* all functions referencing these symbols must define pdata */
|
||||
#define SPI_MISO_GPIO ((pdata)->miso)
|
||||
#define SPI_MOSI_GPIO ((pdata)->mosi)
|
||||
#define SPI_SCK_GPIO ((pdata)->sck)
|
||||
|
||||
#define SPI_N_CHIPSEL ((pdata)->num_chipselect)
|
||||
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
static inline struct spi_gpio *__pure
|
||||
spi_to_spi_gpio(const struct spi_device *spi)
|
||||
{
|
||||
const struct spi_bitbang *bang;
|
||||
struct spi_gpio *spi_gpio;
|
||||
|
||||
bang = spi_master_get_devdata(spi->master);
|
||||
spi_gpio = container_of(bang, struct spi_gpio, bitbang);
|
||||
return spi_gpio;
|
||||
}
|
||||
|
||||
static inline struct spi_gpio_platform_data *__pure
|
||||
spi_to_pdata(const struct spi_device *spi)
|
||||
{
|
||||
return &spi_to_spi_gpio(spi)->pdata;
|
||||
}
|
||||
|
||||
/* this is #defined to avoid unused-variable warnings when inlining */
|
||||
#define pdata spi_to_pdata(spi)
|
||||
|
||||
static inline void setsck(const struct spi_device *spi, int is_on)
|
||||
{
|
||||
gpio_set_value_cansleep(SPI_SCK_GPIO, is_on);
|
||||
}
|
||||
|
||||
static inline void setmosi(const struct spi_device *spi, int is_on)
|
||||
{
|
||||
gpio_set_value_cansleep(SPI_MOSI_GPIO, is_on);
|
||||
}
|
||||
|
||||
static inline int getmiso(const struct spi_device *spi)
|
||||
{
|
||||
return !!gpio_get_value_cansleep(SPI_MISO_GPIO);
|
||||
}
|
||||
|
||||
#undef pdata
|
||||
|
||||
/*
|
||||
* NOTE: this clocks "as fast as we can". It "should" be a function of the
|
||||
* requested device clock. Software overhead means we usually have trouble
|
||||
* reaching even one Mbit/sec (except when we can inline bitops), so for now
|
||||
* we'll just assume we never need additional per-bit slowdowns.
|
||||
*/
|
||||
#define spidelay(nsecs) do {} while (0)
|
||||
|
||||
#include "spi-bitbang-txrx.h"
|
||||
|
||||
/*
|
||||
* These functions can leverage inline expansion of GPIO calls to shrink
|
||||
* costs for a txrx bit, often by factors of around ten (by instruction
|
||||
* count). That is particularly visible for larger word sizes, but helps
|
||||
* even with default 8-bit words.
|
||||
*
|
||||
* REVISIT overheads calling these functions for each word also have
|
||||
* significant performance costs. Having txrx_bufs() calls that inline
|
||||
* the txrx_word() logic would help performance, e.g. on larger blocks
|
||||
* used with flash storage or MMC/SD. There should also be ways to make
|
||||
* GCC be less stupid about reloading registers inside the I/O loops,
|
||||
* even without inlined GPIO calls; __attribute__((hot)) on GCC 4.3?
|
||||
*/
|
||||
|
||||
static u32 spi_gpio_txrx_word_mode0(struct spi_device *spi,
|
||||
unsigned nsecs, u32 word, u8 bits)
|
||||
{
|
||||
return bitbang_txrx_be_cpha0(spi, nsecs, 0, 0, word, bits);
|
||||
}
|
||||
|
||||
static u32 spi_gpio_txrx_word_mode1(struct spi_device *spi,
|
||||
unsigned nsecs, u32 word, u8 bits)
|
||||
{
|
||||
return bitbang_txrx_be_cpha1(spi, nsecs, 0, 0, word, bits);
|
||||
}
|
||||
|
||||
static u32 spi_gpio_txrx_word_mode2(struct spi_device *spi,
|
||||
unsigned nsecs, u32 word, u8 bits)
|
||||
{
|
||||
return bitbang_txrx_be_cpha0(spi, nsecs, 1, 0, word, bits);
|
||||
}
|
||||
|
||||
static u32 spi_gpio_txrx_word_mode3(struct spi_device *spi,
|
||||
unsigned nsecs, u32 word, u8 bits)
|
||||
{
|
||||
return bitbang_txrx_be_cpha1(spi, nsecs, 1, 0, word, bits);
|
||||
}
|
||||
|
||||
/*
|
||||
* These functions do not call setmosi or getmiso if respective flag
|
||||
* (SPI_MASTER_NO_RX or SPI_MASTER_NO_TX) is set, so they are safe to
|
||||
* call when such pin is not present or defined in the controller.
|
||||
* A separate set of callbacks is defined to get highest possible
|
||||
* speed in the generic case (when both MISO and MOSI lines are
|
||||
* available), as optimiser will remove the checks when argument is
|
||||
* constant.
|
||||
*/
|
||||
|
||||
static u32 spi_gpio_spec_txrx_word_mode0(struct spi_device *spi,
|
||||
unsigned nsecs, u32 word, u8 bits)
|
||||
{
|
||||
unsigned flags = spi->master->flags;
|
||||
return bitbang_txrx_be_cpha0(spi, nsecs, 0, flags, word, bits);
|
||||
}
|
||||
|
||||
static u32 spi_gpio_spec_txrx_word_mode1(struct spi_device *spi,
|
||||
unsigned nsecs, u32 word, u8 bits)
|
||||
{
|
||||
unsigned flags = spi->master->flags;
|
||||
return bitbang_txrx_be_cpha1(spi, nsecs, 0, flags, word, bits);
|
||||
}
|
||||
|
||||
static u32 spi_gpio_spec_txrx_word_mode2(struct spi_device *spi,
|
||||
unsigned nsecs, u32 word, u8 bits)
|
||||
{
|
||||
unsigned flags = spi->master->flags;
|
||||
return bitbang_txrx_be_cpha0(spi, nsecs, 1, flags, word, bits);
|
||||
}
|
||||
|
||||
static u32 spi_gpio_spec_txrx_word_mode3(struct spi_device *spi,
|
||||
unsigned nsecs, u32 word, u8 bits)
|
||||
{
|
||||
unsigned flags = spi->master->flags;
|
||||
return bitbang_txrx_be_cpha1(spi, nsecs, 1, flags, word, bits);
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
static void spi_gpio_chipselect(struct spi_device *spi, int is_active)
|
||||
{
|
||||
struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi);
|
||||
unsigned long cs = spi_gpio->cs_gpios[spi->chip_select];
|
||||
|
||||
/* set initial clock polarity */
|
||||
if (is_active)
|
||||
setsck(spi, spi->mode & SPI_CPOL);
|
||||
|
||||
if (cs != SPI_GPIO_NO_CHIPSELECT) {
|
||||
/* SPI is normally active-low */
|
||||
gpio_set_value_cansleep(cs, (spi->mode & SPI_CS_HIGH) ? is_active : !is_active);
|
||||
}
|
||||
}
|
||||
|
||||
static int spi_gpio_setup(struct spi_device *spi)
|
||||
{
|
||||
unsigned long cs;
|
||||
int status = 0;
|
||||
struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi);
|
||||
struct device_node *np = spi->master->dev.of_node;
|
||||
|
||||
if (np) {
|
||||
/*
|
||||
* In DT environments, the CS GPIOs have already been
|
||||
* initialized from the "cs-gpios" property of the node.
|
||||
*/
|
||||
cs = spi_gpio->cs_gpios[spi->chip_select];
|
||||
} else {
|
||||
/*
|
||||
* ... otherwise, take it from spi->controller_data
|
||||
*/
|
||||
cs = (uintptr_t) spi->controller_data;
|
||||
}
|
||||
|
||||
if (!spi->controller_state) {
|
||||
if (cs != SPI_GPIO_NO_CHIPSELECT) {
|
||||
status = gpio_request(cs, dev_name(&spi->dev));
|
||||
if (status)
|
||||
return status;
|
||||
status = gpio_direction_output(cs,
|
||||
!(spi->mode & SPI_CS_HIGH));
|
||||
}
|
||||
}
|
||||
if (!status) {
|
||||
/* in case it was initialized from static board data */
|
||||
spi_gpio->cs_gpios[spi->chip_select] = cs;
|
||||
status = spi_bitbang_setup(spi);
|
||||
}
|
||||
|
||||
if (status) {
|
||||
if (!spi->controller_state && cs != SPI_GPIO_NO_CHIPSELECT)
|
||||
gpio_free(cs);
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
static void spi_gpio_cleanup(struct spi_device *spi)
|
||||
{
|
||||
struct spi_gpio *spi_gpio = spi_to_spi_gpio(spi);
|
||||
unsigned long cs = spi_gpio->cs_gpios[spi->chip_select];
|
||||
|
||||
if (cs != SPI_GPIO_NO_CHIPSELECT)
|
||||
gpio_free(cs);
|
||||
spi_bitbang_cleanup(spi);
|
||||
}
|
||||
|
||||
static int spi_gpio_alloc(unsigned pin, const char *label, bool is_in)
|
||||
{
|
||||
int value;
|
||||
|
||||
value = gpio_request(pin, label);
|
||||
if (value == 0) {
|
||||
if (is_in)
|
||||
value = gpio_direction_input(pin);
|
||||
else
|
||||
value = gpio_direction_output(pin, 0);
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
static int spi_gpio_request(struct spi_gpio_platform_data *pdata,
|
||||
const char *label, u16 *res_flags)
|
||||
{
|
||||
int value;
|
||||
|
||||
/* NOTE: SPI_*_GPIO symbols may reference "pdata" */
|
||||
|
||||
if (SPI_MOSI_GPIO != SPI_GPIO_NO_MOSI) {
|
||||
value = spi_gpio_alloc(SPI_MOSI_GPIO, label, false);
|
||||
if (value)
|
||||
goto done;
|
||||
} else {
|
||||
/* HW configuration without MOSI pin */
|
||||
*res_flags |= SPI_MASTER_NO_TX;
|
||||
}
|
||||
|
||||
if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO) {
|
||||
value = spi_gpio_alloc(SPI_MISO_GPIO, label, true);
|
||||
if (value)
|
||||
goto free_mosi;
|
||||
} else {
|
||||
/* HW configuration without MISO pin */
|
||||
*res_flags |= SPI_MASTER_NO_RX;
|
||||
}
|
||||
|
||||
value = spi_gpio_alloc(SPI_SCK_GPIO, label, false);
|
||||
if (value)
|
||||
goto free_miso;
|
||||
|
||||
goto done;
|
||||
|
||||
free_miso:
|
||||
if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO)
|
||||
gpio_free(SPI_MISO_GPIO);
|
||||
free_mosi:
|
||||
if (SPI_MOSI_GPIO != SPI_GPIO_NO_MOSI)
|
||||
gpio_free(SPI_MOSI_GPIO);
|
||||
done:
|
||||
return value;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static const struct of_device_id spi_gpio_dt_ids[] = {
|
||||
{ .compatible = "spi-gpio" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, spi_gpio_dt_ids);
|
||||
|
||||
static int spi_gpio_probe_dt(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
u32 tmp;
|
||||
struct spi_gpio_platform_data *pdata;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
const struct of_device_id *of_id =
|
||||
of_match_device(spi_gpio_dt_ids, &pdev->dev);
|
||||
|
||||
if (!of_id)
|
||||
return 0;
|
||||
|
||||
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
|
||||
if (!pdata)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = of_get_named_gpio(np, "gpio-sck", 0);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "gpio-sck property not found\n");
|
||||
goto error_free;
|
||||
}
|
||||
pdata->sck = ret;
|
||||
|
||||
ret = of_get_named_gpio(np, "gpio-miso", 0);
|
||||
if (ret < 0) {
|
||||
dev_info(&pdev->dev, "gpio-miso property not found, switching to no-rx mode\n");
|
||||
pdata->miso = SPI_GPIO_NO_MISO;
|
||||
} else
|
||||
pdata->miso = ret;
|
||||
|
||||
ret = of_get_named_gpio(np, "gpio-mosi", 0);
|
||||
if (ret < 0) {
|
||||
dev_info(&pdev->dev, "gpio-mosi property not found, switching to no-tx mode\n");
|
||||
pdata->mosi = SPI_GPIO_NO_MOSI;
|
||||
} else
|
||||
pdata->mosi = ret;
|
||||
|
||||
ret = of_property_read_u32(np, "num-chipselects", &tmp);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "num-chipselects property not found\n");
|
||||
goto error_free;
|
||||
}
|
||||
|
||||
pdata->num_chipselect = tmp;
|
||||
pdev->dev.platform_data = pdata;
|
||||
|
||||
return 1;
|
||||
|
||||
error_free:
|
||||
devm_kfree(&pdev->dev, pdata);
|
||||
return ret;
|
||||
}
|
||||
#else
|
||||
static inline int spi_gpio_probe_dt(struct platform_device *pdev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int spi_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
int status;
|
||||
struct spi_master *master;
|
||||
struct spi_gpio *spi_gpio;
|
||||
struct spi_gpio_platform_data *pdata;
|
||||
u16 master_flags = 0;
|
||||
bool use_of = 0;
|
||||
int num_devices;
|
||||
|
||||
status = spi_gpio_probe_dt(pdev);
|
||||
if (status < 0)
|
||||
return status;
|
||||
if (status > 0)
|
||||
use_of = 1;
|
||||
|
||||
pdata = dev_get_platdata(&pdev->dev);
|
||||
#ifdef GENERIC_BITBANG
|
||||
if (!pdata || (!use_of && !pdata->num_chipselect))
|
||||
return -ENODEV;
|
||||
#endif
|
||||
|
||||
if (use_of && !SPI_N_CHIPSEL)
|
||||
num_devices = 1;
|
||||
else
|
||||
num_devices = SPI_N_CHIPSEL;
|
||||
|
||||
status = spi_gpio_request(pdata, dev_name(&pdev->dev), &master_flags);
|
||||
if (status < 0)
|
||||
return status;
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(*spi_gpio) +
|
||||
(sizeof(unsigned long) * num_devices));
|
||||
if (!master) {
|
||||
status = -ENOMEM;
|
||||
goto gpio_free;
|
||||
}
|
||||
spi_gpio = spi_master_get_devdata(master);
|
||||
platform_set_drvdata(pdev, spi_gpio);
|
||||
|
||||
spi_gpio->pdev = pdev;
|
||||
if (pdata)
|
||||
spi_gpio->pdata = *pdata;
|
||||
|
||||
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
|
||||
master->flags = master_flags;
|
||||
master->bus_num = pdev->id;
|
||||
master->num_chipselect = num_devices;
|
||||
master->setup = spi_gpio_setup;
|
||||
master->cleanup = spi_gpio_cleanup;
|
||||
#ifdef CONFIG_OF
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
|
||||
if (use_of) {
|
||||
int i;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
|
||||
/*
|
||||
* In DT environments, take the CS GPIO from the "cs-gpios"
|
||||
* property of the node.
|
||||
*/
|
||||
|
||||
if (!SPI_N_CHIPSEL)
|
||||
spi_gpio->cs_gpios[0] = SPI_GPIO_NO_CHIPSELECT;
|
||||
else
|
||||
for (i = 0; i < SPI_N_CHIPSEL; i++) {
|
||||
status = of_get_named_gpio(np, "cs-gpios", i);
|
||||
if (status < 0) {
|
||||
dev_err(&pdev->dev,
|
||||
"invalid cs-gpios property\n");
|
||||
goto gpio_free;
|
||||
}
|
||||
spi_gpio->cs_gpios[i] = status;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
spi_gpio->bitbang.master = master;
|
||||
spi_gpio->bitbang.chipselect = spi_gpio_chipselect;
|
||||
|
||||
if ((master_flags & (SPI_MASTER_NO_TX | SPI_MASTER_NO_RX)) == 0) {
|
||||
spi_gpio->bitbang.txrx_word[SPI_MODE_0] = spi_gpio_txrx_word_mode0;
|
||||
spi_gpio->bitbang.txrx_word[SPI_MODE_1] = spi_gpio_txrx_word_mode1;
|
||||
spi_gpio->bitbang.txrx_word[SPI_MODE_2] = spi_gpio_txrx_word_mode2;
|
||||
spi_gpio->bitbang.txrx_word[SPI_MODE_3] = spi_gpio_txrx_word_mode3;
|
||||
} else {
|
||||
spi_gpio->bitbang.txrx_word[SPI_MODE_0] = spi_gpio_spec_txrx_word_mode0;
|
||||
spi_gpio->bitbang.txrx_word[SPI_MODE_1] = spi_gpio_spec_txrx_word_mode1;
|
||||
spi_gpio->bitbang.txrx_word[SPI_MODE_2] = spi_gpio_spec_txrx_word_mode2;
|
||||
spi_gpio->bitbang.txrx_word[SPI_MODE_3] = spi_gpio_spec_txrx_word_mode3;
|
||||
}
|
||||
spi_gpio->bitbang.setup_transfer = spi_bitbang_setup_transfer;
|
||||
spi_gpio->bitbang.flags = SPI_CS_HIGH;
|
||||
|
||||
status = spi_bitbang_start(&spi_gpio->bitbang);
|
||||
if (status < 0) {
|
||||
gpio_free:
|
||||
if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO)
|
||||
gpio_free(SPI_MISO_GPIO);
|
||||
if (SPI_MOSI_GPIO != SPI_GPIO_NO_MOSI)
|
||||
gpio_free(SPI_MOSI_GPIO);
|
||||
gpio_free(SPI_SCK_GPIO);
|
||||
spi_master_put(master);
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static int spi_gpio_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_gpio *spi_gpio;
|
||||
struct spi_gpio_platform_data *pdata;
|
||||
|
||||
spi_gpio = platform_get_drvdata(pdev);
|
||||
pdata = dev_get_platdata(&pdev->dev);
|
||||
|
||||
/* stop() unregisters child devices too */
|
||||
spi_bitbang_stop(&spi_gpio->bitbang);
|
||||
|
||||
if (SPI_MISO_GPIO != SPI_GPIO_NO_MISO)
|
||||
gpio_free(SPI_MISO_GPIO);
|
||||
if (SPI_MOSI_GPIO != SPI_GPIO_NO_MOSI)
|
||||
gpio_free(SPI_MOSI_GPIO);
|
||||
gpio_free(SPI_SCK_GPIO);
|
||||
spi_master_put(spi_gpio->bitbang.master);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
MODULE_ALIAS("platform:" DRIVER_NAME);
|
||||
|
||||
static struct platform_driver spi_gpio_driver = {
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.of_match_table = of_match_ptr(spi_gpio_dt_ids),
|
||||
},
|
||||
.probe = spi_gpio_probe,
|
||||
.remove = spi_gpio_remove,
|
||||
};
|
||||
module_platform_driver(spi_gpio_driver);
|
||||
|
||||
MODULE_DESCRIPTION("SPI master driver using generic bitbanged GPIO ");
|
||||
MODULE_AUTHOR("David Brownell");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -78,11 +78,11 @@ struct spi_gpio {
|
|||
#define GENERIC_BITBANG /* vs tight inlines */
|
||||
|
||||
/* all functions referencing these symbols must define pdata */
|
||||
#define SPI_MISO_GPIO 507 //((pdata)->miso)
|
||||
#define SPI_MOSI_GPIO 509 //((pdata)->mosi)
|
||||
#define SPI_SCK_GPIO 510 //((pdata)->sck)
|
||||
#define SPI_MISO_GPIO ((pdata)->miso)
|
||||
#define SPI_MOSI_GPIO ((pdata)->mosi)
|
||||
#define SPI_SCK_GPIO ((pdata)->sck)
|
||||
|
||||
#define SPI_N_CHIPSEL 508 //((pdata)->num_chipselect)
|
||||
#define SPI_N_CHIPSEL ((pdata)->num_chipselect)
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -575,7 +575,6 @@ struct qman_portal *qman_create_portal(
|
|||
char buf[16];
|
||||
int ret;
|
||||
u32 isdr;
|
||||
struct platform_device_info pdev_info;
|
||||
|
||||
if (!portal) {
|
||||
portal = kmalloc(sizeof(*portal), GFP_KERNEL);
|
||||
|
|
@ -672,22 +671,27 @@ struct qman_portal *qman_create_portal(
|
|||
portal->dqrr_disable_ref = 0;
|
||||
portal->cb_dc_ern = NULL;
|
||||
sprintf(buf, "qportal-%d", config->public_cfg.channel);
|
||||
|
||||
memset(&pdev_info, 0, sizeof(pdev_info));
|
||||
pdev_info.name = buf;
|
||||
pdev_info.id = PLATFORM_DEVID_NONE;
|
||||
pdev_info.dma_mask = DMA_BIT_MASK(40);
|
||||
|
||||
portal->pdev = platform_device_register_full(&pdev_info);
|
||||
portal->pdev = platform_device_alloc(buf, -1);
|
||||
if (!portal->pdev) {
|
||||
pr_err("qman_portal - platform_device_alloc() failed\n");
|
||||
goto fail_devregister;
|
||||
goto fail_devalloc;
|
||||
}
|
||||
|
||||
arch_setup_dma_ops(&portal->pdev->dev, 0, 0, NULL, true);
|
||||
|
||||
#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
|
||||
portal->pdev->dev.coherent_dma_mask = DMA_BIT_MASK(40);
|
||||
portal->pdev->dev.dma_mask = &portal->pdev->dev.coherent_dma_mask;
|
||||
#else
|
||||
if (dma_set_mask(&portal->pdev->dev, DMA_BIT_MASK(40))) {
|
||||
pr_err("qman_portal - dma_set_mask() failed\n");
|
||||
goto fail_devadd;
|
||||
}
|
||||
#endif
|
||||
portal->pdev->dev.pm_domain = &qman_portal_device_pm_domain;
|
||||
portal->pdev->dev.platform_data = portal;
|
||||
ret = platform_device_add(portal->pdev);
|
||||
if (ret) {
|
||||
pr_err("qman_portal - platform_device_add() failed\n");
|
||||
goto fail_devadd;
|
||||
}
|
||||
dpa_rbtree_init(&portal->retire_table);
|
||||
isdr = 0xffffffff;
|
||||
qm_isr_disable_write(__p, isdr);
|
||||
|
|
@ -747,8 +751,10 @@ fail_eqcr_empty:
|
|||
fail_affinity:
|
||||
free_irq(config->public_cfg.irq, portal);
|
||||
fail_irq:
|
||||
platform_device_unregister(portal->pdev);
|
||||
fail_devregister:
|
||||
platform_device_del(portal->pdev);
|
||||
fail_devadd:
|
||||
platform_device_put(portal->pdev);
|
||||
fail_devalloc:
|
||||
if (num_ceetms)
|
||||
for (ret = 0; ret < num_ceetms; ret++)
|
||||
kfree(portal->ccgrs[ret]);
|
||||
|
|
@ -1803,11 +1809,6 @@ int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
|
|||
} else {
|
||||
phys_fq = dma_map_single(&p->pdev->dev, fq, sizeof(*fq),
|
||||
DMA_TO_DEVICE);
|
||||
if (dma_mapping_error(&p->pdev->dev, phys_fq))
|
||||
dev_err(&p->pdev->dev,
|
||||
"dma_map_single failed for fqid: %u\n",
|
||||
fq->fqid);
|
||||
|
||||
qm_fqd_stashing_set64(&mcc->initfq.fqd, phys_fq);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -575,7 +575,7 @@ static void option_instat_callback(struct urb *urb);
|
|||
static const struct usb_device_id option_ids[] = {
|
||||
/*add USB DEVICE for ZTE_LTE*/
|
||||
{ USB_DEVICE(ZTE_VENDOR_ID, OPTION_PRODUCT_ZTE_LTE_1476) },
|
||||
|
||||
{ USB_DEVICE(0x1508, 0x1001) },
|
||||
{ USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_COLT) },
|
||||
{ USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_RICOLA) },
|
||||
{ USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_RICOLA_LIGHT) },
|
||||
|
|
|
|||
|
|
@ -0,0 +1,124 @@
|
|||
#
|
||||
# Huachen hcenDEV drivers
|
||||
#
|
||||
|
||||
config HCDEV_GPIO_SYSFS
|
||||
tristate "HCENDEV gpio leds"
|
||||
select GPIO_SYSFS
|
||||
select GPIO_MPC8XXX
|
||||
select LEDS_USER
|
||||
select LEDS_TRIGGER_TIMER
|
||||
select LEDS_TRIGGER_ONESHOT
|
||||
select LEDS_TRIGGER_GPIO
|
||||
default y
|
||||
help
|
||||
HCENDEV gpio leds drivers
|
||||
|
||||
config HCDEV_GPIO_LED
|
||||
tristate "HCENDEV gpio leds"
|
||||
depends on HCDEV_GPIO_SYSFS
|
||||
default y
|
||||
help
|
||||
HCEN1004A gpio keys drivers
|
||||
|
||||
config HCDEV_GPIO_KEY
|
||||
tristate "HCENDEV gpio keys"
|
||||
depends on HCDEV_GPIO_SYSFS
|
||||
default y
|
||||
help
|
||||
HCEN1004A gpio keys drivers
|
||||
|
||||
config HCENDEV_GPIO_I2C
|
||||
tristate "HCENDEV gpio i2c "
|
||||
select I2C
|
||||
select I2C_ALGOBIT
|
||||
select I2C_GPIO
|
||||
depends on HCDEV_GPIO_SYSFS
|
||||
help
|
||||
HCENDEV gpio i2c drivers
|
||||
|
||||
config HCENDEV_WIRELESS
|
||||
tristate "HCENDEV wireless card"
|
||||
select EXPERT
|
||||
select CFG80211
|
||||
select CFG80211_CERTIFICATION_ONUS
|
||||
select CFG80211_CRDA_SUPPORT
|
||||
select CFG80211_INTERNAL_REGDB
|
||||
select CFG80211_REG_CELLULAR_HINTS
|
||||
select CFG80211_REG_RELAX_NO_IR
|
||||
select CFG80211_WEXT
|
||||
select CFG80211_WEXT_EXPORT
|
||||
select IPW2200
|
||||
select MAC80211
|
||||
select MAC80211_HAS_RC
|
||||
select MAC80211_LEDS
|
||||
select MAC80211_MESH
|
||||
select MAC80211_RC_DEFAULT_MINSTREL
|
||||
select MAC80211_RC_MINSTREL
|
||||
select MAC80211_RC_MINSTREL_HT
|
||||
select MAC80211_RC_MINSTREL_VHT
|
||||
select NETDEVICES
|
||||
select WLAN
|
||||
select RFKILL
|
||||
select WLAN_VENDOR_ATH
|
||||
select WLAN_VENDOR_INTEL
|
||||
select IPW2100
|
||||
help
|
||||
this is fuction support for wireless
|
||||
|
||||
config HCENDEV_ATH9k_SERIES
|
||||
tristate "HCENDEV ath9k support"
|
||||
depends on HCENDEV_WIRELESS
|
||||
select ATH9K
|
||||
select ATH9K_AHB
|
||||
select ATH9K_CHANNEL_CONTEXT
|
||||
select ATH9K_COMMON
|
||||
select ATH9K_DFS_CERTIFIED
|
||||
select ATH9K_DYNACK
|
||||
select ATH9K_HW
|
||||
select ATH9K_HWRNG
|
||||
select ATH9K_PCI
|
||||
select ATH9K_RFKILL
|
||||
select ATH9K_DEBUGFS
|
||||
help
|
||||
HCENDEV support for ath9k series
|
||||
|
||||
config HCENDEV_ATH10k_SERIES
|
||||
tristate "HCENDEV ath10k support"
|
||||
depends on HCENDEV_WIRELESS
|
||||
select ATH10K
|
||||
select ATH10K_AHB
|
||||
select ATH10K_DFS_CERTIFIED
|
||||
select ATH10K_PCI
|
||||
help
|
||||
HCENDEV support for QCA6174
|
||||
|
||||
config HCENDEV_LTE
|
||||
tristate "HCENDEV lte function enable"
|
||||
select PPP
|
||||
select PPP_BSDCOMP
|
||||
select PPP_DEFLATE
|
||||
select PPP_FILTER
|
||||
select PPP_MPPE
|
||||
select PPP_MULTILINK
|
||||
select PPPOE
|
||||
select PPP_ASYNC
|
||||
select PPP_SYNC_TTY
|
||||
select SLHC
|
||||
select CRC_CCITT
|
||||
select USB_ACM
|
||||
select USB_SERIAL
|
||||
select USB_SERIAL_WWAN
|
||||
select USB_SERIAL_OPTION
|
||||
select USB_NET_DRIVERS
|
||||
select USB_USBNET
|
||||
select USB_NET_CDCETHER
|
||||
select USB_NET_CDC_EEM
|
||||
select USB_NET_CDC_NCM
|
||||
select USB_NET_CDC_SUBSET_ENABLE
|
||||
select USB_NET_CDC_SUBSET
|
||||
select USB_WDM
|
||||
help
|
||||
HCENDEV support for LTE
|
||||
|
||||
|
||||
|
|
@ -17,9 +17,7 @@
|
|||
#define MARVELL_PHY_ID_88E1318S 0x01410e90
|
||||
#define MARVELL_PHY_ID_88E1116R 0x01410e40
|
||||
#define MARVELL_PHY_ID_88E1510 0x01410dd0
|
||||
#define MARVELL_PHY_ID_88E1512 0x01410dd1
|
||||
#define MARVELL_PHY_ID_88E1540 0x01410eb0
|
||||
#define MARVELL_PHY_ID_88E1543 0x01410ea2
|
||||
#define MARVELL_PHY_ID_88E1545 0x01410ea0
|
||||
#define MARVELL_PHY_ID_88E3016 0x01410e60
|
||||
|
||||
|
|
|
|||
|
|
@ -47,14 +47,6 @@ union nf_conntrack_expect_proto {
|
|||
#include <net/netfilter/ipv4/nf_conntrack_ipv4.h>
|
||||
#include <net/netfilter/ipv6/nf_conntrack_ipv6.h>
|
||||
|
||||
struct cmhi_ext_info {
|
||||
uint16_t user_version;
|
||||
uint16_t app_id;
|
||||
uint32_t user_id;
|
||||
uint32_t node_index;
|
||||
uint32_t policy_version;
|
||||
uint32_t action;
|
||||
};
|
||||
struct nf_conn {
|
||||
/* Usage count in here is 1 for hash table, 1 per skb,
|
||||
* plus 1 for any connection(s) we are `master' for
|
||||
|
|
@ -106,9 +98,6 @@ struct nf_conn {
|
|||
|
||||
/* Storage reserved for other modules, must be the last member */
|
||||
union nf_conntrack_proto proto;
|
||||
|
||||
/* add by wuqi@cmhi */
|
||||
struct cmhi_ext_info cmhi;
|
||||
};
|
||||
|
||||
static inline struct nf_conn *
|
||||
|
|
|
|||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Copyright (C) 2016-2017 Synopsys, Inc. (www.synopsys.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __SOC_ARC_AUX_H__
|
||||
#define __SOC_ARC_AUX_H__
|
||||
|
||||
#ifdef CONFIG_ARC
|
||||
|
||||
#define read_aux_reg(r) __builtin_arc_lr(r)
|
||||
|
||||
/* gcc builtin sr needs reg param to be long immediate */
|
||||
#define write_aux_reg(r, v) __builtin_arc_sr((unsigned int)(v), r)
|
||||
|
||||
#else /* !CONFIG_ARC */
|
||||
|
||||
static inline int read_aux_reg(u32 r)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* function helps elide unused variable warning
|
||||
* see: http://lists.infradead.org/pipermail/linux-snps-arc/2016-November/001748.html
|
||||
*/
|
||||
static inline void write_aux_reg(u32 r, u32 v)
|
||||
{
|
||||
;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#define READ_BCR(reg, into) \
|
||||
{ \
|
||||
unsigned int tmp; \
|
||||
tmp = read_aux_reg(reg); \
|
||||
if (sizeof(tmp) == sizeof(into)) { \
|
||||
into = *((typeof(into) *)&tmp); \
|
||||
} else { \
|
||||
extern void bogus_undefined(void); \
|
||||
bogus_undefined(); \
|
||||
} \
|
||||
}
|
||||
|
||||
#define WRITE_AUX(reg, into) \
|
||||
{ \
|
||||
unsigned int tmp; \
|
||||
if (sizeof(tmp) == sizeof(into)) { \
|
||||
tmp = (*(unsigned int *)&(into)); \
|
||||
write_aux_reg(reg, tmp); \
|
||||
} else { \
|
||||
extern void bogus_undefined(void); \
|
||||
bogus_undefined(); \
|
||||
} \
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -1,32 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
|
||||
#ifndef _XT_CONNMARK_H
|
||||
#define _XT_CONNMARK_H
|
||||
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
#ifndef _XT_CONNMARK_H_target
|
||||
#define _XT_CONNMARK_H_target
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/netfilter/xt_connmark.h>
|
||||
|
||||
/* Copyright (C) 2002,2004 MARA Systems AB <http://www.marasystems.com>
|
||||
* by Henrik Nordstrom <hno@marasystems.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
enum {
|
||||
XT_CONNMARK_SET = 0,
|
||||
XT_CONNMARK_SAVE,
|
||||
XT_CONNMARK_RESTORE
|
||||
};
|
||||
|
||||
struct xt_connmark_tginfo1 {
|
||||
__u32 ctmark, ctmask, nfmask;
|
||||
__u8 mode;
|
||||
};
|
||||
|
||||
struct xt_connmark_mtinfo1 {
|
||||
__u32 mark, mask;
|
||||
__u8 invert;
|
||||
};
|
||||
|
||||
#endif /*_XT_CONNMARK_H*/
|
||||
#endif /*_XT_CONNMARK_H_target*/
|
||||
|
|
|
|||
|
|
@ -1,32 +1,27 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
/* x_tables module for matching the IPv4/IPv6 DSCP field
|
||||
/* x_tables module for setting the IPv4/IPv6 DSCP field
|
||||
*
|
||||
* (C) 2002 Harald Welte <laforge@gnumonks.org>
|
||||
* based on ipt_FTOS.c (C) 2000 by Matthew G. Marsh <mgm@paktronix.com>
|
||||
* This software is distributed under GNU GPL v2, 1991
|
||||
*
|
||||
* See RFC2474 for a description of the DSCP field within the IP Header.
|
||||
*
|
||||
* xt_dscp.h,v 1.3 2002/08/05 19:00:21 laforge Exp
|
||||
* xt_DSCP.h,v 1.7 2002/03/14 12:03:13 laforge Exp
|
||||
*/
|
||||
#ifndef _XT_DSCP_H
|
||||
#define _XT_DSCP_H
|
||||
|
||||
#ifndef _XT_DSCP_TARGET_H
|
||||
#define _XT_DSCP_TARGET_H
|
||||
#include <linux/netfilter/xt_dscp.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#define XT_DSCP_MASK 0xfc /* 11111100 */
|
||||
#define XT_DSCP_SHIFT 2
|
||||
#define XT_DSCP_MAX 0x3f /* 00111111 */
|
||||
|
||||
/* match info */
|
||||
struct xt_dscp_info {
|
||||
/* target info */
|
||||
struct xt_DSCP_info {
|
||||
__u8 dscp;
|
||||
__u8 invert;
|
||||
};
|
||||
|
||||
struct xt_tos_match_info {
|
||||
__u8 tos_mask;
|
||||
struct xt_tos_target_info {
|
||||
__u8 tos_value;
|
||||
__u8 invert;
|
||||
__u8 tos_mask;
|
||||
};
|
||||
|
||||
#endif /* _XT_DSCP_H */
|
||||
#endif /* _XT_DSCP_TARGET_H */
|
||||
|
|
|
|||
|
|
@ -1,16 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
#ifndef _XT_MARK_H
|
||||
#define _XT_MARK_H
|
||||
#ifndef _XT_MARK_H_target
|
||||
#define _XT_MARK_H_target
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/netfilter/xt_mark.h>
|
||||
|
||||
struct xt_mark_tginfo2 {
|
||||
__u32 mark, mask;
|
||||
};
|
||||
|
||||
struct xt_mark_mtinfo1 {
|
||||
__u32 mark, mask;
|
||||
__u8 invert;
|
||||
};
|
||||
|
||||
#endif /*_XT_MARK_H*/
|
||||
#endif /*_XT_MARK_H_target */
|
||||
|
|
|
|||
|
|
@ -1,39 +1,17 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
#ifndef _XT_RATEEST_MATCH_H
|
||||
#define _XT_RATEEST_MATCH_H
|
||||
#ifndef _XT_RATEEST_TARGET_H
|
||||
#define _XT_RATEEST_TARGET_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/if.h>
|
||||
|
||||
enum xt_rateest_match_flags {
|
||||
XT_RATEEST_MATCH_INVERT = 1<<0,
|
||||
XT_RATEEST_MATCH_ABS = 1<<1,
|
||||
XT_RATEEST_MATCH_REL = 1<<2,
|
||||
XT_RATEEST_MATCH_DELTA = 1<<3,
|
||||
XT_RATEEST_MATCH_BPS = 1<<4,
|
||||
XT_RATEEST_MATCH_PPS = 1<<5,
|
||||
};
|
||||
|
||||
enum xt_rateest_match_mode {
|
||||
XT_RATEEST_MATCH_NONE,
|
||||
XT_RATEEST_MATCH_EQ,
|
||||
XT_RATEEST_MATCH_LT,
|
||||
XT_RATEEST_MATCH_GT,
|
||||
};
|
||||
|
||||
struct xt_rateest_match_info {
|
||||
char name1[IFNAMSIZ];
|
||||
char name2[IFNAMSIZ];
|
||||
__u16 flags;
|
||||
__u16 mode;
|
||||
__u32 bps1;
|
||||
__u32 pps1;
|
||||
__u32 bps2;
|
||||
__u32 pps2;
|
||||
struct xt_rateest_target_info {
|
||||
char name[IFNAMSIZ];
|
||||
__s8 interval;
|
||||
__u8 ewma_log;
|
||||
|
||||
/* Used internally by the kernel */
|
||||
struct xt_rateest *est1 __attribute__((aligned(8)));
|
||||
struct xt_rateest *est2 __attribute__((aligned(8)));
|
||||
struct xt_rateest *est __attribute__((aligned(8)));
|
||||
};
|
||||
|
||||
#endif /* _XT_RATEEST_MATCH_H */
|
||||
#endif /* _XT_RATEEST_TARGET_H */
|
||||
|
|
|
|||
|
|
@ -1,12 +1,13 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
#ifndef _XT_TCPMSS_MATCH_H
|
||||
#define _XT_TCPMSS_MATCH_H
|
||||
#ifndef _XT_TCPMSS_H
|
||||
#define _XT_TCPMSS_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct xt_tcpmss_match_info {
|
||||
__u16 mss_min, mss_max;
|
||||
__u8 invert;
|
||||
struct xt_tcpmss_info {
|
||||
__u16 mss;
|
||||
};
|
||||
|
||||
#endif /*_XT_TCPMSS_MATCH_H*/
|
||||
#define XT_TCPMSS_CLAMP_PMTU 0xffff
|
||||
|
||||
#endif /* _XT_TCPMSS_H */
|
||||
|
|
|
|||
|
|
@ -1,16 +1,34 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
#ifndef _IPT_ECN_H
|
||||
#define _IPT_ECN_H
|
||||
/* Header file for iptables ipt_ECN target
|
||||
*
|
||||
* (C) 2002 by Harald Welte <laforge@gnumonks.org>
|
||||
*
|
||||
* This software is distributed under GNU GPL v2, 1991
|
||||
*
|
||||
* ipt_ECN.h,v 1.3 2002/05/29 12:17:40 laforge Exp
|
||||
*/
|
||||
#ifndef _IPT_ECN_TARGET_H
|
||||
#define _IPT_ECN_TARGET_H
|
||||
|
||||
#include <linux/netfilter/xt_ecn.h>
|
||||
#define ipt_ecn_info xt_ecn_info
|
||||
#include <linux/types.h>
|
||||
#include <linux/netfilter/xt_DSCP.h>
|
||||
|
||||
enum {
|
||||
IPT_ECN_IP_MASK = XT_ECN_IP_MASK,
|
||||
IPT_ECN_OP_MATCH_IP = XT_ECN_OP_MATCH_IP,
|
||||
IPT_ECN_OP_MATCH_ECE = XT_ECN_OP_MATCH_ECE,
|
||||
IPT_ECN_OP_MATCH_CWR = XT_ECN_OP_MATCH_CWR,
|
||||
IPT_ECN_OP_MATCH_MASK = XT_ECN_OP_MATCH_MASK,
|
||||
#define IPT_ECN_IP_MASK (~XT_DSCP_MASK)
|
||||
|
||||
#define IPT_ECN_OP_SET_IP 0x01 /* set ECN bits of IPv4 header */
|
||||
#define IPT_ECN_OP_SET_ECE 0x10 /* set ECE bit of TCP header */
|
||||
#define IPT_ECN_OP_SET_CWR 0x20 /* set CWR bit of TCP header */
|
||||
|
||||
#define IPT_ECN_OP_MASK 0xce
|
||||
|
||||
struct ipt_ECN_info {
|
||||
__u8 operation; /* bitset of operations */
|
||||
__u8 ip_ect; /* ECT codepoint of IPv4 header, pre-shifted */
|
||||
union {
|
||||
struct {
|
||||
__u8 ece:1, cwr:1; /* TCP ECT bits */
|
||||
} tcp;
|
||||
} proto;
|
||||
};
|
||||
|
||||
#endif /* IPT_ECN_H */
|
||||
#endif /* _IPT_ECN_TARGET_H */
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
/* IP tables module for matching the value of the TTL
|
||||
* (C) 2000 by Harald Welte <laforge@gnumonks.org> */
|
||||
/* TTL modification module for IP tables
|
||||
* (C) 2000 by Harald Welte <laforge@netfilter.org> */
|
||||
|
||||
#ifndef _IPT_TTL_H
|
||||
#define _IPT_TTL_H
|
||||
|
|
@ -8,14 +8,14 @@
|
|||
#include <linux/types.h>
|
||||
|
||||
enum {
|
||||
IPT_TTL_EQ = 0, /* equals */
|
||||
IPT_TTL_NE, /* not equals */
|
||||
IPT_TTL_LT, /* less than */
|
||||
IPT_TTL_GT, /* greater than */
|
||||
IPT_TTL_SET = 0,
|
||||
IPT_TTL_INC,
|
||||
IPT_TTL_DEC
|
||||
};
|
||||
|
||||
#define IPT_TTL_MAXMODE IPT_TTL_DEC
|
||||
|
||||
struct ipt_ttl_info {
|
||||
struct ipt_TTL_info {
|
||||
__u8 mode;
|
||||
__u8 ttl;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
|
||||
/* ip6tables module for matching the Hop Limit value
|
||||
/* Hop Limit modification module for ip6tables
|
||||
* Maciej Soltysiak <solt@dns.toxicfilms.tv>
|
||||
* Based on HW's ttl module */
|
||||
* Based on HW's TTL module */
|
||||
|
||||
#ifndef _IP6T_HL_H
|
||||
#define _IP6T_HL_H
|
||||
|
|
@ -9,14 +9,14 @@
|
|||
#include <linux/types.h>
|
||||
|
||||
enum {
|
||||
IP6T_HL_EQ = 0, /* equals */
|
||||
IP6T_HL_NE, /* not equals */
|
||||
IP6T_HL_LT, /* less than */
|
||||
IP6T_HL_GT, /* greater than */
|
||||
IP6T_HL_SET = 0,
|
||||
IP6T_HL_INC,
|
||||
IP6T_HL_DEC
|
||||
};
|
||||
|
||||
#define IP6T_HL_MAXMODE IP6T_HL_DEC
|
||||
|
||||
struct ip6t_hl_info {
|
||||
struct ip6t_HL_info {
|
||||
__u8 mode;
|
||||
__u8 hop_limit;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -39,9 +39,9 @@
|
|||
};
|
||||
};
|
||||
|
||||
hcen1002-dtb {
|
||||
description = "hcen1002-dtb";
|
||||
data = /incbin/("arch/arm64/boot/dts/freescale/hc-ls1043a-hcen1002-sdk.dtb");
|
||||
hcen101-dtb {
|
||||
description = "hcen101-dtb";
|
||||
data = /incbin/("arch/arm64/boot/dts/huachentel/hc-ls1012a-hcen101.dtb");
|
||||
type = "flat_dt";
|
||||
arch = "arm64";
|
||||
os = "linux";
|
||||
|
|
@ -51,22 +51,10 @@
|
|||
algo = "crc32";
|
||||
};
|
||||
};
|
||||
hcen1002-dpdk {
|
||||
description = "hcen1002-dpdk";
|
||||
data = /incbin/("arch/arm64/boot/dts/freescale/hc-ls1043a-hcen1002-usdpaa.dtb");
|
||||
type = "flat_dt";
|
||||
arch = "arm64";
|
||||
os = "linux";
|
||||
compression = "none";
|
||||
load = <0x90000000>;
|
||||
hash@1 {
|
||||
algo = "crc32";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
hcen104-dtb {
|
||||
description = "hcen1002-dtb";
|
||||
data = /incbin/("arch/arm64/boot/dts/freescale/hc-ls1043a-hcen104-sdk.dtb");
|
||||
description = "hcen1004a-dtb";
|
||||
data = /incbin/("arch/arm64/boot/dts/huachentel/hc-ls1043a-hcen104-sdk.dtb");
|
||||
type = "flat_dt";
|
||||
arch = "arm64";
|
||||
os = "linux";
|
||||
|
|
@ -77,8 +65,8 @@
|
|||
};
|
||||
};
|
||||
hcen104-dpdk {
|
||||
description = "hcen104-dpdk";
|
||||
data = /incbin/("arch/arm64/boot/dts/freescale/hc-ls1043a-hcen104-usdpaa.dtb");
|
||||
description = "hcen1004a-dpdk";
|
||||
data = /incbin/("arch/arm64/boot/dts/huachentel/hc-ls1043a-hcen104-usdpaa.dtb");
|
||||
type = "flat_dt";
|
||||
arch = "arm64";
|
||||
os = "linux";
|
||||
|
|
@ -88,33 +76,177 @@
|
|||
algo = "crc32";
|
||||
};
|
||||
};
|
||||
|
||||
hcen1002a-dtb {
|
||||
description = "hcen10042a-dtb";
|
||||
data = /incbin/("arch/arm64/boot/dts/huachentel/hc-ls1043a-hcen1002a-sdk.dtb");
|
||||
type = "flat_dt";
|
||||
arch = "arm64";
|
||||
os = "linux";
|
||||
compression = "none";
|
||||
load = <0x90000000>;
|
||||
hash@1 {
|
||||
algo = "crc32";
|
||||
};
|
||||
};
|
||||
hcen1002a-dpdk {
|
||||
description = "hcen1002a-dpdk";
|
||||
data = /incbin/("arch/arm64/boot/dts/huachentel/hc-ls1043a-hcen1002a-usdpaa.dtb");
|
||||
type = "flat_dt";
|
||||
arch = "arm64";
|
||||
os = "linux";
|
||||
compression = "none";
|
||||
load = <0x90000000>;
|
||||
hash@1 {
|
||||
algo = "crc32";
|
||||
};
|
||||
};
|
||||
|
||||
hcen1002b-dtb {
|
||||
description = "hcen1002b-dtb";
|
||||
data = /incbin/("arch/arm64/boot/dts/huachentel/hc-ls1043a-hcen1002b-sdk.dtb");
|
||||
type = "flat_dt";
|
||||
arch = "arm64";
|
||||
os = "linux";
|
||||
compression = "none";
|
||||
load = <0x90000000>;
|
||||
hash@1 {
|
||||
algo = "crc32";
|
||||
};
|
||||
};
|
||||
hcen1002b-dpdk {
|
||||
description = "hcen1002b-dpdk";
|
||||
data = /incbin/("arch/arm64/boot/dts/huachentel/hc-ls1043a-hcen1002b-usdpaa.dtb");
|
||||
type = "flat_dt";
|
||||
arch = "arm64";
|
||||
os = "linux";
|
||||
compression = "none";
|
||||
load = <0x90000000>;
|
||||
hash@1 {
|
||||
algo = "crc32";
|
||||
};
|
||||
};
|
||||
|
||||
hcen1004a-dtb {
|
||||
description = "hcen1004a-dtb";
|
||||
data = /incbin/("arch/arm64/boot/dts/huachentel/hc-ls1046a-hcen1004a-sdk.dtb");
|
||||
type = "flat_dt";
|
||||
arch = "arm64";
|
||||
os = "linux";
|
||||
compression = "none";
|
||||
load = <0x90000000>;
|
||||
hash@1 {
|
||||
algo = "crc32";
|
||||
};
|
||||
};
|
||||
hcen1004a-dpdk {
|
||||
description = "hcen1004a-dpdk";
|
||||
data = /incbin/("arch/arm64/boot/dts/huachentel/hc-ls1046a-hcen1004a-usdpaa.dtb");
|
||||
type = "flat_dt";
|
||||
arch = "arm64";
|
||||
os = "linux";
|
||||
compression = "none";
|
||||
load = <0x90000000>;
|
||||
hash@1 {
|
||||
algo = "crc32";
|
||||
};
|
||||
};
|
||||
|
||||
hcen1004-dtb {
|
||||
description = "hcen1004-dtb";
|
||||
data = /incbin/("arch/arm64/boot/dts/huachentel/hc-ls1046a-hcen1004-sdk.dtb");
|
||||
type = "flat_dt";
|
||||
arch = "arm64";
|
||||
os = "linux";
|
||||
compression = "none";
|
||||
load = <0x90000000>;
|
||||
hash@1 {
|
||||
algo = "crc32";
|
||||
};
|
||||
};
|
||||
hcen1004-dpdk {
|
||||
description = "hcen1004-dpdk";
|
||||
data = /incbin/("arch/arm64/boot/dts/huachentel/hc-ls1046a-hcen1004-usdpaa.dtb");
|
||||
type = "flat_dt";
|
||||
arch = "arm64";
|
||||
os = "linux";
|
||||
compression = "none";
|
||||
load = <0x90000000>;
|
||||
hash@1 {
|
||||
algo = "crc32";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
configurations {
|
||||
|
||||
hcen1002 {
|
||||
description = "config for hcen1002";
|
||||
kernel = "kernel";
|
||||
ramdisk = "initrd";
|
||||
fdt = "hcen1002-dtb";
|
||||
};
|
||||
hcen1002-dpdk {
|
||||
description = "config for hcen1002 dpdk mode";
|
||||
kernel = "kernel";
|
||||
ramdisk = "initrd";
|
||||
fdt = "hcen1002-dpdk";
|
||||
};
|
||||
default = "hcen101";
|
||||
|
||||
hcen101 {
|
||||
description = "config for hcen104";
|
||||
kernel = "kernel";
|
||||
fdt = "hcen101-dtb";
|
||||
};
|
||||
|
||||
hcen104 {
|
||||
description = "config for hcen104";
|
||||
kernel = "kernel";
|
||||
ramdisk = "initrd";
|
||||
kernel = "kernel";
|
||||
fdt = "hcen104-dtb";
|
||||
};
|
||||
};
|
||||
|
||||
hcen104-dpdk {
|
||||
description = "config for hcen104 dpdk mode";
|
||||
kernel = "kernel";
|
||||
ramdisk = "initrd";
|
||||
description = "config for hcen104";
|
||||
kernel = "kernel";
|
||||
fdt = "hcen104-dpdk";
|
||||
};
|
||||
|
||||
hcen1002 {
|
||||
description = "config for hcen1002a";
|
||||
kernel = "kernel";
|
||||
fdt = "hcen1002a-dtb";
|
||||
};
|
||||
|
||||
hcen1002-dpdk {
|
||||
description = "config for hcen1002a";
|
||||
kernel = "kernel";
|
||||
fdt = "hcen1002a-dpdk";
|
||||
};
|
||||
|
||||
hcen1002b {
|
||||
description = "config for hcen1002b";
|
||||
kernel = "kernel";
|
||||
fdt = "hcen1002b-dtb";
|
||||
};
|
||||
|
||||
hcen1002b-dpdk {
|
||||
description = "config for hcen1002b";
|
||||
kernel = "kernel";
|
||||
fdt = "hcen1002b-dpdk";
|
||||
};
|
||||
|
||||
hcen1004 {
|
||||
description = "config for hcen1004";
|
||||
kernel = "kernel";
|
||||
fdt = "hcen1004-dtb";
|
||||
};
|
||||
|
||||
hcen1004-dpdk {
|
||||
description = "config for hcen1004";
|
||||
kernel = "kernel";
|
||||
fdt = "hcen1004-dpdk";
|
||||
};
|
||||
|
||||
hcen1004a {
|
||||
description = "config for hcen1004a";
|
||||
kernel = "kernel";
|
||||
fdt = "hcen1004a-dtb";
|
||||
};
|
||||
|
||||
hcen1004a-dpdk {
|
||||
description = "config for hcen1004a";
|
||||
kernel = "kernel";
|
||||
fdt = "hcen1004a-dpdk";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -626,7 +626,7 @@ ieee80211_rx_monitor(struct ieee80211_local *local, struct sk_buff *origskb,
|
|||
if (ieee80211_hw_check(&local->hw, RX_INCLUDES_FCS)) {
|
||||
if (unlikely(origskb->len <= FCS_LEN)) {
|
||||
/* driver bug */
|
||||
// WARN_ON(1);
|
||||
WARN_ON(1);
|
||||
dev_kfree_skb(origskb);
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -190,10 +190,6 @@ EXPORT_SYMBOL_GPL(nf_conntrack_htable_size);
|
|||
unsigned int nf_conntrack_max __read_mostly;
|
||||
seqcount_t nf_conntrack_generation __read_mostly;
|
||||
static unsigned int nf_conntrack_hash_rnd __read_mostly;
|
||||
/* add by yinbin@cmhi */
|
||||
u32 cmhi_seed;
|
||||
EXPORT_SYMBOL_GPL(cmhi_seed);
|
||||
EXPORT_SYMBOL_GPL(nf_conntrack_generation);
|
||||
|
||||
static u32 hash_conntrack_raw(const struct nf_conntrack_tuple *tuple,
|
||||
const struct net *net)
|
||||
|
|
@ -208,8 +204,6 @@ static u32 hash_conntrack_raw(const struct nf_conntrack_tuple *tuple,
|
|||
* three bytes manually.
|
||||
*/
|
||||
seed = nf_conntrack_hash_rnd ^ net_hash_mix(net);
|
||||
/* add by yinbin@cmhi */
|
||||
cmhi_seed = seed;
|
||||
n = (sizeof(tuple->src) + sizeof(tuple->dst.u3)) / sizeof(u32);
|
||||
return jhash2((u32 *)tuple, n, seed ^
|
||||
(((__force __u16)tuple->dst.u.all << 16) |
|
||||
|
|
@ -1140,9 +1134,6 @@ __nf_conntrack_alloc(struct net *net,
|
|||
/* save hash for reusing when confirming */
|
||||
*(unsigned long *)(&ct->tuplehash[IP_CT_DIR_REPLY].hnnode.pprev) = hash;
|
||||
ct->status = 0;
|
||||
|
||||
/* add by yinbin@cmhi 2019.5.16*/
|
||||
memset(&(ct->cmhi), 0, sizeof(ct->cmhi));
|
||||
write_pnet(&ct->ct_net, net);
|
||||
memset(&ct->__nfct_init_offset[0], 0,
|
||||
offsetof(struct nf_conn, proto) -
|
||||
|
|
|
|||
|
|
@ -1,11 +1,14 @@
|
|||
/* IP tables module for matching the value of the IPv4/IPv6 DSCP field
|
||||
/* x_tables module for setting the IPv4/IPv6 DSCP field, Version 1.8
|
||||
*
|
||||
* (C) 2002 by Harald Welte <laforge@netfilter.org>
|
||||
* based on ipt_FTOS.c (C) 2000 by Matthew G. Marsh <mgm@paktronix.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
*
|
||||
* See RFC2474 for a description of the DSCP field within the IP Header.
|
||||
*/
|
||||
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
||||
#include <linux/module.h>
|
||||
#include <linux/skbuff.h>
|
||||
|
|
@ -14,102 +17,150 @@
|
|||
#include <net/dsfield.h>
|
||||
|
||||
#include <linux/netfilter/x_tables.h>
|
||||
#include <linux/netfilter/xt_dscp.h>
|
||||
#include <linux/netfilter/xt_DSCP.h>
|
||||
|
||||
MODULE_AUTHOR("Harald Welte <laforge@netfilter.org>");
|
||||
MODULE_DESCRIPTION("Xtables: DSCP/TOS field match");
|
||||
MODULE_DESCRIPTION("Xtables: DSCP/TOS field modification");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("ipt_dscp");
|
||||
MODULE_ALIAS("ip6t_dscp");
|
||||
MODULE_ALIAS("ipt_tos");
|
||||
MODULE_ALIAS("ip6t_tos");
|
||||
MODULE_ALIAS("ipt_DSCP");
|
||||
MODULE_ALIAS("ip6t_DSCP");
|
||||
MODULE_ALIAS("ipt_TOS");
|
||||
MODULE_ALIAS("ip6t_TOS");
|
||||
|
||||
static bool
|
||||
dscp_mt(const struct sk_buff *skb, struct xt_action_param *par)
|
||||
static unsigned int
|
||||
dscp_tg(struct sk_buff *skb, const struct xt_action_param *par)
|
||||
{
|
||||
const struct xt_dscp_info *info = par->matchinfo;
|
||||
const struct xt_DSCP_info *dinfo = par->targinfo;
|
||||
u_int8_t dscp = ipv4_get_dsfield(ip_hdr(skb)) >> XT_DSCP_SHIFT;
|
||||
|
||||
return (dscp == info->dscp) ^ !!info->invert;
|
||||
if (dscp != dinfo->dscp) {
|
||||
if (!skb_make_writable(skb, sizeof(struct iphdr)))
|
||||
return NF_DROP;
|
||||
|
||||
ipv4_change_dsfield(ip_hdr(skb),
|
||||
(__force __u8)(~XT_DSCP_MASK),
|
||||
dinfo->dscp << XT_DSCP_SHIFT);
|
||||
|
||||
}
|
||||
return XT_CONTINUE;
|
||||
}
|
||||
|
||||
static bool
|
||||
dscp_mt6(const struct sk_buff *skb, struct xt_action_param *par)
|
||||
static unsigned int
|
||||
dscp_tg6(struct sk_buff *skb, const struct xt_action_param *par)
|
||||
{
|
||||
const struct xt_dscp_info *info = par->matchinfo;
|
||||
const struct xt_DSCP_info *dinfo = par->targinfo;
|
||||
u_int8_t dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> XT_DSCP_SHIFT;
|
||||
|
||||
return (dscp == info->dscp) ^ !!info->invert;
|
||||
if (dscp != dinfo->dscp) {
|
||||
if (!skb_make_writable(skb, sizeof(struct ipv6hdr)))
|
||||
return NF_DROP;
|
||||
|
||||
ipv6_change_dsfield(ipv6_hdr(skb),
|
||||
(__force __u8)(~XT_DSCP_MASK),
|
||||
dinfo->dscp << XT_DSCP_SHIFT);
|
||||
}
|
||||
return XT_CONTINUE;
|
||||
}
|
||||
|
||||
static int dscp_mt_check(const struct xt_mtchk_param *par)
|
||||
static int dscp_tg_check(const struct xt_tgchk_param *par)
|
||||
{
|
||||
const struct xt_dscp_info *info = par->matchinfo;
|
||||
const struct xt_DSCP_info *info = par->targinfo;
|
||||
|
||||
if (info->dscp > XT_DSCP_MAX) {
|
||||
pr_info("dscp %x out of range\n", info->dscp);
|
||||
return -EDOM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool tos_mt(const struct sk_buff *skb, struct xt_action_param *par)
|
||||
static unsigned int
|
||||
tos_tg(struct sk_buff *skb, const struct xt_action_param *par)
|
||||
{
|
||||
const struct xt_tos_match_info *info = par->matchinfo;
|
||||
const struct xt_tos_target_info *info = par->targinfo;
|
||||
struct iphdr *iph = ip_hdr(skb);
|
||||
u_int8_t orig, nv;
|
||||
|
||||
if (xt_family(par) == NFPROTO_IPV4)
|
||||
return ((ip_hdr(skb)->tos & info->tos_mask) ==
|
||||
info->tos_value) ^ !!info->invert;
|
||||
else
|
||||
return ((ipv6_get_dsfield(ipv6_hdr(skb)) & info->tos_mask) ==
|
||||
info->tos_value) ^ !!info->invert;
|
||||
orig = ipv4_get_dsfield(iph);
|
||||
nv = (orig & ~info->tos_mask) ^ info->tos_value;
|
||||
|
||||
if (orig != nv) {
|
||||
if (!skb_make_writable(skb, sizeof(struct iphdr)))
|
||||
return NF_DROP;
|
||||
iph = ip_hdr(skb);
|
||||
ipv4_change_dsfield(iph, 0, nv);
|
||||
}
|
||||
|
||||
return XT_CONTINUE;
|
||||
}
|
||||
|
||||
static struct xt_match dscp_mt_reg[] __read_mostly = {
|
||||
static unsigned int
|
||||
tos_tg6(struct sk_buff *skb, const struct xt_action_param *par)
|
||||
{
|
||||
const struct xt_tos_target_info *info = par->targinfo;
|
||||
struct ipv6hdr *iph = ipv6_hdr(skb);
|
||||
u_int8_t orig, nv;
|
||||
|
||||
orig = ipv6_get_dsfield(iph);
|
||||
nv = (orig & ~info->tos_mask) ^ info->tos_value;
|
||||
|
||||
if (orig != nv) {
|
||||
if (!skb_make_writable(skb, sizeof(struct iphdr)))
|
||||
return NF_DROP;
|
||||
iph = ipv6_hdr(skb);
|
||||
ipv6_change_dsfield(iph, 0, nv);
|
||||
}
|
||||
|
||||
return XT_CONTINUE;
|
||||
}
|
||||
|
||||
static struct xt_target dscp_tg_reg[] __read_mostly = {
|
||||
{
|
||||
.name = "dscp",
|
||||
.name = "DSCP",
|
||||
.family = NFPROTO_IPV4,
|
||||
.checkentry = dscp_mt_check,
|
||||
.match = dscp_mt,
|
||||
.matchsize = sizeof(struct xt_dscp_info),
|
||||
.checkentry = dscp_tg_check,
|
||||
.target = dscp_tg,
|
||||
.targetsize = sizeof(struct xt_DSCP_info),
|
||||
.table = "mangle",
|
||||
.me = THIS_MODULE,
|
||||
},
|
||||
{
|
||||
.name = "dscp",
|
||||
.name = "DSCP",
|
||||
.family = NFPROTO_IPV6,
|
||||
.checkentry = dscp_mt_check,
|
||||
.match = dscp_mt6,
|
||||
.matchsize = sizeof(struct xt_dscp_info),
|
||||
.checkentry = dscp_tg_check,
|
||||
.target = dscp_tg6,
|
||||
.targetsize = sizeof(struct xt_DSCP_info),
|
||||
.table = "mangle",
|
||||
.me = THIS_MODULE,
|
||||
},
|
||||
{
|
||||
.name = "tos",
|
||||
.name = "TOS",
|
||||
.revision = 1,
|
||||
.family = NFPROTO_IPV4,
|
||||
.match = tos_mt,
|
||||
.matchsize = sizeof(struct xt_tos_match_info),
|
||||
.table = "mangle",
|
||||
.target = tos_tg,
|
||||
.targetsize = sizeof(struct xt_tos_target_info),
|
||||
.me = THIS_MODULE,
|
||||
},
|
||||
{
|
||||
.name = "tos",
|
||||
.name = "TOS",
|
||||
.revision = 1,
|
||||
.family = NFPROTO_IPV6,
|
||||
.match = tos_mt,
|
||||
.matchsize = sizeof(struct xt_tos_match_info),
|
||||
.table = "mangle",
|
||||
.target = tos_tg6,
|
||||
.targetsize = sizeof(struct xt_tos_target_info),
|
||||
.me = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init dscp_mt_init(void)
|
||||
static int __init dscp_tg_init(void)
|
||||
{
|
||||
return xt_register_matches(dscp_mt_reg, ARRAY_SIZE(dscp_mt_reg));
|
||||
return xt_register_targets(dscp_tg_reg, ARRAY_SIZE(dscp_tg_reg));
|
||||
}
|
||||
|
||||
static void __exit dscp_mt_exit(void)
|
||||
static void __exit dscp_tg_exit(void)
|
||||
{
|
||||
xt_unregister_matches(dscp_mt_reg, ARRAY_SIZE(dscp_mt_reg));
|
||||
xt_unregister_targets(dscp_tg_reg, ARRAY_SIZE(dscp_tg_reg));
|
||||
}
|
||||
|
||||
module_init(dscp_mt_init);
|
||||
module_exit(dscp_mt_exit);
|
||||
module_init(dscp_tg_init);
|
||||
module_exit(dscp_tg_exit);
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue