173 lines
2.8 KiB
Plaintext
173 lines
2.8 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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//
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// Device Tree file for LX2160AQDS
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//
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// Copyright 2018 NXP
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/dts-v1/;
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#include "fsl-lx2160a.dtsi"
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/ {
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model = "NXP Layerscape LX2160AQDS";
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compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
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aliases {
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crypto = &crypto;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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sb_3v3: regulator-sb3v3 {
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compatible = "regulator-fixed";
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regulator-name = "MC34717-3.3VSB";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&crypto {
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status = "okay";
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};
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&esdhc0 {
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status = "okay";
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};
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&esdhc1 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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i2c-mux@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2>;
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power-monitor@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <500>;
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};
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power-monitor@41 {
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compatible = "ti,ina220";
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reg = <0x41>;
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shunt-resistor = <1000>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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temperature-sensor@4c {
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compatible = "nxp,sa56004";
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reg = <0x4c>;
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vcc-supply = <&sb_3v3>;
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};
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temperature-sensor@4d {
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compatible = "nxp,sa56004";
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reg = <0x4d>;
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vcc-supply = <&sb_3v3>;
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};
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rtc@51 {
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compatible = "nxp,pcf2129";
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reg = <0x51>;
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};
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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&pcs_mdio1 {
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pcs_phy1: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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backplane-mode = "40gbase-kr";
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reg = <0x0>;
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fsl,lane-handle = <&serdes1>;
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fsl,lane-reg = <0xF00 0xE00 0xD00 0xC00>; /* lanes H, G, F, E */
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};
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};
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&pcs_mdio2 {
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pcs_phy2: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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backplane-mode = "40gbase-kr";
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reg = <0x0>;
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fsl,lane-handle = <&serdes1>;
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fsl,lane-reg = <0xB00 0xA00 0x900 0x800>; /* lanes D, C, B, A */
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};
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};
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&pcs_mdio3 {
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pcs_phy3: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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backplane-mode = "10gbase-kr";
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reg = <0x0>;
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fsl,lane-handle = <&serdes1>;
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fsl,lane-reg = <0xF00 0x100>; /* lane H */
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};
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};
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&pcs_mdio4 {
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pcs_phy4: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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backplane-mode = "10gbase-kr";
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reg = <0x0>;
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fsl,lane-handle = <&serdes1>;
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fsl,lane-reg = <0xE00 0x100>; /* lane G */
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};
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};
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/* Update DPMAC connections to 40G backplane PHYs
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* &dpmac1 {
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* phy-handle = <&pcs_phy1>;
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* };
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*
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* &dpmac2 {
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* phy-handle = <&pcs_phy2>;
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* };
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*/
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/* Update DPMAC connections to 10G backplane PHYs
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* &dpmac3 {
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* phy-handle = <&pcs_phy3>;
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* };
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*
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* &dpmac4 {
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* phy-handle = <&pcs_phy4>;
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* };
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*/
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