166 lines
2.7 KiB
Plaintext
166 lines
2.7 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree file for NXP LS1088A QDS Board.
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*
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* Copyright 2017 NXP
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*
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* Harninder Rai <harninder.rai@nxp.com>
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*
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*/
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/dts-v1/;
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#include "fsl-ls1088a.dtsi"
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/ {
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model = "LS1088A QDS Board";
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compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
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};
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&i2c0 {
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status = "okay";
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i2c-switch@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2>;
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ina220@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <1000>;
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};
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ina220@41 {
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compatible = "ti,ina220";
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reg = <0x41>;
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shunt-resistor = <1000>;
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};
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};
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i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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temp-sensor@4c {
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compatible = "adi,adt7461a";
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reg = <0x4c>;
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};
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rtc@51 {
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compatible = "nxp,pcf2129";
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reg = <0x51>;
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/* IRQ10_B */
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interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
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};
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eeprom@56 {
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compatible = "atmel,24c512";
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reg = <0x56>;
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};
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eeprom@57 {
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compatible = "atmel,24c512";
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reg = <0x57>;
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};
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};
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};
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};
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&ifc {
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ranges = <0 0 0x5 0x80000000 0x08000000
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2 0 0x5 0x30000000 0x00010000
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3 0 0x5 0x20000000 0x00010000>;
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status = "okay";
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nor@0,0 {
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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nand@2,0 {
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compatible = "fsl,ifc-nand";
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reg = <0x2 0x0 0x10000>;
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};
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fpga: board-control@3,0 {
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compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
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reg = <0x3 0x0 0x0000100>;
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};
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};
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&qspi {
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status = "okay";
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fsl,qspi-has-second-chip;
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qflash0: s25fs512s@0 {
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compatible = "spansion,m25p80";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <20000000>;
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reg = <0>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <4>;
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};
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qflash1: s25fs512s@1 {
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compatible = "spansion,m25p80";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <20000000>;
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reg = <1>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <4>;
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};
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};
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&duart0 {
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status = "okay";
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};
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&duart1 {
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status = "okay";
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};
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&esdhc {
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status = "okay";
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};
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&sata {
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status = "okay";
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};
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&pcs_mdio1 {
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pcs_phy1: ethernet-phy@0 {
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backplane-mode = "10gbase-kr";
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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fsl,lane-handle = <&serdes1>;
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fsl,lane-reg = <0x840 0x40>;/* lane B */
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};
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};
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&pcs_mdio2 {
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pcs_phy2: ethernet-phy@0 {
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backplane-mode = "10gbase-kr";
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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fsl,lane-handle = <&serdes1>;
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fsl,lane-reg = <0x800 0x40>;/* lane A */
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};
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};
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/* Update DPMAC connections to backplane PHYs, under SerDes 0x1D_0xXX.
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* &dpmac1 {
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* phy-handle = <&pcs_phy1>;
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* };
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*/
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