mirror of https://github.com/F-Stack/f-stack.git
138 lines
4.0 KiB
C
138 lines
4.0 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2015 Intel Corporation
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*/
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#ifndef _RTE_PREFETCH_H_
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#define _RTE_PREFETCH_H_
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#include <rte_compat.h>
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/**
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* @file
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*
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* Prefetch operations.
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*
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* This file defines an API for prefetch macros / inline-functions,
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* which are architecture-dependent. Prefetching occurs when a
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* processor requests an instruction or data from memory to cache
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* before it is actually needed, potentially speeding up the execution of the
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* program.
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*/
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/**
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* Prefetch a cache line into all cache levels.
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* @param p
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* Address to prefetch
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*/
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static inline void rte_prefetch0(const volatile void *p);
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/**
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* Prefetch a cache line into all cache levels except the 0th cache level.
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* @param p
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* Address to prefetch
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*/
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static inline void rte_prefetch1(const volatile void *p);
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/**
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* Prefetch a cache line into all cache levels except the 0th and 1th cache
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* levels.
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* @param p
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* Address to prefetch
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*/
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static inline void rte_prefetch2(const volatile void *p);
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/**
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* Prefetch a cache line into all cache levels (non-temporal/transient version)
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*
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* The non-temporal prefetch is intended as a prefetch hint that processor will
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* use the prefetched data only once or short period, unlike the
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* rte_prefetch0() function which imply that prefetched data to use repeatedly.
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*
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* @param p
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* Address to prefetch
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*/
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static inline void rte_prefetch_non_temporal(const volatile void *p);
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/**
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* @warning
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* @b EXPERIMENTAL: this API may change, or be removed, without prior notice
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*
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* Prefetch a cache line into all cache levels, with intention to write. This
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* prefetch variant hints to the CPU that the program is expecting to write to
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* the cache line being prefetched.
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*
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* @param p Address to prefetch
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*/
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__rte_experimental
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static inline void
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rte_prefetch0_write(const void *p)
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{
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/* 1 indicates intention to write, 3 sets target cache level to L1. See
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* GCC docs where these integer constants are described in more detail:
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* https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
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*/
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__builtin_prefetch(p, 1, 3);
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}
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/**
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* @warning
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* @b EXPERIMENTAL: this API may change, or be removed, without prior notice
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*
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* Prefetch a cache line into all cache levels, except the 0th, with intention
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* to write. This prefetch variant hints to the CPU that the program is
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* expecting to write to the cache line being prefetched.
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*
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* @param p Address to prefetch
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*/
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__rte_experimental
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static inline void
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rte_prefetch1_write(const void *p)
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{
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/* 1 indicates intention to write, 2 sets target cache level to L2. See
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* GCC docs where these integer constants are described in more detail:
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* https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
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*/
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__builtin_prefetch(p, 1, 2);
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}
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/**
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* @warning
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* @b EXPERIMENTAL: this API may change, or be removed, without prior notice
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*
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* Prefetch a cache line into all cache levels, except the 0th and 1st, with
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* intention to write. This prefetch variant hints to the CPU that the program
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* is expecting to write to the cache line being prefetched.
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*
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* @param p Address to prefetch
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*/
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__rte_experimental
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static inline void
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rte_prefetch2_write(const void *p)
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{
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/* 1 indicates intention to write, 1 sets target cache level to L3. See
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* GCC docs where these integer constants are described in more detail:
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* https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
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*/
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__builtin_prefetch(p, 1, 1);
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}
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/**
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* @warning
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* @b EXPERIMENTAL: this API may change, or be removed, without prior notice
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*
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* Demote a cache line to a more distant level of cache from the processor.
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* CLDEMOTE hints to hardware to move (demote) a cache line from the closest to
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* the processor to a level more distant from the processor. It is a hint and
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* not guaranteed. rte_cldemote is intended to move the cache line to the more
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* remote cache, where it expects sharing to be efficient and to indicate that
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* a line may be accessed by a different core in the future.
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*
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* @param p
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* Address to demote
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*/
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__rte_experimental
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static inline void
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rte_cldemote(const volatile void *p);
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#endif /* _RTE_PREFETCH_H_ */
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