mirror of https://github.com/F-Stack/f-stack.git
416 lines
14 KiB
C
416 lines
14 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2022 Intel Corporation
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* Copyright(c) 2022 Arm Limited
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*/
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#include <stdint.h>
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#include <ethdev_driver.h>
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#include <rte_malloc.h>
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#include <rte_vect.h>
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#include "iavf.h"
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#include "iavf_rxtx.h"
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#include "iavf_rxtx_vec_common.h"
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static inline void
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iavf_rxq_rearm(struct iavf_rx_queue *rxq)
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{
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int i;
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uint16_t rx_id;
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volatile union iavf_rx_desc *rxdp;
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struct rte_mbuf **rxep = &rxq->sw_ring[rxq->rxrearm_start];
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struct rte_mbuf *mb0, *mb1;
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uint64x2_t dma_addr0, dma_addr1;
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uint64x2_t zero = vdupq_n_u64(0);
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uint64_t paddr;
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rxdp = rxq->rx_ring + rxq->rxrearm_start;
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/* Pull 'n' more MBUFs into the software ring */
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if (unlikely(rte_mempool_get_bulk(rxq->mp,
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(void *)rxep,
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IAVF_RXQ_REARM_THRESH) < 0)) {
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if (rxq->rxrearm_nb + IAVF_RXQ_REARM_THRESH >=
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rxq->nb_rx_desc) {
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for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
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rxep[i] = &rxq->fake_mbuf;
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vst1q_u64((uint64_t *)&rxdp[i].read, zero);
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}
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}
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rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
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IAVF_RXQ_REARM_THRESH;
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return;
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}
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/* Initialize the mbufs in vector, process 2 mbufs in one loop */
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for (i = 0; i < IAVF_RXQ_REARM_THRESH; i += 2, rxep += 2) {
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mb0 = rxep[0];
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mb1 = rxep[1];
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paddr = mb0->buf_iova + RTE_PKTMBUF_HEADROOM;
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dma_addr0 = vdupq_n_u64(paddr);
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/* flush desc with pa dma_addr */
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vst1q_u64((uint64_t *)&rxdp++->read, dma_addr0);
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paddr = mb1->buf_iova + RTE_PKTMBUF_HEADROOM;
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dma_addr1 = vdupq_n_u64(paddr);
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vst1q_u64((uint64_t *)&rxdp++->read, dma_addr1);
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}
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rxq->rxrearm_start += IAVF_RXQ_REARM_THRESH;
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if (rxq->rxrearm_start >= rxq->nb_rx_desc)
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rxq->rxrearm_start = 0;
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rxq->rxrearm_nb -= IAVF_RXQ_REARM_THRESH;
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rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
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(rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
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rte_io_wmb();
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/* Update the tail pointer on the NIC */
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IAVF_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rx_id);
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}
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static inline void
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desc_to_olflags_v(struct iavf_rx_queue *rxq, volatile union iavf_rx_desc *rxdp,
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uint64x2_t descs[4], struct rte_mbuf **rx_pkts)
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{
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RTE_SET_USED(rxdp);
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uint32x4_t vlan0, vlan1, rss, l3_l4e;
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const uint64x2_t mbuf_init = {rxq->mbuf_initializer, 0};
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uint64x2_t rearm0, rearm1, rearm2, rearm3;
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/* mask everything except RSS, flow director and VLAN flags
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* bit2 is for VLAN tag, bit11 for flow director indication
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* bit13:12 for RSS indication.
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*/
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const uint32x4_t rss_vlan_msk = {
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0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804};
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const uint32x4_t cksum_mask = {
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RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
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RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
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RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD,
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RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
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RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
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RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD,
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RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
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RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
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RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD,
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RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
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RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
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RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD};
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/* map rss and vlan type to rss hash and vlan flag */
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const uint8x16_t vlan_flags = {
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0, 0, 0, 0,
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RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED, 0, 0, 0,
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0, 0, 0, 0,
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0, 0, 0, 0};
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const uint8x16_t rss_flags = {
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0, RTE_MBUF_F_RX_FDIR, 0, 0,
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0, 0, RTE_MBUF_F_RX_RSS_HASH, RTE_MBUF_F_RX_RSS_HASH | RTE_MBUF_F_RX_FDIR,
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0, 0, 0, 0,
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0, 0, 0, 0};
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const uint8x16_t l3_l4e_flags = {
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(RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,
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RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1,
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(RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
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(RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
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(RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD) >> 1,
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(RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
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(RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |
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RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
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(RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
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RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
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0, 0, 0, 0, 0, 0, 0, 0};
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vlan0 = vzipq_u32(vreinterpretq_u32_u64(descs[0]),
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vreinterpretq_u32_u64(descs[2])).val[1];
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vlan1 = vzipq_u32(vreinterpretq_u32_u64(descs[1]),
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vreinterpretq_u32_u64(descs[3])).val[1];
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vlan0 = vzipq_u32(vlan0, vlan1).val[0];
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vlan1 = vandq_u32(vlan0, rss_vlan_msk);
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vlan0 = vreinterpretq_u32_u8(vqtbl1q_u8(vlan_flags,
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vreinterpretq_u8_u32(vlan1)));
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const uint32x4_t desc_fltstat = vshrq_n_u32(vlan1, 11);
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rss = vreinterpretq_u32_u8(vqtbl1q_u8(rss_flags,
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vreinterpretq_u8_u32(desc_fltstat)));
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l3_l4e = vshrq_n_u32(vlan1, 22);
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l3_l4e = vreinterpretq_u32_u8(vqtbl1q_u8(l3_l4e_flags,
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vreinterpretq_u8_u32(l3_l4e)));
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/* then we shift left 1 bit */
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l3_l4e = vshlq_n_u32(l3_l4e, 1);
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/* we need to mask out the redundant bits */
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l3_l4e = vandq_u32(l3_l4e, cksum_mask);
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vlan0 = vorrq_u32(vlan0, rss);
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vlan0 = vorrq_u32(vlan0, l3_l4e);
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rearm0 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 0), mbuf_init, 1);
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rearm1 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 1), mbuf_init, 1);
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rearm2 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 2), mbuf_init, 1);
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rearm3 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 3), mbuf_init, 1);
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vst1q_u64((uint64_t *)&rx_pkts[0]->rearm_data, rearm0);
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vst1q_u64((uint64_t *)&rx_pkts[1]->rearm_data, rearm1);
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vst1q_u64((uint64_t *)&rx_pkts[2]->rearm_data, rearm2);
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vst1q_u64((uint64_t *)&rx_pkts[3]->rearm_data, rearm3);
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}
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#define PKTLEN_SHIFT 10
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#define IAVF_UINT16_BIT (CHAR_BIT * sizeof(uint16_t))
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static inline void
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desc_to_ptype_v(uint64x2_t descs[4], struct rte_mbuf **__rte_restrict rx_pkts,
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uint32_t *__rte_restrict ptype_tbl)
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{
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int i;
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uint8_t ptype;
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uint8x16_t tmp;
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for (i = 0; i < 4; i++) {
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tmp = vreinterpretq_u8_u64(vshrq_n_u64(descs[i], 30));
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ptype = vgetq_lane_u8(tmp, 8);
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rx_pkts[i]->packet_type = ptype_tbl[ptype];
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}
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}
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/**
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* vPMD raw receive routine, only accept(nb_pkts >= IAVF_VPMD_DESCS_PER_LOOP)
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*
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* Notice:
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* - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
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* - floor align nb_pkts to a IAVF_VPMD_DESCS_PER_LOOP power-of-two
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*/
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static inline uint16_t
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_recv_raw_pkts_vec(struct iavf_rx_queue *__rte_restrict rxq,
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struct rte_mbuf **__rte_restrict rx_pkts,
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uint16_t nb_pkts, uint8_t *split_packet)
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{
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RTE_SET_USED(split_packet);
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volatile union iavf_rx_desc *rxdp;
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struct rte_mbuf **sw_ring;
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uint16_t nb_pkts_recd;
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int pos;
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uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
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/* mask to shuffle from desc. to mbuf */
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uint8x16_t shuf_msk = {
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0xFF, 0xFF, /* pkt_type set as unknown */
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0xFF, 0xFF, /* pkt_type set as unknown */
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14, 15, /* octet 15~14, low 16 bits pkt_len */
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0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
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14, 15, /* octet 15~14, 16 bits data_len */
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2, 3, /* octet 2~3, low 16 bits vlan_macip */
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4, 5, 6, 7 /* octet 4~7, 32bits rss */
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};
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uint16x8_t crc_adjust = {
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0, 0, /* ignore pkt_type field */
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rxq->crc_len, /* sub crc on pkt_len */
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0, /* ignore high-16bits of pkt_len */
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rxq->crc_len, /* sub crc on data_len */
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0, 0, 0 /* ignore non-length fields */
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};
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/* nb_pkts has to be floor-aligned to IAVF_VPMD_DESCS_PER_LOOP */
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nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_VPMD_DESCS_PER_LOOP);
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rxdp = rxq->rx_ring + rxq->rx_tail;
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rte_prefetch_non_temporal(rxdp);
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/* See if we need to rearm the RX queue - gives the prefetch a bit
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* of time to act
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*/
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if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
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iavf_rxq_rearm(rxq);
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/* Before we start moving massive data around, check to see if
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* there is actually a packet available
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*/
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if (!(rxdp->wb.qword1.status_error_len &
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rte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
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return 0;
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/* Cache is empty -> need to scan the buffer rings, but first move
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* the next 'n' mbufs into the cache
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*/
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sw_ring = &rxq->sw_ring[rxq->rx_tail];
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/* A. load 4 packet in one loop
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* [A*. mask out 4 unused dirty field in desc]
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* B. copy 4 mbuf point from swring to rx_pkts
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* C. calc the number of DD bits among the 4 packets
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* [C*. extract the end-of-packet bit, if requested]
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* D. fill info. from desc to mbuf
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*/
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for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
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pos += IAVF_VPMD_DESCS_PER_LOOP,
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rxdp += IAVF_VPMD_DESCS_PER_LOOP) {
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uint64x2_t descs[IAVF_VPMD_DESCS_PER_LOOP];
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uint8x16_t pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
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uint16x8x2_t sterr_tmp1, sterr_tmp2;
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uint64x2_t mbp1, mbp2;
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uint16x8_t staterr;
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uint16x8_t tmp;
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uint64_t stat;
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int32x4_t len_shl = {0, 0, 0, PKTLEN_SHIFT};
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/* A.1 load desc[3-0] */
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descs[3] = vld1q_u64((uint64_t *)(rxdp + 3));
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descs[2] = vld1q_u64((uint64_t *)(rxdp + 2));
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descs[1] = vld1q_u64((uint64_t *)(rxdp + 1));
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descs[0] = vld1q_u64((uint64_t *)(rxdp));
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/* Use acquire fence to order loads of descriptor qwords */
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rte_atomic_thread_fence(__ATOMIC_ACQUIRE);
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/* A.2 reload qword0 to make it ordered after qword1 load */
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descs[3] = vld1q_lane_u64((uint64_t *)(rxdp + 3), descs[3], 0);
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descs[2] = vld1q_lane_u64((uint64_t *)(rxdp + 2), descs[2], 0);
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descs[1] = vld1q_lane_u64((uint64_t *)(rxdp + 1), descs[1], 0);
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descs[0] = vld1q_lane_u64((uint64_t *)(rxdp), descs[0], 0);
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/* B.1 load 4 mbuf point */
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mbp1 = vld1q_u64((uint64_t *)&sw_ring[pos]);
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mbp2 = vld1q_u64((uint64_t *)&sw_ring[pos + 2]);
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/* B.2 copy 4 mbuf point into rx_pkts */
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vst1q_u64((uint64_t *)&rx_pkts[pos], mbp1);
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vst1q_u64((uint64_t *)&rx_pkts[pos + 2], mbp2);
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/* pkts shift the pktlen field to be 16-bit aligned*/
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uint32x4_t len3 = vshlq_u32(vreinterpretq_u32_u64(descs[3]),
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len_shl);
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descs[3] = vreinterpretq_u64_u16(vsetq_lane_u16
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(vgetq_lane_u16(vreinterpretq_u16_u32(len3), 7),
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vreinterpretq_u16_u64(descs[3]),
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7));
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uint32x4_t len2 = vshlq_u32(vreinterpretq_u32_u64(descs[2]),
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len_shl);
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descs[2] = vreinterpretq_u64_u16(vsetq_lane_u16
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(vgetq_lane_u16(vreinterpretq_u16_u32(len2), 7),
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vreinterpretq_u16_u64(descs[2]),
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7));
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uint32x4_t len1 = vshlq_u32(vreinterpretq_u32_u64(descs[1]),
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len_shl);
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descs[1] = vreinterpretq_u64_u16(vsetq_lane_u16
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(vgetq_lane_u16(vreinterpretq_u16_u32(len1), 7),
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vreinterpretq_u16_u64(descs[1]),
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7));
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uint32x4_t len0 = vshlq_u32(vreinterpretq_u32_u64(descs[0]),
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len_shl);
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descs[0] = vreinterpretq_u64_u16(vsetq_lane_u16
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(vgetq_lane_u16(vreinterpretq_u16_u32(len0), 7),
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vreinterpretq_u16_u64(descs[0]),
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7));
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desc_to_olflags_v(rxq, rxdp, descs, &rx_pkts[pos]);
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/* D.1 pkts convert format from desc to pktmbuf */
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pkt_mb4 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[3]), shuf_msk);
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pkt_mb3 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[2]), shuf_msk);
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pkt_mb2 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[1]), shuf_msk);
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pkt_mb1 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[0]), shuf_msk);
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/* D.2 pkts set in_port/nb_seg and remove crc */
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tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb4), crc_adjust);
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pkt_mb4 = vreinterpretq_u8_u16(tmp);
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tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb3), crc_adjust);
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pkt_mb3 = vreinterpretq_u8_u16(tmp);
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tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb2), crc_adjust);
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pkt_mb2 = vreinterpretq_u8_u16(tmp);
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tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb1), crc_adjust);
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pkt_mb1 = vreinterpretq_u8_u16(tmp);
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/* D.3 copy final data to rx_pkts */
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vst1q_u8((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
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pkt_mb4);
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vst1q_u8((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
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pkt_mb3);
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vst1q_u8((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
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pkt_mb2);
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vst1q_u8((void *)&rx_pkts[pos]->rx_descriptor_fields1,
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pkt_mb1);
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desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
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if (likely(pos + IAVF_VPMD_DESCS_PER_LOOP < nb_pkts))
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rte_prefetch_non_temporal(rxdp + IAVF_VPMD_DESCS_PER_LOOP);
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/* C.1 4=>2 filter staterr info only */
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sterr_tmp2 = vzipq_u16(vreinterpretq_u16_u64(descs[1]),
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vreinterpretq_u16_u64(descs[3]));
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sterr_tmp1 = vzipq_u16(vreinterpretq_u16_u64(descs[0]),
|
|
vreinterpretq_u16_u64(descs[2]));
|
|
|
|
/* C.2 get 4 pkts staterr value */
|
|
staterr = vzipq_u16(sterr_tmp1.val[1],
|
|
sterr_tmp2.val[1]).val[0];
|
|
|
|
staterr = vshlq_n_u16(staterr, IAVF_UINT16_BIT - 1);
|
|
staterr = vreinterpretq_u16_s16(
|
|
vshrq_n_s16(vreinterpretq_s16_u16(staterr),
|
|
IAVF_UINT16_BIT - 1));
|
|
stat = ~vgetq_lane_u64(vreinterpretq_u64_u16(staterr), 0);
|
|
|
|
/* C.4 calc available number of desc */
|
|
if (unlikely(stat == 0)) {
|
|
nb_pkts_recd += IAVF_VPMD_DESCS_PER_LOOP;
|
|
} else {
|
|
nb_pkts_recd += __builtin_ctzl(stat) / IAVF_UINT16_BIT;
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* Update our internal tail pointer */
|
|
rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
|
|
rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
|
|
rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
|
|
return nb_pkts_recd;
|
|
}
|
|
|
|
/*
|
|
* Notice:
|
|
* - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
|
|
* - nb_pkts > IAVF_VPMD_RX_BURST, only scan IAVF_VPMD_RX_BURST
|
|
* numbers of DD bits
|
|
*/
|
|
uint16_t
|
|
iavf_recv_pkts_vec(void *__rte_restrict rx_queue,
|
|
struct rte_mbuf **__rte_restrict rx_pkts, uint16_t nb_pkts)
|
|
{
|
|
return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
|
|
}
|
|
|
|
static void __rte_cold
|
|
iavf_rx_queue_release_mbufs_neon(struct iavf_rx_queue *rxq)
|
|
{
|
|
_iavf_rx_queue_release_mbufs_vec(rxq);
|
|
}
|
|
|
|
static const struct iavf_rxq_ops neon_vec_rxq_ops = {
|
|
.release_mbufs = iavf_rx_queue_release_mbufs_neon,
|
|
};
|
|
|
|
int __rte_cold
|
|
iavf_rxq_vec_setup(struct iavf_rx_queue *rxq)
|
|
{
|
|
rxq->ops = &neon_vec_rxq_ops;
|
|
return iavf_rxq_vec_setup_default(rxq);
|
|
}
|
|
|
|
int __rte_cold
|
|
iavf_rx_vec_dev_check(struct rte_eth_dev *dev)
|
|
{
|
|
return iavf_rx_vec_dev_check_default(dev);
|
|
}
|