mirror of https://github.com/F-Stack/f-stack.git
284 lines
7.6 KiB
C
284 lines
7.6 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
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* Copyright(c) 2010-2017 Intel Corporation
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*/
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#include "txgbe_type.h"
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#include "txgbe_dcb.h"
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/**
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* txgbe_dcb_config_rx_arbiter_raptor - Config Rx Data arbiter
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* @hw: pointer to hardware structure
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* @refill: refill credits index by traffic class
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* @max: max credits index by traffic class
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* @bwg_id: bandwidth grouping indexed by traffic class
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* @tsa: transmission selection algorithm indexed by traffic class
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* @map: priority to tc assignments indexed by priority
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*
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* Configure Rx Packet Arbiter and credits for each traffic class.
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*/
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s32 txgbe_dcb_config_rx_arbiter_raptor(struct txgbe_hw *hw, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *tsa,
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u8 *map)
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{
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u32 reg = 0;
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u32 credit_refill = 0;
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u32 credit_max = 0;
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u8 i = 0;
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/*
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* Disable the arbiter before changing parameters
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* (always enable recycle mode; WSP)
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*/
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reg = TXGBE_ARBRXCTL_RRM | TXGBE_ARBRXCTL_WSP |
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TXGBE_ARBRXCTL_DIA;
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wr32(hw, TXGBE_ARBRXCTL, reg);
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/*
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* map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
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* bits sets for the UPs that needs to be mappped to that TC.
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* e.g if priorities 6 and 7 are to be mapped to a TC then the
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* up_to_tc_bitmap value for that TC will be 11000000 in binary.
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*/
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reg = 0;
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for (i = 0; i < TXGBE_DCB_UP_MAX; i++)
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reg |= (map[i] << (i * TXGBE_RPUP2TC_UP_SHIFT));
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wr32(hw, TXGBE_RPUP2TC, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
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credit_refill = refill[i];
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credit_max = max[i];
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reg = TXGBE_QARBRXCFG_CRQ(credit_refill) |
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TXGBE_QARBRXCFG_MCL(credit_max) |
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TXGBE_QARBRXCFG_BWG(bwg_id[i]);
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if (tsa[i] == txgbe_dcb_tsa_strict)
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reg |= TXGBE_QARBRXCFG_LSP;
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wr32(hw, TXGBE_QARBRXCFG(i), reg);
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}
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/*
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* Configure Rx packet plane (recycle mode; WSP) and
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* enable arbiter
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*/
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reg = TXGBE_ARBRXCTL_RRM | TXGBE_ARBRXCTL_WSP;
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wr32(hw, TXGBE_ARBRXCTL, reg);
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return 0;
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}
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/**
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* txgbe_dcb_config_tx_desc_arbiter_raptor - Config Tx Desc. arbiter
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* @hw: pointer to hardware structure
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* @refill: refill credits index by traffic class
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* @max: max credits index by traffic class
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* @bwg_id: bandwidth grouping indexed by traffic class
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* @tsa: transmission selection algorithm indexed by traffic class
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*
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* Configure Tx Descriptor Arbiter and credits for each traffic class.
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*/
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s32 txgbe_dcb_config_tx_desc_arbiter_raptor(struct txgbe_hw *hw, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *tsa)
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{
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u32 reg, max_credits;
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u8 i;
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/* Clear the per-Tx queue credits; we use per-TC instead */
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for (i = 0; i < 128; i++)
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wr32(hw, TXGBE_QARBTXCRED(i), 0);
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/* Configure traffic class credits and priority */
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for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
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max_credits = max[i];
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reg = TXGBE_QARBTXCFG_MCL(max_credits) |
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TXGBE_QARBTXCFG_CRQ(refill[i]) |
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TXGBE_QARBTXCFG_BWG(bwg_id[i]);
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if (tsa[i] == txgbe_dcb_tsa_group_strict_cee)
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reg |= TXGBE_QARBTXCFG_GSP;
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if (tsa[i] == txgbe_dcb_tsa_strict)
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reg |= TXGBE_QARBTXCFG_LSP;
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wr32(hw, TXGBE_QARBTXCFG(i), reg);
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}
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/*
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* Configure Tx descriptor plane (recycle mode; WSP) and
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* enable arbiter
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*/
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reg = TXGBE_ARBTXCTL_WSP | TXGBE_ARBTXCTL_RRM;
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wr32(hw, TXGBE_ARBTXCTL, reg);
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return 0;
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}
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/**
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* txgbe_dcb_config_tx_data_arbiter_raptor - Config Tx Data arbiter
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* @hw: pointer to hardware structure
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* @refill: refill credits index by traffic class
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* @max: max credits index by traffic class
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* @bwg_id: bandwidth grouping indexed by traffic class
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* @tsa: transmission selection algorithm indexed by traffic class
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* @map: priority to tc assignments indexed by priority
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*
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* Configure Tx Packet Arbiter and credits for each traffic class.
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*/
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s32 txgbe_dcb_config_tx_data_arbiter_raptor(struct txgbe_hw *hw, u16 *refill,
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u16 *max, u8 *bwg_id, u8 *tsa,
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u8 *map)
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{
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u32 reg;
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u8 i;
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/*
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* Disable the arbiter before changing parameters
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* (always enable recycle mode; SP; arb delay)
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*/
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reg = TXGBE_PARBTXCTL_SP |
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TXGBE_PARBTXCTL_RECYC |
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TXGBE_PARBTXCTL_DA;
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wr32(hw, TXGBE_PARBTXCTL, reg);
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/*
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* map all UPs to TCs. up_to_tc_bitmap for each TC has corresponding
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* bits sets for the UPs that needs to be mappped to that TC.
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* e.g if priorities 6 and 7 are to be mapped to a TC then the
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* up_to_tc_bitmap value for that TC will be 11000000 in binary.
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*/
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reg = 0;
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for (i = 0; i < TXGBE_DCB_UP_MAX; i++)
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reg |= TXGBE_DCBUP2TC_MAP(i, map[i]);
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wr32(hw, TXGBE_PBRXUP2TC, reg);
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/* Configure traffic class credits and priority */
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for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
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reg = TXGBE_PARBTXCFG_CRQ(refill[i]) |
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TXGBE_PARBTXCFG_MCL(max[i]) |
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TXGBE_PARBTXCFG_BWG(bwg_id[i]);
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if (tsa[i] == txgbe_dcb_tsa_group_strict_cee)
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reg |= TXGBE_PARBTXCFG_GSP;
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if (tsa[i] == txgbe_dcb_tsa_strict)
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reg |= TXGBE_PARBTXCFG_LSP;
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wr32(hw, TXGBE_PARBTXCFG(i), reg);
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}
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/*
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* Configure Tx packet plane (recycle mode; SP; arb delay) and
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* enable arbiter
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*/
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reg = TXGBE_PARBTXCTL_SP | TXGBE_PARBTXCTL_RECYC;
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wr32(hw, TXGBE_PARBTXCTL, reg);
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return 0;
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}
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/**
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* txgbe_dcb_config_pfc_raptor - Configure priority flow control
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* @hw: pointer to hardware structure
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* @pfc_en: enabled pfc bitmask
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* @map: priority to tc assignments indexed by priority
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*
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* Configure Priority Flow Control (PFC) for each traffic class.
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*/
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s32 txgbe_dcb_config_pfc_raptor(struct txgbe_hw *hw, u8 pfc_en, u8 *map)
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{
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u32 i, j, fcrtl, reg;
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u8 max_tc = 0;
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/* Enable Transmit Priority Flow Control */
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wr32(hw, TXGBE_TXFCCFG, TXGBE_TXFCCFG_PFC);
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/* Enable Receive Priority Flow Control */
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wr32m(hw, TXGBE_RXFCCFG, TXGBE_RXFCCFG_PFC,
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pfc_en ? TXGBE_RXFCCFG_PFC : 0);
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for (i = 0; i < TXGBE_DCB_UP_MAX; i++) {
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if (map[i] > max_tc)
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max_tc = map[i];
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}
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/* Configure PFC Tx thresholds per TC */
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for (i = 0; i <= max_tc; i++) {
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int enabled = 0;
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for (j = 0; j < TXGBE_DCB_UP_MAX; j++) {
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if (map[j] == i && (pfc_en & (1 << j))) {
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enabled = 1;
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break;
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}
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}
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if (enabled) {
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reg = TXGBE_FCWTRHI_TH(hw->fc.high_water[i]) |
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TXGBE_FCWTRHI_XOFF;
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fcrtl = TXGBE_FCWTRLO_TH(hw->fc.low_water[i]) |
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TXGBE_FCWTRLO_XON;
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wr32(hw, TXGBE_FCWTRLO(i), fcrtl);
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} else {
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/*
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* In order to prevent Tx hangs when the internal Tx
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* switch is enabled we must set the high water mark
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* to the Rx packet buffer size - 24KB. This allows
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* the Tx switch to function even under heavy Rx
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* workloads.
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*/
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reg = rd32(hw, TXGBE_PBRXSIZE(i)) - 24576;
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wr32(hw, TXGBE_FCWTRLO(i), 0);
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}
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wr32(hw, TXGBE_FCWTRHI(i), reg);
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}
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for (; i < TXGBE_DCB_TC_MAX; i++) {
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wr32(hw, TXGBE_FCWTRLO(i), 0);
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wr32(hw, TXGBE_FCWTRHI(i), 0);
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}
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/* Configure pause time (2 TCs per register) */
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reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
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for (i = 0; i < (TXGBE_DCB_TC_MAX / 2); i++)
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wr32(hw, TXGBE_FCXOFFTM(i), reg);
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/* Configure flow control refresh threshold value */
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wr32(hw, TXGBE_RXFCRFSH, hw->fc.pause_time / 2);
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return 0;
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}
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/**
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* txgbe_dcb_config_tc_stats_raptor - Config traffic class statistics
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* @hw: pointer to hardware structure
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* @dcb_config: pointer to txgbe_dcb_config structure
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*
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* Configure queue statistics registers, all queues belonging to same traffic
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* class uses a single set of queue statistics counters.
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*/
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s32 txgbe_dcb_config_tc_stats_raptor(struct txgbe_hw *hw,
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struct txgbe_dcb_config *dcb_config)
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{
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u8 tc_count = 8;
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bool vt_mode = false;
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UNREFERENCED_PARAMETER(hw);
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if (dcb_config != NULL) {
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tc_count = dcb_config->num_tcs.pg_tcs;
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vt_mode = dcb_config->vt_mode;
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}
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if (!((tc_count == 8 && !vt_mode) || tc_count == 4))
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return TXGBE_ERR_PARAM;
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return 0;
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}
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