mirror of https://github.com/F-Stack/f-stack.git
655 lines
14 KiB
C
655 lines
14 KiB
C
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) */
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/* Copyright (C) 2014-2017 aQuantia Corporation. */
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/* File hw_atl_utils.h: Declaration of common functions for Atlantic hardware
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* abstraction layer.
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*/
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#ifndef HW_ATL_UTILS_H
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#define HW_ATL_UTILS_H
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#define BIT(x) (1UL << (x))
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#define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); }
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/* Hardware tx descriptor */
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struct hw_atl_txd_s {
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u64 buf_addr;
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union {
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struct {
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u32 type:3;
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u32:1;
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u32 len:16;
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u32 dd:1;
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u32 eop:1;
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u32 cmd:8;
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u32:14;
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u32 ct_idx:1;
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u32 ct_en:1;
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u32 pay_len:18;
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} __rte_packed;
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u64 flags;
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};
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} __rte_packed;
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/* Hardware tx context descriptor */
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union hw_atl_txc_s {
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struct {
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u64 flags1;
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u64 flags2;
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};
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struct {
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u64:40;
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u32 tun_len:8;
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u32 out_len:16;
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u32 type:3;
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u32 idx:1;
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u32 vlan_tag:16;
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u32 cmd:4;
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u32 l2_len:7;
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u32 l3_len:9;
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u32 l4_len:8;
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u32 mss_len:16;
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} __rte_packed;
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} __rte_packed;
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enum aq_tx_desc_type {
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tx_desc_type_desc = 1,
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tx_desc_type_ctx = 2,
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};
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enum aq_tx_desc_cmd {
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tx_desc_cmd_vlan = 1,
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tx_desc_cmd_fcs = 2,
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tx_desc_cmd_ipv4 = 4,
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tx_desc_cmd_l4cs = 8,
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tx_desc_cmd_lso = 0x10,
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tx_desc_cmd_wb = 0x20,
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};
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/* Hardware rx descriptor */
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struct hw_atl_rxd_s {
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u64 buf_addr;
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u64 hdr_addr;
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} __rte_packed;
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/* Hardware rx descriptor writeback */
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struct hw_atl_rxd_wb_s {
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u32 rss_type:4;
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u32 pkt_type:8;
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u32 type:20;
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u32 rss_hash;
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u16 dd:1;
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u16 eop:1;
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u16 rx_stat:4;
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u16 rx_estat:6;
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u16 rsc_cnt:4;
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u16 pkt_len;
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u16 next_desc_ptr;
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u16 vlan;
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} __rte_packed;
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struct hw_atl_stats_s {
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u32 uprc;
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u32 mprc;
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u32 bprc;
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u32 erpt;
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u32 uptc;
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u32 mptc;
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u32 bptc;
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u32 erpr;
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u32 mbtc;
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u32 bbtc;
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u32 mbrc;
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u32 bbrc;
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u32 ubrc;
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u32 ubtc;
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u32 dpc;
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} __rte_packed;
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union ip_addr {
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struct {
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u8 addr[16];
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} v6;
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struct {
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u8 padding[12];
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u8 addr[4];
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} v4;
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} __rte_packed;
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struct hw_aq_atl_utils_fw_rpc {
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u32 msg_id;
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union {
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struct {
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u32 pong;
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} msg_ping;
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struct {
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u8 mac_addr[6];
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u32 ip_addr_cnt;
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struct {
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union ip_addr addr;
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union ip_addr mask;
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} ip[1];
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} msg_arp;
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struct {
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u32 len;
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u8 packet[1514U];
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} msg_inject;
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struct {
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u32 priority;
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u32 wol_packet_type;
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u32 pattern_id;
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u32 next_wol_pattern_offset;
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union {
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struct {
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u32 flags;
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u8 ipv4_source_address[4];
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u8 ipv4_dest_address[4];
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u16 tcp_source_port_number;
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u16 tcp_dest_port_number;
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} ipv4_tcp_syn_parameters;
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struct {
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u32 flags;
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u8 ipv6_source_address[16];
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u8 ipv6_dest_address[16];
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u16 tcp_source_port_number;
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u16 tcp_dest_port_number;
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} ipv6_tcp_syn_parameters;
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struct {
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u32 flags;
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} eapol_request_id_message_parameters;
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struct {
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u32 flags;
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u32 mask_offset;
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u32 mask_size;
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u32 pattern_offset;
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u32 pattern_size;
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} wol_bit_map_pattern;
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struct {
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u8 mac_addr[6];
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} wol_magic_packet_pattern;
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} wol_pattern;
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} msg_wol;
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struct {
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u16 tc_quanta[8];
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u16 tc_threshold[8];
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} msg_msm_pfc_quantas;
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struct {
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union {
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u32 pattern_mask;
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struct {
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u32 aq_pm_wol_reason_arp_v4_pkt : 1;
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u32 aq_pm_wol_reason_ipv4_ping_pkt : 1;
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u32 aq_pm_wol_reason_ipv6_ns_pkt : 1;
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u32 aq_pm_wol_reason_ipv6_ping_pkt : 1;
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u32 aq_pm_wol_reason_link_up : 1;
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u32 aq_pm_wol_reason_link_down : 1;
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u32 aq_pm_wol_reason_maximum : 1;
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};
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};
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union {
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u32 offload_mask;
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};
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} msg_enable_wakeup;
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struct {
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u32 priority;
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u32 protocol_offload_type;
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u32 protocol_offload_id;
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u32 next_protocol_offload_offset;
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union {
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struct {
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u32 flags;
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u8 remote_ipv4_addr[4];
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u8 host_ipv4_addr[4];
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u8 mac_addr[6];
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} ipv4_arp_params;
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};
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} msg_offload;
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struct {
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u32 id;
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} msg_del_id;
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};
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} __rte_packed;
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struct hw_aq_atl_utils_mbox_header {
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u32 version;
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u32 transaction_id;
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u32 error;
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} __rte_packed;
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struct hw_aq_info {
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u8 reserved[6];
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u16 phy_fault_code;
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u16 phy_temperature;
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u8 cable_len;
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u8 reserved1;
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u32 cable_diag_data[4];
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u8 reserved2[32];
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u32 caps_lo;
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u32 caps_hi;
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} __rte_packed;
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struct hw_aq_atl_utils_mbox {
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struct hw_aq_atl_utils_mbox_header header;
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struct hw_atl_stats_s stats;
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struct hw_aq_info info;
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} __rte_packed;
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/* fw2x */
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typedef u16 in_port_t;
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typedef u32 ip4_addr_t;
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typedef int int32_t;
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typedef short int16_t;
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typedef u32 fw_offset_t;
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struct ip6_addr {
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u32 addr[4];
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} __rte_packed;
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struct offload_ka_v4 {
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u32 timeout;
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in_port_t local_port;
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in_port_t remote_port;
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u8 remote_mac_addr[6];
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u16 win_size;
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u32 seq_num;
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u32 ack_num;
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ip4_addr_t local_ip;
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ip4_addr_t remote_ip;
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} __rte_packed;
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struct offload_ka_v6 {
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u32 timeout;
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in_port_t local_port;
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in_port_t remote_port;
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u8 remote_mac_addr[6];
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u16 win_size;
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u32 seq_num;
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u32 ack_num;
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struct ip6_addr local_ip;
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struct ip6_addr remote_ip;
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} __rte_packed;
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struct offload_ip_info {
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u8 v4_local_addr_count;
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u8 v4_addr_count;
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u8 v6_local_addr_count;
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u8 v6_addr_count;
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fw_offset_t v4_addr;
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fw_offset_t v4_prefix;
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fw_offset_t v6_addr;
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fw_offset_t v6_prefix;
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} __rte_packed;
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struct offload_port_info {
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u16 udp_port_count;
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u16 tcp_port_count;
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fw_offset_t udp_port;
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fw_offset_t tcp_port;
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} __rte_packed;
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struct offload_ka_info {
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u16 v4_ka_count;
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u16 v6_ka_count;
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u32 retry_count;
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u32 retry_interval;
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fw_offset_t v4_ka;
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fw_offset_t v6_ka;
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} __rte_packed;
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struct offload_rr_info {
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u32 rr_count;
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u32 rr_buf_len;
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fw_offset_t rr_id_x;
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fw_offset_t rr_buf;
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} __rte_packed;
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struct offload_info {
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u32 version; // current version is 0x00000000
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u32 len; // The whole structure length
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// including the variable-size buf
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u8 mac_addr[6]; // 8 bytes to keep alignment. Only
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// first 6 meaningful.
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u8 reserved[2];
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struct offload_ip_info ips;
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struct offload_port_info ports;
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struct offload_ka_info kas;
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struct offload_rr_info rrs;
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u8 buf[0];
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} __rte_packed;
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struct smbus_request {
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u32 msg_id; /* not used */
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u32 device_id;
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u32 address;
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u32 length;
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} __rte_packed;
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enum macsec_msg_type {
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macsec_cfg_msg = 0,
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macsec_add_rx_sc_msg,
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macsec_add_tx_sc_msg,
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macsec_add_rx_sa_msg,
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macsec_add_tx_sa_msg,
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macsec_get_stats_msg,
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};
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struct macsec_cfg {
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uint32_t enabled;
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uint32_t egress_threshold;
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uint32_t ingress_threshold;
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uint32_t interrupts_enabled;
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} __rte_packed;
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struct add_rx_sc {
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uint32_t index;
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uint32_t pi; /* Port identifier */
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uint32_t sci[2]; /* Secure Channel identifier */
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uint32_t sci_mask; /* 1: enable comparison of SCI, 0: don't care */
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uint32_t tci;
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uint32_t tci_mask;
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uint32_t mac_sa[2];
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uint32_t sa_mask; /* 0: ignore mac_sa */
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uint32_t mac_da[2];
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uint32_t da_mask; /* 0: ignore mac_da */
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uint32_t validate_frames; /* 0: strict, 1:check, 2:disabled */
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uint32_t replay_protect; /* 1: enabled, 0:disabled */
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uint32_t anti_replay_window; /* default 0 */
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/* 1: auto_rollover enabled (when SA next_pn is saturated */
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uint32_t an_rol;
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} __rte_packed;
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struct add_tx_sc {
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uint32_t index;
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uint32_t pi; /* Port identifier */
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uint32_t sci[2]; /* Secure Channel identifier */
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uint32_t sci_mask; /* 1: enable comparison of SCI, 0: don't care */
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uint32_t tci; /* TCI value, used if packet is not explicitly tagged */
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uint32_t tci_mask;
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uint32_t mac_sa[2];
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uint32_t sa_mask; /* 0: ignore mac_sa */
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uint32_t mac_da[2];
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uint32_t da_mask; /* 0: ignore mac_da */
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uint32_t protect;
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uint32_t curr_an; /* SA index which currently used */
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} __rte_packed;
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struct add_rx_sa {
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uint32_t index;
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uint32_t next_pn;
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uint32_t key[4]; /* 128 bit key */
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} __rte_packed;
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struct add_tx_sa {
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uint32_t index;
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uint32_t next_pn;
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uint32_t key[4]; /* 128 bit key */
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} __rte_packed;
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struct get_stats {
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uint32_t version_only;
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uint32_t ingress_sa_index;
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uint32_t egress_sa_index;
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uint32_t egress_sc_index;
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} __rte_packed;
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struct macsec_stats {
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uint32_t api_version;
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/* Ingress Common Counters */
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uint64_t in_ctl_pkts;
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uint64_t in_tagged_miss_pkts;
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uint64_t in_untagged_miss_pkts;
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uint64_t in_notag_pkts;
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uint64_t in_untagged_pkts;
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uint64_t in_bad_tag_pkts;
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uint64_t in_no_sci_pkts;
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uint64_t in_unknown_sci_pkts;
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uint64_t in_ctrl_prt_pass_pkts;
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uint64_t in_unctrl_prt_pass_pkts;
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uint64_t in_ctrl_prt_fail_pkts;
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uint64_t in_unctrl_prt_fail_pkts;
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uint64_t in_too_long_pkts;
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uint64_t in_igpoc_ctl_pkts;
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uint64_t in_ecc_error_pkts;
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uint64_t in_unctrl_hit_drop_redir;
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/* Egress Common Counters */
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uint64_t out_ctl_pkts;
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uint64_t out_unknown_sa_pkts;
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uint64_t out_untagged_pkts;
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uint64_t out_too_long;
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uint64_t out_ecc_error_pkts;
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uint64_t out_unctrl_hit_drop_redir;
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/* Ingress SA Counters */
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uint64_t in_untagged_hit_pkts;
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uint64_t in_ctrl_hit_drop_redir_pkts;
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uint64_t in_not_using_sa;
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uint64_t in_unused_sa;
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uint64_t in_not_valid_pkts;
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uint64_t in_invalid_pkts;
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uint64_t in_ok_pkts;
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uint64_t in_late_pkts;
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uint64_t in_delayed_pkts;
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uint64_t in_unchecked_pkts;
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uint64_t in_validated_octets;
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uint64_t in_decrypted_octets;
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/* Egress SA Counters */
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uint64_t out_sa_hit_drop_redirect;
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uint64_t out_sa_protected2_pkts;
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uint64_t out_sa_protected_pkts;
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uint64_t out_sa_encrypted_pkts;
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/* Egress SC Counters */
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uint64_t out_sc_protected_pkts;
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uint64_t out_sc_encrypted_pkts;
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uint64_t out_sc_protected_octets;
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uint64_t out_sc_encrypted_octets;
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/* SA Counters expiration info */
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uint32_t egress_threshold_expired;
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uint32_t ingress_threshold_expired;
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uint32_t egress_expired;
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uint32_t ingress_expired;
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} __rte_packed;
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struct macsec_msg_fw_request {
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uint32_t offset; /* not used */
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uint32_t msg_type;
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union {
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struct macsec_cfg cfg;
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struct add_rx_sc rxsc;
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struct add_tx_sc txsc;
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struct add_rx_sa rxsa;
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struct add_tx_sa txsa;
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struct get_stats stats;
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};
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} __rte_packed;
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struct macsec_msg_fw_response {
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uint32_t result;
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struct macsec_stats stats;
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} __rte_packed;
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#define HAL_ATLANTIC_UTILS_CHIP_MIPS 0x00000001U
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#define HAL_ATLANTIC_UTILS_CHIP_TPO2 0x00000002U
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#define HAL_ATLANTIC_UTILS_CHIP_RPF2 0x00000004U
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#define HAL_ATLANTIC_UTILS_CHIP_MPI_AQ 0x00000010U
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#define HAL_ATLANTIC_UTILS_CHIP_REVISION_A0 0x01000000U
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#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B0 0x02000000U
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#define HAL_ATLANTIC_UTILS_CHIP_REVISION_B1 0x04000000U
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#define IS_CHIP_FEATURE(_F_) (HAL_ATLANTIC_UTILS_CHIP_##_F_ & \
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self->chip_features)
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enum hal_atl_utils_fw_state_e {
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MPI_DEINIT = 0,
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MPI_RESET = 1,
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MPI_INIT = 2,
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MPI_POWER = 4,
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};
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#define HAL_ATLANTIC_RATE_10G BIT(0)
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#define HAL_ATLANTIC_RATE_5G BIT(1)
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#define HAL_ATLANTIC_RATE_5GSR BIT(2)
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#define HAL_ATLANTIC_RATE_2GS BIT(3)
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#define HAL_ATLANTIC_RATE_1G BIT(4)
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#define HAL_ATLANTIC_RATE_100M BIT(5)
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#define HAL_ATLANTIC_RATE_INVALID BIT(6)
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#define HAL_ATLANTIC_UTILS_FW_MSG_PING 1U
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#define HAL_ATLANTIC_UTILS_FW_MSG_ARP 2U
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#define HAL_ATLANTIC_UTILS_FW_MSG_INJECT 3U
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#define HAL_ATLANTIC_UTILS_FW_MSG_WOL_ADD 4U
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#define HAL_ATLANTIC_UTILS_FW_MSG_WOL_DEL 5U
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#define HAL_ATLANTIC_UTILS_FW_MSG_ENABLE_WAKEUP 6U
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#define HAL_ATLANTIC_UTILS_FW_MSG_MSM_PFC 7U
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#define HAL_ATLANTIC_UTILS_FW_MSG_PROVISIONING 8U
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#define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_ADD 9U
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#define HAL_ATLANTIC_UTILS_FW_MSG_OFFLOAD_DEL 10U
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#define HAL_ATLANTIC_UTILS_FW_MSG_CABLE_DIAG 13U // 0xd
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#define SMBUS_DEVICE_ID 0x50
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enum hw_atl_fw2x_caps_lo {
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CAPS_LO_10BASET_HD = 0x00,
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CAPS_LO_10BASET_FD,
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CAPS_LO_100BASETX_HD,
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CAPS_LO_100BASET4_HD,
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CAPS_LO_100BASET2_HD,
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CAPS_LO_100BASETX_FD,
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CAPS_LO_100BASET2_FD,
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CAPS_LO_1000BASET_HD,
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CAPS_LO_1000BASET_FD,
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CAPS_LO_2P5GBASET_FD,
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CAPS_LO_5GBASET_FD,
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CAPS_LO_10GBASET_FD,
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CAPS_LO_AUTONEG,
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CAPS_LO_SMBUS_READ,
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CAPS_LO_SMBUS_WRITE,
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CAPS_LO_MACSEC
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};
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enum hw_atl_fw2x_caps_hi {
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CAPS_HI_RESERVED1 = 0x00,
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CAPS_HI_10BASET_EEE,
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CAPS_HI_RESERVED2,
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CAPS_HI_PAUSE,
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CAPS_HI_ASYMMETRIC_PAUSE,
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CAPS_HI_100BASETX_EEE,
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CAPS_HI_RESERVED3,
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CAPS_HI_RESERVED4,
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CAPS_HI_1000BASET_FD_EEE,
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CAPS_HI_2P5GBASET_FD_EEE,
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CAPS_HI_5GBASET_FD_EEE,
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CAPS_HI_10GBASET_FD_EEE,
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CAPS_HI_RESERVED5,
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CAPS_HI_RESERVED6,
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CAPS_HI_RESERVED7,
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CAPS_HI_RESERVED8,
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CAPS_HI_RESERVED9,
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CAPS_HI_CABLE_DIAG,
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CAPS_HI_TEMPERATURE,
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CAPS_HI_DOWNSHIFT,
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CAPS_HI_PTP_AVB_EN,
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|
CAPS_HI_MEDIA_DETECT,
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CAPS_HI_LINK_DROP,
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|
CAPS_HI_SLEEP_PROXY,
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CAPS_HI_WOL,
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|
CAPS_HI_MAC_STOP,
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|
CAPS_HI_EXT_LOOPBACK,
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|
CAPS_HI_INT_LOOPBACK,
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CAPS_HI_EFUSE_AGENT,
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CAPS_HI_WOL_TIMER,
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CAPS_HI_STATISTICS,
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CAPS_HI_TRANSACTION_ID,
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};
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enum hw_atl_fw2x_rate {
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FW2X_RATE_100M = BIT(CAPS_LO_100BASETX_FD),
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FW2X_RATE_1G = BIT(CAPS_LO_1000BASET_FD),
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FW2X_RATE_2G5 = BIT(CAPS_LO_2P5GBASET_FD),
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FW2X_RATE_5G = BIT(CAPS_LO_5GBASET_FD),
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FW2X_RATE_10G = BIT(CAPS_LO_10GBASET_FD),
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|
};
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struct aq_hw_s;
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struct aq_fw_ops;
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struct aq_hw_link_status_s;
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int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops);
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int hw_atl_utils_soft_reset(struct aq_hw_s *self);
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|
|
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void hw_atl_utils_hw_chip_features_init(struct aq_hw_s *self, u32 *p);
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|
|
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int hw_atl_utils_mpi_read_mbox(struct aq_hw_s *self,
|
|
struct hw_aq_atl_utils_mbox_header *pmbox);
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|
|
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void hw_atl_utils_mpi_read_stats(struct aq_hw_s *self,
|
|
struct hw_aq_atl_utils_mbox *pmbox);
|
|
|
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void hw_atl_utils_mpi_set(struct aq_hw_s *self,
|
|
enum hal_atl_utils_fw_state_e state,
|
|
u32 speed);
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|
|
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int hw_atl_utils_mpi_get_link_status(struct aq_hw_s *self);
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|
|
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unsigned int hw_atl_utils_mbps_2_speed_index(unsigned int mbps);
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|
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unsigned int hw_atl_utils_hw_get_reg_length(void);
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|
|
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int hw_atl_utils_hw_get_regs(struct aq_hw_s *self,
|
|
u32 *regs_buff);
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|
|
|
int hw_atl_utils_hw_set_power(struct aq_hw_s *self,
|
|
unsigned int power_state);
|
|
|
|
int hw_atl_utils_hw_deinit(struct aq_hw_s *self);
|
|
|
|
int hw_atl_utils_get_fw_version(struct aq_hw_s *self, u32 *fw_version);
|
|
|
|
int hw_atl_utils_update_stats(struct aq_hw_s *self);
|
|
|
|
struct aq_stats_s *hw_atl_utils_get_hw_stats(struct aq_hw_s *self);
|
|
|
|
int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
|
|
u32 *p, u32 cnt);
|
|
|
|
int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
|
|
u32 cnt);
|
|
|
|
int hw_atl_utils_fw_set_wol(struct aq_hw_s *self, bool wol_enabled, u8 *mac);
|
|
|
|
int hw_atl_utils_fw_rpc_call(struct aq_hw_s *self, unsigned int rpc_size);
|
|
|
|
int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
|
|
struct hw_aq_atl_utils_fw_rpc **rpc);
|
|
|
|
extern const struct aq_fw_ops aq_fw_1x_ops;
|
|
extern const struct aq_fw_ops aq_fw_2x_ops;
|
|
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#endif /* HW_ATL_UTILS_H */
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