mirror of https://github.com/F-Stack/f-stack.git
76 lines
2.8 KiB
C
76 lines
2.8 KiB
C
/*-
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* BSD LICENSE
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*
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* Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
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* Copyright 2016 NXP.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Freescale Semiconductor, Inc nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DPAA2_HW_DPIO_H_
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#define _DPAA2_HW_DPIO_H_
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#include <mc/fsl_dpio.h>
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#include <mc/fsl_mc_sys.h>
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struct dpaa2_io_portal_t {
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struct dpaa2_dpio_dev *dpio_dev;
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struct dpaa2_dpio_dev *sec_dpio_dev;
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uint64_t net_tid;
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uint64_t sec_tid;
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void *eventdev;
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};
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/*! Global per thread DPIO portal */
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RTE_DECLARE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
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#define DPAA2_PER_LCORE_DPIO RTE_PER_LCORE(_dpaa2_io).dpio_dev
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#define DPAA2_PER_LCORE_PORTAL DPAA2_PER_LCORE_DPIO->sw_portal
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#define DPAA2_PER_LCORE_SEC_DPIO RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
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#define DPAA2_PER_LCORE_SEC_PORTAL DPAA2_PER_LCORE_SEC_DPIO->sw_portal
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extern struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
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struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id);
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/* Affine a DPIO portal to current processing thread */
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int dpaa2_affine_qbman_swp(void);
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/* Affine additional DPIO portal to current crypto processing thread */
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int dpaa2_affine_qbman_swp_sec(void);
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/* allocate memory for FQ - dq storage */
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int
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dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage);
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/* free memory for FQ- dq storage */
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void
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dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage);
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#endif /* _DPAA2_HW_DPIO_H_ */
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