mirror of https://github.com/F-Stack/f-stack.git
99 lines
3.5 KiB
ArmAsm
99 lines
3.5 KiB
ArmAsm
/*-
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* Copyright (C) 2011 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of MARVELL nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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#include <machine/param.h>
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.Lpj4b_sf_ctrl_reg:
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.word 0xf1021820
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ENTRY(pj4b_config)
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/* Set Auxiliary Debug Modes Control 0 register */
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mrc p15, 1, r0, c15, c1, 0
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/* ARMADAXP errata fix: ARM-CPU-6136 */
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bic r0, r0, #(1 << 12) /* LDSTM first issue is single word */
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orr r0, r0, #(1 << 22) /* DVM_WAKEUP disable */
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mcr p15, 1, r0, c15, c1, 0
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/* Set Auxiliary Debug Modes Control 1 register */
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mrc p15, 1, r0, c15, c1, 1
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/* ARMADAXP errata fix: ARM-CPU-6409 */
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bic r0, r0, #(1 << 2) /* Disable static branch prediction */
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orr r0, r0, #(1 << 5) /* STREX backoff disable */
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orr r0, r0, #(1 << 8) /* Internal parity handling disable */
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orr r0, r0, #(1 << 16) /* Disable data transfer for clean line */
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mcr p15, 1, r0, c15, c1, 1
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/* Set Auxiliary Function Modes Control 0 register */
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mrc p15, 1, r0, c15, c2, 0
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#if defined(SMP)
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orr r0, r0, #(1 << 1) /* SMP/nAMP enabled (coherency) */
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#endif
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orr r0, r0, #(1 << 2) /* L1 parite enable */
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orr r0, r0, #(1 << 8) /* Cache and TLB maintenance broadcast enable */
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mcr p15, 1, r0, c15, c2, 0
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/* Set Auxiliary Debug Modes Control 2 register */
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mrc p15, 1, r0, c15, c1, 2
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bic r0, r0, #(1 << 23) /* Enable fast LDR */
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orr r0, r0, #(1 << 25) /* Intervention Interleave disable */
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orr r0, r0, #(1 << 27) /* Critical word first sequencing disable */
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orr r0, r0, #(1 << 29) /* Disable MO device read / write */
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orr r0, r0, #(1 << 30) /* L1 cache strict round-robin replacement policy*/
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orr r0, r0, #(1 << 31) /* Enable write evict */
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mcr p15, 1, r0, c15, c1, 2
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#if defined(SMP)
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/* Set SMP mode in Auxiliary Control Register */
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mrc p15, 0, r0, c1, c0, 1
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orr r0, r0, #(1 << 5)
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mcr p15, 0, r0, c1, c0, 1
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#endif
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/* Load CPU number */
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mrc p15, 0, r0, c0, c0, 5
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and r0, r0, #0xf
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/* SF Enable and invalidate */
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ldr r1, .Lpj4b_sf_ctrl_reg
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ldr r2, [r1, r0, lsl #8]
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orr r2, r2, #(1 << 0)
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bic r2, r2, #(1 << 8)
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str r2, [r1, r0, lsl #8]
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RET
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END(pj4b_config)
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