mirror of https://github.com/F-Stack/f-stack.git
118 lines
3.4 KiB
C
118 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*******************************************************************************
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Intel 10 Gigabit PCI Express Linux driver
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Copyright(c) 1999 - 2012 Intel Corporation.
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Contact Information:
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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/* glue for the OS independent part of ixgbe
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* includes register access macros
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*/
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#ifndef _IXGBE_OSDEP_H_
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#define _IXGBE_OSDEP_H_
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/if_ether.h>
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#include <linux/sched.h>
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#include "kcompat.h"
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#ifndef msleep
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#define msleep(x) do { if (in_interrupt()) { \
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/* Don't mdelay in interrupt context! */ \
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BUG(); \
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} else { \
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msleep(x); \
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} } while (0)
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#endif
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#undef ASSERT
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#ifdef DBG
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#define hw_dbg(hw, S, A...) printk(KERN_DEBUG S, ## A)
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#else
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#define hw_dbg(hw, S, A...) do {} while (0)
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#endif
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#define e_dev_info(format, arg...) \
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dev_info(pci_dev_to_dev(adapter->pdev), format, ## arg)
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#define e_dev_warn(format, arg...) \
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dev_warn(pci_dev_to_dev(adapter->pdev), format, ## arg)
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#define e_dev_err(format, arg...) \
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dev_err(pci_dev_to_dev(adapter->pdev), format, ## arg)
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#define e_dev_notice(format, arg...) \
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dev_notice(pci_dev_to_dev(adapter->pdev), format, ## arg)
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#define e_info(msglvl, format, arg...) \
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netif_info(adapter, msglvl, adapter->netdev, format, ## arg)
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#define e_err(msglvl, format, arg...) \
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netif_err(adapter, msglvl, adapter->netdev, format, ## arg)
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#define e_warn(msglvl, format, arg...) \
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netif_warn(adapter, msglvl, adapter->netdev, format, ## arg)
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#define e_crit(msglvl, format, arg...) \
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netif_crit(adapter, msglvl, adapter->netdev, format, ## arg)
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#ifdef DBG
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#define IXGBE_WRITE_REG(a, reg, value) do {\
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switch (reg) { \
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case IXGBE_EIMS: \
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case IXGBE_EIMC: \
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case IXGBE_EIAM: \
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case IXGBE_EIAC: \
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case IXGBE_EICR: \
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case IXGBE_EICS: \
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printk("%s: Reg - 0x%05X, value - 0x%08X\n", __func__, \
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reg, (u32)(value)); \
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default: \
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break; \
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} \
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writel((value), ((a)->hw_addr + (reg))); \
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} while (0)
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#else
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#define IXGBE_WRITE_REG(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
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#endif
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#define IXGBE_READ_REG(a, reg) readl((a)->hw_addr + (reg))
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#define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) ( \
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writel((value), ((a)->hw_addr + (reg) + ((offset) << 2))))
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#define IXGBE_READ_REG_ARRAY(a, reg, offset) ( \
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readl((a)->hw_addr + (reg) + ((offset) << 2)))
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#ifndef writeq
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#define writeq(val, addr) do { writel((u32) (val), addr); \
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writel((u32) (val >> 32), (addr + 4)); \
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} while (0);
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#endif
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#define IXGBE_WRITE_REG64(a, reg, value) writeq((value), ((a)->hw_addr + (reg)))
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#define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
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struct ixgbe_hw;
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extern u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg);
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extern void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value);
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extern void ewarn(struct ixgbe_hw *hw, const char *str, u32 status);
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#define IXGBE_READ_PCIE_WORD ixgbe_read_pci_cfg_word
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#define IXGBE_WRITE_PCIE_WORD ixgbe_write_pci_cfg_word
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#define IXGBE_EEPROM_GRANT_ATTEMPS 100
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#define IXGBE_HTONL(_i) htonl(_i)
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#define IXGBE_NTOHL(_i) ntohl(_i)
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#define IXGBE_NTOHS(_i) ntohs(_i)
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#define IXGBE_CPU_TO_LE32(_i) cpu_to_le32(_i)
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#define IXGBE_LE32_TO_CPUS(_i) le32_to_cpus(_i)
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#define EWARN(H, W, S) ewarn(H, W, S)
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#endif /* _IXGBE_OSDEP_H_ */
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