mirror of https://github.com/F-Stack/f-stack.git
122 lines
3.6 KiB
C
122 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*******************************************************************************
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Intel(R) Gigabit Ethernet Linux driver
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Copyright(c) 2007-2013 Intel Corporation.
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Contact Information:
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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/* glue for the OS independent part of e1000
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* includes register access macros
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*/
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#ifndef _E1000_OSDEP_H_
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#define _E1000_OSDEP_H_
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/if_ether.h>
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#include <linux/sched.h>
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#include "kcompat.h"
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#ifndef __INTEL_COMPILER
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#pragma GCC diagnostic ignored "-Wunused-function"
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#endif
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#define usec_delay(x) udelay(x)
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#define usec_delay_irq(x) udelay(x)
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#ifndef msec_delay
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#define msec_delay(x) do { \
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/* Don't mdelay in interrupt context! */ \
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if (in_interrupt()) \
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BUG(); \
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else \
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msleep(x); \
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} while (0)
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/* Some workarounds require millisecond delays and are run during interrupt
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* context. Most notably, when establishing link, the phy may need tweaking
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* but cannot process phy register reads/writes faster than millisecond
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* intervals...and we establish link due to a "link status change" interrupt.
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*/
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#define msec_delay_irq(x) mdelay(x)
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#endif
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#define PCI_COMMAND_REGISTER PCI_COMMAND
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#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
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#define ETH_ADDR_LEN ETH_ALEN
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#ifdef __BIG_ENDIAN
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#define E1000_BIG_ENDIAN __BIG_ENDIAN
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#endif
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#ifdef DEBUG
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#define DEBUGOUT(S) printk(KERN_DEBUG S)
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#define DEBUGOUT1(S, A...) printk(KERN_DEBUG S, ## A)
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#else
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#define DEBUGOUT(S)
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#define DEBUGOUT1(S, A...)
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#endif
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#ifdef DEBUG_FUNC
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#define DEBUGFUNC(F) DEBUGOUT(F "\n")
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#else
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#define DEBUGFUNC(F)
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#endif
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#define DEBUGOUT2 DEBUGOUT1
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#define DEBUGOUT3 DEBUGOUT2
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#define DEBUGOUT7 DEBUGOUT3
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#define E1000_REGISTER(a, reg) reg
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#define E1000_WRITE_REG(a, reg, value) ( \
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writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg))))
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#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_REGISTER(a, reg)))
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#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
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writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2))))
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#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
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readl((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2)))
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#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
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#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
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#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
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writew((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1))))
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#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
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readw((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1)))
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#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
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writeb((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + (offset))))
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#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
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readb((a)->hw_addr + E1000_REGISTER(a, reg) + (offset)))
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#define E1000_WRITE_REG_IO(a, reg, offset) do { \
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outl(reg, ((a)->io_base)); \
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outl(offset, ((a)->io_base + 4)); } while (0)
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#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
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#define E1000_WRITE_FLASH_REG(a, reg, value) ( \
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writel((value), ((a)->flash_address + reg)))
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#define E1000_WRITE_FLASH_REG16(a, reg, value) ( \
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writew((value), ((a)->flash_address + reg)))
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#define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg))
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#define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg))
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#endif /* _E1000_OSDEP_H_ */
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