mirror of https://github.com/F-Stack/f-stack.git
225 lines
7.7 KiB
C
225 lines
7.7 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2017-2021 Intel Corporation
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*/
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#include <rte_cryptodev.h>
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#include <cryptodev_pmd.h>
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#include "qat_sym_session.h"
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#include "qat_sym.h"
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#include "qat_asym.h"
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#include "qat_crypto.h"
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#include "qat_crypto_pmd_gens.h"
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#define MIXED_CRYPTO_MIN_FW_VER 0x04090000
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static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen2[] = {
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QAT_SYM_PLAIN_AUTH_CAP(SHA1,
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CAP_SET(block_size, 64),
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CAP_RNG(digest_size, 1, 20, 1)),
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QAT_SYM_AEAD_CAP(AES_GCM,
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CAP_SET(block_size, 16),
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CAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4),
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CAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 0, 12, 12)),
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QAT_SYM_AEAD_CAP(AES_CCM,
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CAP_SET(block_size, 16),
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CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 2),
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CAP_RNG(aad_size, 0, 224, 1), CAP_RNG(iv_size, 7, 13, 1)),
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QAT_SYM_AUTH_CAP(AES_GMAC,
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CAP_SET(block_size, 16),
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CAP_RNG(key_size, 16, 32, 8), CAP_RNG(digest_size, 8, 16, 4),
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CAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 0, 12, 12)),
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QAT_SYM_AUTH_CAP(AES_CMAC,
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CAP_SET(block_size, 16),
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CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 16, 4),
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CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),
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QAT_SYM_AUTH_CAP(SHA224,
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CAP_SET(block_size, 64),
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CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 28, 1),
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CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),
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QAT_SYM_AUTH_CAP(SHA256,
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CAP_SET(block_size, 64),
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CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 32, 1),
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CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),
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QAT_SYM_AUTH_CAP(SHA384,
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CAP_SET(block_size, 128),
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CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 48, 1),
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CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),
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QAT_SYM_AUTH_CAP(SHA512,
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CAP_SET(block_size, 128),
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CAP_RNG_ZERO(key_size), CAP_RNG(digest_size, 1, 64, 1),
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CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),
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QAT_SYM_AUTH_CAP(SHA1_HMAC,
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CAP_SET(block_size, 64),
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CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 20, 1),
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CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),
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QAT_SYM_AUTH_CAP(SHA224_HMAC,
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CAP_SET(block_size, 64),
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CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 28, 1),
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CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),
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QAT_SYM_AUTH_CAP(SHA256_HMAC,
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CAP_SET(block_size, 64),
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CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 32, 1),
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CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),
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QAT_SYM_AUTH_CAP(SHA384_HMAC,
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CAP_SET(block_size, 128),
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CAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 48, 1),
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CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),
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QAT_SYM_AUTH_CAP(SHA512_HMAC,
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CAP_SET(block_size, 128),
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CAP_RNG(key_size, 1, 128, 1), CAP_RNG(digest_size, 1, 64, 1),
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CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),
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QAT_SYM_AUTH_CAP(MD5_HMAC,
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CAP_SET(block_size, 64),
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CAP_RNG(key_size, 1, 64, 1), CAP_RNG(digest_size, 1, 16, 1),
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CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),
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QAT_SYM_AUTH_CAP(AES_XCBC_MAC,
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CAP_SET(block_size, 16),
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CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 12, 12, 0),
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CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),
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QAT_SYM_AUTH_CAP(SNOW3G_UIA2,
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CAP_SET(block_size, 16),
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CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0),
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CAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 16, 16, 0)),
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QAT_SYM_AUTH_CAP(KASUMI_F9,
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CAP_SET(block_size, 8),
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CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0),
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CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),
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QAT_SYM_AUTH_CAP(NULL,
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CAP_SET(block_size, 1),
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CAP_RNG_ZERO(key_size), CAP_RNG_ZERO(digest_size),
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CAP_RNG_ZERO(aad_size), CAP_RNG_ZERO(iv_size)),
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QAT_SYM_CIPHER_CAP(AES_CBC,
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CAP_SET(block_size, 16),
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CAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)),
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QAT_SYM_CIPHER_CAP(AES_CTR,
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CAP_SET(block_size, 16),
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CAP_RNG(key_size, 16, 32, 8), CAP_RNG(iv_size, 16, 16, 0)),
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QAT_SYM_CIPHER_CAP(AES_XTS,
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CAP_SET(block_size, 16),
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CAP_RNG(key_size, 32, 64, 32), CAP_RNG(iv_size, 16, 16, 0)),
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QAT_SYM_CIPHER_CAP(AES_DOCSISBPI,
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CAP_SET(block_size, 16),
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CAP_RNG(key_size, 16, 32, 16), CAP_RNG(iv_size, 16, 16, 0)),
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QAT_SYM_CIPHER_CAP(SNOW3G_UEA2,
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CAP_SET(block_size, 16),
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CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),
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QAT_SYM_CIPHER_CAP(KASUMI_F8,
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CAP_SET(block_size, 8),
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CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 8, 8, 0)),
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QAT_SYM_CIPHER_CAP(NULL,
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CAP_SET(block_size, 1),
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CAP_RNG_ZERO(key_size), CAP_RNG_ZERO(iv_size)),
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QAT_SYM_CIPHER_CAP(3DES_CBC,
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CAP_SET(block_size, 8),
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CAP_RNG(key_size, 8, 24, 8), CAP_RNG(iv_size, 8, 8, 0)),
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QAT_SYM_CIPHER_CAP(3DES_CTR,
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CAP_SET(block_size, 8),
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CAP_RNG(key_size, 16, 24, 8), CAP_RNG(iv_size, 8, 8, 0)),
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QAT_SYM_CIPHER_CAP(DES_CBC,
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CAP_SET(block_size, 8),
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CAP_RNG(key_size, 8, 24, 8), CAP_RNG(iv_size, 8, 8, 0)),
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QAT_SYM_CIPHER_CAP(DES_DOCSISBPI,
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CAP_SET(block_size, 8),
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CAP_RNG(key_size, 8, 8, 0), CAP_RNG(iv_size, 8, 8, 0)),
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QAT_SYM_CIPHER_CAP(ZUC_EEA3,
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CAP_SET(block_size, 16),
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CAP_RNG(key_size, 16, 16, 0), CAP_RNG(iv_size, 16, 16, 0)),
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QAT_SYM_AUTH_CAP(ZUC_EIA3,
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CAP_SET(block_size, 16),
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CAP_RNG(key_size, 16, 16, 0), CAP_RNG(digest_size, 4, 4, 0),
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CAP_RNG_ZERO(aad_size), CAP_RNG(iv_size, 16, 16, 0)),
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RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
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};
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static int
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qat_sym_crypto_qp_setup_gen2(struct rte_cryptodev *dev, uint16_t qp_id,
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const struct rte_cryptodev_qp_conf *qp_conf, int socket_id)
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{
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struct qat_cryptodev_private *qat_sym_private = dev->data->dev_private;
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struct qat_qp *qp;
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int ret;
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if (qat_cryptodev_qp_setup(dev, qp_id, qp_conf, socket_id)) {
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QAT_LOG(DEBUG, "QAT qp setup failed");
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return -1;
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}
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qp = qat_sym_private->qat_dev->qps_in_use[QAT_SERVICE_SYMMETRIC][qp_id];
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ret = qat_cq_get_fw_version(qp);
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if (ret < 0) {
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qat_cryptodev_qp_release(dev, qp_id);
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return ret;
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}
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if (ret != 0)
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QAT_LOG(DEBUG, "QAT firmware version: %d.%d.%d",
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(ret >> 24) & 0xff,
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(ret >> 16) & 0xff,
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(ret >> 8) & 0xff);
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else
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QAT_LOG(DEBUG, "unknown QAT firmware version");
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/* set capabilities based on the fw version */
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qat_sym_private->internal_capabilities = QAT_SYM_CAP_VALID |
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((ret >= MIXED_CRYPTO_MIN_FW_VER) ?
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QAT_SYM_CAP_MIXED_CRYPTO : 0);
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return 0;
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}
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struct rte_cryptodev_ops qat_sym_crypto_ops_gen2 = {
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/* Device related operations */
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.dev_configure = qat_cryptodev_config,
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.dev_start = qat_cryptodev_start,
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.dev_stop = qat_cryptodev_stop,
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.dev_close = qat_cryptodev_close,
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.dev_infos_get = qat_cryptodev_info_get,
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.stats_get = qat_cryptodev_stats_get,
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.stats_reset = qat_cryptodev_stats_reset,
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.queue_pair_setup = qat_sym_crypto_qp_setup_gen2,
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.queue_pair_release = qat_cryptodev_qp_release,
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/* Crypto related operations */
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.sym_session_get_size = qat_sym_session_get_private_size,
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.sym_session_configure = qat_sym_session_configure,
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.sym_session_clear = qat_sym_session_clear,
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/* Raw data-path API related operations */
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.sym_get_raw_dp_ctx_size = qat_sym_get_dp_ctx_size,
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.sym_configure_raw_dp_ctx = qat_sym_configure_dp_ctx,
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};
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static struct qat_capabilities_info
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qat_sym_crypto_cap_get_gen2(struct qat_pci_device *qat_dev __rte_unused)
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{
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struct qat_capabilities_info capa_info;
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capa_info.data = qat_sym_crypto_caps_gen2;
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capa_info.size = sizeof(qat_sym_crypto_caps_gen2);
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return capa_info;
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}
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RTE_INIT(qat_sym_crypto_gen2_init)
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{
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qat_sym_gen_dev_ops[QAT_GEN2].cryptodev_ops = &qat_sym_crypto_ops_gen2;
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qat_sym_gen_dev_ops[QAT_GEN2].get_capabilities =
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qat_sym_crypto_cap_get_gen2;
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qat_sym_gen_dev_ops[QAT_GEN2].get_feature_flags =
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qat_sym_crypto_feature_flags_get_gen1;
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#ifdef RTE_LIB_SECURITY
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qat_sym_gen_dev_ops[QAT_GEN2].create_security_ctx =
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qat_sym_create_security_gen1;
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#endif
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}
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RTE_INIT(qat_asym_crypto_gen2_init)
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{
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qat_asym_gen_dev_ops[QAT_GEN2].cryptodev_ops =
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&qat_asym_crypto_ops_gen1;
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qat_asym_gen_dev_ops[QAT_GEN2].get_capabilities =
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qat_asym_crypto_cap_get_gen1;
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qat_asym_gen_dev_ops[QAT_GEN2].get_feature_flags =
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qat_asym_crypto_feature_flags_get_gen1;
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}
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