mirror of https://github.com/F-Stack/f-stack.git
64 lines
1.4 KiB
C
64 lines
1.4 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright (C) 2019 Marvell International Ltd.
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*/
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#ifndef _OTX2_CRYPTODEV_H_
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#define _OTX2_CRYPTODEV_H_
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#include "cpt_common.h"
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#include "cpt_hw_types.h"
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#include "otx2_dev.h"
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/* Marvell OCTEON TX2 Crypto PMD device name */
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#define CRYPTODEV_NAME_OCTEONTX2_PMD crypto_octeontx2
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#define OTX2_CPT_MAX_LFS 128
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#define OTX2_CPT_MAX_QUEUES_PER_VF 64
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#define OTX2_CPT_MAX_BLKS 2
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#define OTX2_CPT_PMD_VERSION 3
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#define OTX2_CPT_REVISION_ID_3 3
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/**
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* Device private data
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*/
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struct otx2_cpt_vf {
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struct otx2_dev otx2_dev;
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/**< Base class */
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uint16_t max_queues;
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/**< Max queues supported */
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uint8_t nb_queues;
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/**< Number of crypto queues attached */
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uint16_t lf_msixoff[OTX2_CPT_MAX_LFS];
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/**< MSI-X offsets */
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uint8_t lf_blkaddr[OTX2_CPT_MAX_LFS];
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/**< CPT0/1 BLKADDR of LFs */
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uint8_t cpt_revision;
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/**< CPT revision */
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uint8_t err_intr_registered:1;
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/**< Are error interrupts registered? */
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union cpt_eng_caps hw_caps[CPT_MAX_ENG_TYPES];
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/**< CPT device capabilities */
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};
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struct cpt_meta_info {
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uint64_t deq_op_info[5];
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uint64_t comp_code_sz;
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union cpt_res_s cpt_res __rte_aligned(16);
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struct cpt_request_info cpt_req;
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};
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#define CPT_LOGTYPE otx2_cpt_logtype
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extern int otx2_cpt_logtype;
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/*
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* Crypto device driver ID
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*/
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extern uint8_t otx2_cryptodev_driver_id;
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uint64_t otx2_cpt_default_ff_get(void);
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void otx2_cpt_set_enqdeq_fns(struct rte_cryptodev *dev);
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#endif /* _OTX2_CRYPTODEV_H_ */
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