mirror of https://github.com/F-Stack/f-stack.git
402 lines
15 KiB
C
402 lines
15 KiB
C
/*-
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* Copyright (C) 2007
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* Oleksandr Tymoshenko <gonzo@freebsd.org>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __IF_AREREG_H__
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#define __IF_AREREG_H__
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struct are_desc {
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uint32_t are_stat;
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uint32_t are_devcs;
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uint32_t are_addr;
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uint32_t are_link;
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};
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#define ARE_DMASIZE(len) ((len) & ((1 << 11)-1))
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#define ARE_PKTSIZE(len) ((len & 0xffff0000) >> 16)
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#define ARE_RX_RING_CNT 128
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#define ARE_TX_RING_CNT 128
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#define ARE_TX_RING_SIZE sizeof(struct are_desc) * ARE_TX_RING_CNT
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#define ARE_RX_RING_SIZE sizeof(struct are_desc) * ARE_RX_RING_CNT
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#define ARE_MIN_FRAMELEN 60
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#define ARE_RING_ALIGN sizeof(struct are_desc)
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#define ARE_RX_ALIGN sizeof(uint32_t)
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#define ARE_MAXFRAGS 8
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#define ARE_TX_INTR_THRESH 8
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#define ARE_TX_RING_ADDR(sc, i) \
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((sc)->are_rdata.are_tx_ring_paddr + sizeof(struct are_desc) * (i))
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#define ARE_RX_RING_ADDR(sc, i) \
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((sc)->are_rdata.are_rx_ring_paddr + sizeof(struct are_desc) * (i))
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#define ARE_INC(x,y) (x) = (((x) + 1) % y)
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struct are_txdesc {
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struct mbuf *tx_m;
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bus_dmamap_t tx_dmamap;
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};
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struct are_rxdesc {
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struct mbuf *rx_m;
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bus_dmamap_t rx_dmamap;
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struct are_desc *desc;
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/* Use this values on error instead of allocating new mbuf */
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uint32_t saved_ctl, saved_ca;
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};
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struct are_chain_data {
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bus_dma_tag_t are_parent_tag;
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bus_dma_tag_t are_tx_tag;
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struct are_txdesc are_txdesc[ARE_TX_RING_CNT];
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bus_dma_tag_t are_rx_tag;
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struct are_rxdesc are_rxdesc[ARE_RX_RING_CNT];
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bus_dma_tag_t are_tx_ring_tag;
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bus_dma_tag_t are_rx_ring_tag;
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bus_dmamap_t are_tx_ring_map;
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bus_dmamap_t are_rx_ring_map;
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bus_dmamap_t are_rx_sparemap;
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int are_tx_pkts;
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int are_tx_prod;
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int are_tx_cons;
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int are_tx_cnt;
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int are_rx_cons;
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};
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struct are_ring_data {
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struct are_desc *are_rx_ring;
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struct are_desc *are_tx_ring;
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bus_addr_t are_rx_ring_paddr;
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bus_addr_t are_tx_ring_paddr;
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};
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struct are_softc {
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struct ifnet *are_ifp; /* interface info */
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bus_space_handle_t are_bhandle; /* bus space handle */
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bus_space_tag_t are_btag; /* bus space tag */
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device_t are_dev;
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uint8_t are_eaddr[ETHER_ADDR_LEN];
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struct resource *are_res;
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int are_rid;
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struct resource *are_irq;
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void *are_intrhand;
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u_int32_t sc_inten; /* copy of CSR_INTEN */
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u_int32_t sc_rxint_mask; /* mask of Rx interrupts we want */
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u_int32_t sc_txint_mask; /* mask of Tx interrupts we want */
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#ifdef ARE_MII
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device_t are_miibus;
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#else
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struct ifmedia are_ifmedia;
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#endif
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#ifdef ARE_MDIO
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device_t are_miiproxy;
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#endif
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bus_dma_tag_t are_parent_tag;
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bus_dma_tag_t are_tag;
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struct mtx are_mtx;
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struct callout are_stat_callout;
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struct task are_link_task;
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struct are_chain_data are_cdata;
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struct are_ring_data are_rdata;
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int are_link_status;
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int are_detach;
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int are_if_flags; /* last if flags */
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};
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#define ARE_LOCK(_sc) mtx_lock(&(_sc)->are_mtx)
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#define ARE_UNLOCK(_sc) mtx_unlock(&(_sc)->are_mtx)
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#define ARE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->are_mtx, MA_OWNED)
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/*
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* register space access macros
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*/
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4(sc->are_btag, sc->are_bhandle, reg, val)
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4(sc->are_btag, sc->are_bhandle, reg)
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/* $NetBSD: aereg.h,v 1.2 2008/04/28 20:23:28 martin Exp $ */
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/*-
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* Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Descriptor Status bits common to transmit and receive.
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*/
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#define ADSTAT_OWN 0x80000000 /* Tulip owns descriptor */
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#define ADSTAT_ES 0x00008000 /* Error Summary */
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/*
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* Descriptor Status bits for Receive Descriptor.
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*/
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#define ADSTAT_Rx_FF 0x40000000 /* Filtering Fail */
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#define ADSTAT_Rx_FL 0x3fff0000 /* Frame Length including CRC */
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#define ADSTAT_Rx_DE 0x00004000 /* Descriptor Error */
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#define ADSTAT_Rx_LE 0x00001000 /* Length Error */
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#define ADSTAT_Rx_RF 0x00000800 /* Runt Frame */
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#define ADSTAT_Rx_MF 0x00000400 /* Multicast Frame */
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#define ADSTAT_Rx_FS 0x00000200 /* First Descriptor */
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#define ADSTAT_Rx_LS 0x00000100 /* Last Descriptor */
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#define ADSTAT_Rx_TL 0x00000080 /* Frame Too Long */
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#define ADSTAT_Rx_CS 0x00000040 /* Collision Seen */
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#define ADSTAT_Rx_RT 0x00000020 /* Frame Type */
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#define ADSTAT_Rx_RW 0x00000010 /* Receive Watchdog */
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#define ADSTAT_Rx_RE 0x00000008 /* Report on MII Error */
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#define ADSTAT_Rx_DB 0x00000004 /* Dribbling Bit */
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#define ADSTAT_Rx_CE 0x00000002 /* CRC Error */
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#define ADSTAT_Rx_ZER 0x00000001 /* Zero (always 0) */
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#define ADSTAT_Rx_LENGTH(x) (((x) & ADSTAT_Rx_FL) >> 16)
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/*
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* Descriptor Status bits for Transmit Descriptor.
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*/
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#define ADSTAT_Tx_ES 0x00008000 /* Error Summary */
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#define ADSTAT_Tx_TO 0x00004000 /* Transmit Jabber Timeout */
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#define ADSTAT_Tx_LO 0x00000800 /* Loss of Carrier */
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#define ADSTAT_Tx_NC 0x00000400 /* No Carrier */
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#define ADSTAT_Tx_LC 0x00000200 /* Late Collision */
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#define ADSTAT_Tx_EC 0x00000100 /* Excessive Collisions */
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#define ADSTAT_Tx_HF 0x00000080 /* Heartbeat Fail */
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#define ADSTAT_Tx_CC 0x00000078 /* Collision Count */
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#define ADSTAT_Tx_ED 0x00000004 /* Excessive Deferral */
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#define ADSTAT_Tx_UF 0x00000002 /* Underflow Error */
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#define ADSTAT_Tx_DE 0x00000001 /* Deferred */
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#define ADSTAT_Tx_COLLISIONS(x) (((x) & ADSTAT_Tx_CC) >> 3)
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/*
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* Descriptor Control bits common to transmit and receive.
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*/
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#define ADCTL_SIZE1 0x000007ff /* Size of buffer 1 */
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#define ADCTL_SIZE1_SHIFT 0
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#define ADCTL_SIZE2 0x003ff800 /* Size of buffer 2 */
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#define ADCTL_SIZE2_SHIFT 11
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#define ADCTL_ER 0x02000000 /* End of Ring */
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#define ADCTL_CH 0x01000000 /* Second Address Chained */
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/*
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* Descriptor Control bits for Transmit Descriptor.
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*/
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#define ADCTL_Tx_IC 0x80000000 /* Interrupt on Completion */
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#define ADCTL_Tx_LS 0x40000000 /* Last Segment */
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#define ADCTL_Tx_FS 0x20000000 /* First Segment */
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#define ADCTL_Tx_AC 0x04000000 /* Add CRC Disable */
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#define ADCTL_Tx_DPD 0x00800000 /* Disabled Padding */
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/*
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* Control registers.
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*/
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/* tese are registers only found on this part */
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#define CSR_MACCTL 0x0000 /* mac control */
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#define CSR_MACHI 0x0004
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#define CSR_MACLO 0x0008
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#define CSR_HTHI 0x000C /* multicast table high */
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#define CSR_HTLO 0x0010 /* multicast table low */
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#define CSR_MIIADDR 0x0014 /* mii address */
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#define CSR_MIIDATA 0x0018 /* mii data */
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#define CSR_FLOWC 0x001C /* flow control */
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#define CSR_VL1 0x0020 /* vlan 1 tag */
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/* these are more or less normal Tulip registers */
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#define CSR_BUSMODE 0x1000 /* bus mode */
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#define CSR_TXPOLL 0x1004 /* tx poll demand */
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#define CSR_RXPOLL 0x1008 /* rx poll demand */
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#define CSR_RXLIST 0x100C /* rx base descriptor address */
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#define CSR_TXLIST 0x1010 /* tx base descriptor address */
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#define CSR_STATUS 0x1014 /* (interrupt) status */
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#define CSR_OPMODE 0x1018 /* operation mode */
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#define CSR_INTEN 0x101C /* interrupt enable */
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#define CSR_MISSED 0x1020 /* missed frame counter */
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#define CSR_HTBA 0x1050 /* host tx buffer address (ro) */
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#define CSR_HRBA 0x1054 /* host rx buffer address (ro) */
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/* CSR_MACCTL - Mac Control */
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#define MACCTL_RE 0x00000004 /* rx enable */
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#define MACCTL_TE 0x00000008 /* tx enable */
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#define MACCTL_DC 0x00000020 /* deferral check */
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#define MACCTL_PSTR 0x00000100 /* automatic pad strip */
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#define MACCTL_DTRY 0x00000400 /* disable retry */
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#define MACCTL_DBF 0x00000800 /* disable broadcast frames */
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#define MACCTL_LCC 0x00001000 /* late collision control */
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#define MACCTL_HASH 0x00002000 /* hash filtering enable */
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#define MACCTL_HO 0x00008000 /* disable perfect filtering */
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#define MACCTL_PB 0x00010000 /* pass bad frames */
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#define MACCTL_IF 0x00020000 /* inverse filtering */
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#define MACCTL_PR 0x00040000 /* promiscuous mode */
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#define MACCTL_PM 0x00080000 /* pass all multicast */
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#define MACCTL_FDX 0x00100000 /* full duplex mode */
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#define MACCTL_LOOP 0x00600000 /* loopback mask */
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#define MACCTL_LOOP_INT 0x00200000 /* internal loopback */
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#define MACCTL_LOOP_EXT 0x00400000 /* external loopback */
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#define MACCTL_LOOP_NONE 0x00000000
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#define MACCTL_DRO 0x00800000 /* disable receive own */
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#define MACCTL_PS 0x08000000 /* port select, 0 = mii */
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#define MACCTL_HBD 0x10000000 /* heartbeat disable */
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#define MACCTL_BLE 0x40000000 /* mac big endian */
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#define MACCTL_RA 0x80000000 /* receive all packets */
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/* CSR_MIIADDR - MII Addess */
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#define MIIADDR_BUSY 0x00000001 /* mii busy */
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#define MIIADDR_WRITE 0x00000002 /* mii write */
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#define MIIADDR_REG_MASK 0x000007C0 /* mii register */
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#define MIIADDR_REG_SHIFT 6
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#define MIIADDR_PHY_MASK 0x0000F800 /* mii phy */
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#define MIIADDR_PHY_SHIFT 11
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#define MIIADDR_GETREG(x) (((x) & MIIADDR_REG) >> 6)
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#define MIIADDR_PUTREG(x) (((x) << 6) & MIIADR_REG)
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#define MIIADDR_GETPHY(x) (((x) & MIIADDR_PHY) >> 11)
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#define MIIADDR_PUTPHY(x) (((x) << 6) & MIIADR_PHY)
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/* CSR_FLOWC - Flow Control */
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#define FLOWC_FCB 0x00000001 /* flow control busy */
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#define FLOWC_FCE 0x00000002 /* flow control enable */
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#define FLOWC_PCF 0x00000004 /* pass control frames */
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#define FLOWC_PT 0xffff0000 /* pause time */
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/* CSR_BUSMODE - Bus Mode */
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#define BUSMODE_SWR 0x00000001 /* software reset */
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#define BUSMODE_BAR 0x00000002 /* bus arbitration */
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#define BUSMODE_DSL 0x0000007c /* descriptor skip length */
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#define BUSMODE_BLE 0x00000080 /* data buf endian */
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/* programmable burst length */
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#define BUSMODE_PBL_DEFAULT 0x00000000 /* default value */
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#define BUSMODE_PBL_1LW 0x00000100 /* 1 longword */
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#define BUSMODE_PBL_2LW 0x00000200 /* 2 longwords */
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#define BUSMODE_PBL_4LW 0x00000400 /* 4 longwords */
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#define BUSMODE_PBL_8LW 0x00000800 /* 8 longwords */
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#define BUSMODE_PBL_16LW 0x00001000 /* 16 longwords */
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#define BUSMODE_PBL_32LW 0x00002000 /* 32 longwords */
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#define BUSMODE_DBO 0x00100000 /* descriptor endian */
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#define BUSMODE_ALIGN_16B 0x01000000 /* force oddhw rx buf align */
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/* CSR_TXPOLL - Transmit Poll Demand */
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#define TXPOLL_TPD 0x00000001 /* transmit poll demand */
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/* CSR_RXPOLL - Receive Poll Demand */
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#define RXPOLL_RPD 0x00000001 /* receive poll demand */
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/* CSR_STATUS - Status */
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#define STATUS_TI 0x00000001 /* transmit interrupt */
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#define STATUS_TPS 0x00000002 /* transmit process stopped */
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#define STATUS_TU 0x00000004 /* transmit buffer unavail */
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#define STATUS_TJT 0x00000008 /* transmit jabber timeout */
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#define STATUS_UNF 0x00000020 /* transmit underflow */
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#define STATUS_RI 0x00000040 /* receive interrupt */
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#define STATUS_RU 0x00000080 /* receive buffer unavail */
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#define STATUS_RPS 0x00000100 /* receive process stopped */
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#define STATUS_ETI 0x00000400 /* early transmit interrupt */
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#define STATUS_SE 0x00002000 /* system error */
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#define STATUS_ER 0x00004000 /* early receive (21041) */
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#define STATUS_AIS 0x00008000 /* abnormal intr summary */
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#define STATUS_NIS 0x00010000 /* normal interrupt summary */
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#define STATUS_RS 0x000e0000 /* receive process state */
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#define STATUS_RS_STOPPED 0x00000000 /* Stopped */
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#define STATUS_RS_FETCH 0x00020000 /* Running - fetch receive
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descriptor */
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#define STATUS_RS_CHECK 0x00040000 /* Running - check for end
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of receive */
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#define STATUS_RS_WAIT 0x00060000 /* Running - wait for packet */
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#define STATUS_RS_SUSPENDED 0x00080000 /* Suspended */
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#define STATUS_RS_CLOSE 0x000a0000 /* Running - close receive
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descriptor */
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#define STATUS_RS_FLUSH 0x000c0000 /* Running - flush current
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frame from FIFO */
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#define STATUS_RS_QUEUE 0x000e0000 /* Running - queue current
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frame from FIFO into
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buffer */
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#define STATUS_TS 0x00700000 /* transmit process state */
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#define STATUS_TS_STOPPED 0x00000000 /* Stopped */
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#define STATUS_TS_FETCH 0x00100000 /* Running - fetch transmit
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descriptor */
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#define STATUS_TS_WAIT 0x00200000 /* Running - wait for end
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of transmission */
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#define STATUS_TS_READING 0x00300000 /* Running - read buffer from
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memory and queue into
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FIFO */
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#define STATUS_TS_SUSPENDED 0x00600000 /* Suspended */
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#define STATUS_TS_CLOSE 0x00700000 /* Running - close transmit
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descriptor */
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#define STATUS_TX_ABORT 0x00800000 /* Transmit bus abort */
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#define STATUS_RX_ABORT 0x01000000 /* Transmit bus abort */
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/* CSR_OPMODE - Operation Mode */
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#define OPMODE_SR 0x00000002 /* start receive */
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#define OPMODE_OSF 0x00000004 /* operate on second frame */
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#define OPMODE_ST 0x00002000 /* start transmitter */
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#define OPMODE_TR 0x0000c000 /* threshold control */
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#define OPMODE_TR_32 0x00000000 /* 32 words */
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#define OPMODE_TR_64 0x00004000 /* 64 words */
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#define OPMODE_TR_128 0x00008000 /* 128 words */
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#define OPMODE_TR_256 0x0000c000 /* 256 words */
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#define OPMODE_SF 0x00200000 /* store and forward mode */
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/* CSR_INTEN - Interrupt Enable */
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/* See bits for CSR_STATUS -- Status */
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/* CSR_MISSED - Missed Frames */
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#define MISSED_MFC 0xffff0000 /* missed packet count */
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#define MISSED_FOC 0x0000ffff /* fifo overflow counter */
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#define MISSED_GETMFC(x) ((x) & MISSED_MFC)
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#define MISSED_GETFOC(x) (((x) & MISSED_FOC) >> 16)
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#endif /* __IF_AREREG_H__ */
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