mirror of https://github.com/F-Stack/f-stack.git
191 lines
6.6 KiB
ReStructuredText
191 lines
6.6 KiB
ReStructuredText
.. SPDX-License-Identifier: BSD-3-Clause
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Copyright(c) 2019 Intel Corporation
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Intel(R) FPGA 5GNR FEC Poll Mode Driver
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=======================================
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The BBDEV FPGA 5GNR FEC poll mode driver (PMD) supports an FPGA implementation of a VRAN
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LDPC Encode / Decode 5GNR wireless acceleration function, using Intel's PCI-e and FPGA
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based Vista Creek device.
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Features
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--------
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FPGA 5GNR FEC PMD supports the following features:
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- LDPC Encode in the DL
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- LDPC Decode in the UL
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- 8 VFs per PF (physical device)
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- Maximum of 32 UL queues per VF
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- Maximum of 32 DL queues per VF
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- PCIe Gen-3 x8 Interface
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- MSI-X
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- SR-IOV
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FPGA 5GNR FEC PMD supports the following BBDEV capabilities:
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* For the LDPC encode operation:
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- ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)
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- ``RTE_BBDEV_LDPC_RATE_MATCH`` : if set then do not do Rate Match bypass
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* For the LDPC decode operation:
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- ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK`` : check CRC24B from CB(s)
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- ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE`` : disable early termination
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- ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP`` : drops CRC24B bits appended while decoding
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- ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE`` : provides an input for HARQ combining
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- ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE`` : provides an input for HARQ combining
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- ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE`` : HARQ memory input is internal
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- ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE`` : HARQ memory output is internal
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- ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK`` : loopback data to/from HARQ memory
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- ``RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_FILLERS`` : HARQ memory includes the fillers bits
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Limitations
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-----------
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FPGA 5GNR FEC does not support the following:
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- Scatter-Gather function
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Installation
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------------
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Section 3 of the DPDK manual provides instructions on installing and compiling DPDK.
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DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.
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The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The
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hugepage configuration of a server may be examined using:
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.. code-block:: console
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grep Huge* /proc/meminfo
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Initialization
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--------------
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When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:
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.. code-block:: console
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sudo lspci -vd8086:0d8f
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The physical and virtual functions are compatible with Linux UIO drivers:
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``vfio_pci`` and ``igb_uio``. However, in order to work the FPGA 5GNR FEC device firstly needs
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to be bound to one of these linux drivers through DPDK.
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For more details on how to bind the PF device and create VF devices, see
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:ref:`linux_gsg_binding_kernel`.
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Configure the VFs through PF
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The PCI virtual functions must be configured before working or getting assigned
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to VMs/Containers. The configuration involves allocating the number of hardware
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queues, priorities, load balance, bandwidth and other settings necessary for the
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device to perform FEC functions.
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This configuration needs to be executed at least once after reboot or PCI FLR and can
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be achieved by using the function ``rte_fpga_5gnr_fec_configure()``, which sets up the
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parameters defined in ``rte_fpga_5gnr_fec_conf`` structure:
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.. code-block:: c
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struct rte_fpga_5gnr_fec_conf {
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bool pf_mode_en;
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uint8_t vf_ul_queues_number[FPGA_5GNR_FEC_NUM_VFS];
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uint8_t vf_dl_queues_number[FPGA_5GNR_FEC_NUM_VFS];
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uint8_t ul_bandwidth;
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uint8_t dl_bandwidth;
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uint8_t ul_load_balance;
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uint8_t dl_load_balance;
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};
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- ``pf_mode_en``: identifies whether only PF is to be used, or the VFs. PF and
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VFs are mutually exclusive and cannot run simultaneously.
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Set to 1 for PF mode enabled.
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If PF mode is enabled all queues available in the device are assigned
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exclusively to PF and 0 queues given to VFs.
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- ``vf_*l_queues_number``: defines the hardware queue mapping for every VF.
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- ``*l_bandwidth``: in case of congestion on PCIe interface. The device
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allocates different bandwidth to UL and DL. The weight is configured by this
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setting. The unit of weight is 3 code blocks. For example, if the code block
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cbps (code block per second) ratio between UL and DL is 12:1, then the
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configuration value should be set to 36:3. The schedule algorithm is based
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on code block regardless the length of each block.
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- ``*l_load_balance``: hardware queues are load-balanced in a round-robin
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fashion. Queues get filled first-in first-out until they reach a pre-defined
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watermark level, if exceeded, they won't get assigned new code blocks..
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This watermark is defined by this setting.
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If all hardware queues exceeds the watermark, no code blocks will be
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streamed in from UL/DL code block FIFO.
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An example configuration code calling the function ``rte_fpga_5gnr_fec_configure()`` is shown
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below:
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.. code-block:: c
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struct rte_fpga_5gnr_fec_conf conf;
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unsigned int i;
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memset(&conf, 0, sizeof(struct rte_fpga_5gnr_fec_conf));
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conf.pf_mode_en = 1;
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for (i = 0; i < FPGA_5GNR_FEC_NUM_VFS; ++i) {
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conf.vf_ul_queues_number[i] = 4;
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conf.vf_dl_queues_number[i] = 4;
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}
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conf.ul_bandwidth = 12;
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conf.dl_bandwidth = 5;
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conf.dl_load_balance = 64;
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conf.ul_load_balance = 64;
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/* setup FPGA PF */
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ret = rte_fpga_5gnr_fec_configure(info->dev_name, &conf);
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TEST_ASSERT_SUCCESS(ret,
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"Failed to configure 5GNR FPGA PF for bbdev %s",
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info->dev_name);
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Test Application
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----------------
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BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
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the functionality of the device, depending on the device's capabilities.
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For more details on how to use the test application,
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see :ref:`test_bbdev_application`.
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Test Vectors
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~~~~~~~~~~~~
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In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides
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a range of additional tests under the test_vectors folder, which may be useful. The results
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of these tests will depend on the FPGA 5GNR FEC capabilities.
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Alternate Baseband Device configuration tool
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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On top of the embedded configuration feature supported in test-bbdev using "- -init-device"
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option, there is also a tool available to perform that device configuration using a companion
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application.
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The ``pf_bb_config`` application notably enables then to run bbdev-test from the VF
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and not only limited to the PF as captured above.
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See for more details: https://github.com/intel/pf-bb-config
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Specifically for the BBDEV FPGA 5GNR FEC PMD, the command below can be used:
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.. code-block:: console
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./pf_bb_config FPGA_5GNR -c fpga_5gnr/fpga_5gnr_config_vf.cfg
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./test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 32 -l 1 -v ./ldpc_dec_default.data
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