mirror of https://github.com/F-Stack/f-stack.git
230 lines
6.9 KiB
C
230 lines
6.9 KiB
C
/*-
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* Copyright 2014 Svatopluk Kraus <onwahe@gmail.com>
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* Copyright 2014 Michal Meloun <meloun@miracle.cz>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <machine/cpu.h>
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#include <machine/cpuinfo.h>
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struct cpuinfo cpuinfo =
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{
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/* Use safe defaults for start */
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.dcache_line_size = 32,
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.dcache_line_mask = 31,
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.icache_line_size = 32,
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.icache_line_mask = 31,
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};
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/* Read and parse CPU id scheme */
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void
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cpuinfo_init(void)
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{
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cpuinfo.midr = cp15_midr_get();
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/* Test old version id schemes first */
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if ((cpuinfo.midr & CPU_ID_IMPLEMENTOR_MASK) == CPU_ID_ARM_LTD) {
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if (CPU_ID_ISOLD(cpuinfo.midr)) {
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/* obsolete ARMv2 or ARMv3 CPU */
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cpuinfo.midr = 0;
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return;
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}
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if (CPU_ID_IS7(cpuinfo.midr)) {
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if ((cpuinfo.midr & (1 << 23)) == 0) {
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/* obsolete ARMv3 CPU */
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cpuinfo.midr = 0;
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return;
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}
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/* ARMv4T CPU */
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cpuinfo.architecture = 1;
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cpuinfo.revision = (cpuinfo.midr >> 16) & 0x7F;
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} else {
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/* ARM new id scheme */
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cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F;
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cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F;
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}
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} else {
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/* non ARM -> must be new id scheme */
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cpuinfo.architecture = (cpuinfo.midr >> 16) & 0x0F;
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cpuinfo.revision = (cpuinfo.midr >> 20) & 0x0F;
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}
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/* Parse rest of MIDR */
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cpuinfo.implementer = (cpuinfo.midr >> 24) & 0xFF;
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cpuinfo.part_number = (cpuinfo.midr >> 4) & 0xFFF;
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cpuinfo.patch = cpuinfo.midr & 0x0F;
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/* CP15 c0,c0 regs 0-7 exist on all CPUs (although aliased with MIDR) */
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cpuinfo.ctr = cp15_ctr_get();
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cpuinfo.tcmtr = cp15_tcmtr_get();
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#if __ARM_ARCH >= 6
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cpuinfo.tlbtr = cp15_tlbtr_get();
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cpuinfo.mpidr = cp15_mpidr_get();
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cpuinfo.revidr = cp15_revidr_get();
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#endif
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/* if CPU is not v7 cpu id scheme */
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if (cpuinfo.architecture != 0xF)
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return;
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#if __ARM_ARCH >= 6
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cpuinfo.id_pfr0 = cp15_id_pfr0_get();
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cpuinfo.id_pfr1 = cp15_id_pfr1_get();
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cpuinfo.id_dfr0 = cp15_id_dfr0_get();
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cpuinfo.id_afr0 = cp15_id_afr0_get();
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cpuinfo.id_mmfr0 = cp15_id_mmfr0_get();
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cpuinfo.id_mmfr1 = cp15_id_mmfr1_get();
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cpuinfo.id_mmfr2 = cp15_id_mmfr2_get();
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cpuinfo.id_mmfr3 = cp15_id_mmfr3_get();
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cpuinfo.id_isar0 = cp15_id_isar0_get();
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cpuinfo.id_isar1 = cp15_id_isar1_get();
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cpuinfo.id_isar2 = cp15_id_isar2_get();
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cpuinfo.id_isar3 = cp15_id_isar3_get();
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cpuinfo.id_isar4 = cp15_id_isar4_get();
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cpuinfo.id_isar5 = cp15_id_isar5_get();
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/* Not yet - CBAR only exist on ARM SMP Cortex A CPUs
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cpuinfo.cbar = cp15_cbar_get();
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*/
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/* Test if revidr is implemented */
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if (cpuinfo.revidr == cpuinfo.midr)
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cpuinfo.revidr = 0;
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/* parsed bits of above registers */
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/* id_mmfr0 */
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cpuinfo.outermost_shareability = (cpuinfo.id_mmfr0 >> 8) & 0xF;
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cpuinfo.shareability_levels = (cpuinfo.id_mmfr0 >> 12) & 0xF;
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cpuinfo.auxiliary_registers = (cpuinfo.id_mmfr0 >> 20) & 0xF;
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cpuinfo.innermost_shareability = (cpuinfo.id_mmfr0 >> 28) & 0xF;
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/* id_mmfr2 */
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cpuinfo.mem_barrier = (cpuinfo.id_mmfr2 >> 20) & 0xF;
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/* id_mmfr3 */
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cpuinfo.coherent_walk = (cpuinfo.id_mmfr3 >> 20) & 0xF;
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cpuinfo.maintenance_broadcast =(cpuinfo.id_mmfr3 >> 12) & 0xF;
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/* id_pfr1 */
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cpuinfo.generic_timer_ext = (cpuinfo.id_pfr1 >> 16) & 0xF;
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cpuinfo.virtualization_ext = (cpuinfo.id_pfr1 >> 12) & 0xF;
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cpuinfo.security_ext = (cpuinfo.id_pfr1 >> 4) & 0xF;
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/* L1 Cache sizes */
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if (CPU_CT_FORMAT(cpuinfo.ctr) == CPU_CT_ARMV7) {
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cpuinfo.dcache_line_size =
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1 << (CPU_CT_DMINLINE(cpuinfo.ctr) + 2);
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cpuinfo.icache_line_size =
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1 << (CPU_CT_IMINLINE(cpuinfo.ctr) + 2);
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} else {
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cpuinfo.dcache_line_size =
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1 << (CPU_CT_xSIZE_LEN(CPU_CT_DSIZE(cpuinfo.ctr)) + 3);
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cpuinfo.icache_line_size =
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1 << (CPU_CT_xSIZE_LEN(CPU_CT_ISIZE(cpuinfo.ctr)) + 3);
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}
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cpuinfo.dcache_line_mask = cpuinfo.dcache_line_size - 1;
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cpuinfo.icache_line_mask = cpuinfo.icache_line_size - 1;
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#endif
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}
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/*
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* Get bits that must be set or cleared in ACLR register.
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* Note: Bits in ACLR register are IMPLEMENTATION DEFINED.
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* Its expected that SCU is in operational state before this
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* function is called.
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*/
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void
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cpuinfo_get_actlr_modifier(uint32_t *actlr_mask, uint32_t *actlr_set)
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{
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*actlr_mask = 0;
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*actlr_set = 0;
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if (cpuinfo.implementer == CPU_IMPLEMENTER_ARM) {
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switch (cpuinfo.part_number) {
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case CPU_ARCH_CORTEX_A17:
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case CPU_ARCH_CORTEX_A12: /* A12 is merged to A17 */
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/*
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* Enable SMP mode
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*/
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*actlr_mask = (1 << 6);
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*actlr_set = (1 << 6);
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break;
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case CPU_ARCH_CORTEX_A15:
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/*
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* Enable snoop-delayed exclusive handling
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* Enable SMP mode
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*/
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*actlr_mask = (1U << 31) |(1 << 6);
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*actlr_set = (1U << 31) |(1 << 6);
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break;
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case CPU_ARCH_CORTEX_A9:
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/*
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* Disable exclusive L1/L2 cache control
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* Enable SMP mode
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* Enable Cache and TLB maintenance broadcast
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*/
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*actlr_mask = (1 << 7) | (1 << 6) | (1 << 0);
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*actlr_set = (1 << 6) | (1 << 0);
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break;
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case CPU_ARCH_CORTEX_A8:
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/*
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* Enable L2 cache
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* Enable L1 data cache hardware alias checks
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*/
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*actlr_mask = (1 << 1) | (1 << 0);
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*actlr_set = (1 << 1);
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break;
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case CPU_ARCH_CORTEX_A7:
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/*
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* Enable SMP mode
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*/
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*actlr_mask = (1 << 6);
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*actlr_set = (1 << 6);
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break;
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case CPU_ARCH_CORTEX_A5:
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/*
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* Disable exclusive L1/L2 cache control
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* Enable SMP mode
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* Enable Cache and TLB maintenance broadcast
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*/
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*actlr_mask = (1 << 7) | (1 << 6) | (1 << 0);
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*actlr_set = (1 << 6) | (1 << 0);
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break;
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case CPU_ARCH_ARM1176:
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/*
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* Restrict cache size to 16KB
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* Enable the return stack
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* Enable dynamic branch prediction
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* Enable static branch prediction
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*/
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*actlr_mask = (1 << 6) | (1 << 2) | (1 << 1) | (1 << 0);
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*actlr_set = (1 << 6) | (1 << 2) | (1 << 1) | (1 << 0);
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break;
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}
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return;
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}
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}
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