mirror of https://github.com/F-Stack/f-stack.git
359 lines
8.5 KiB
ArmAsm
359 lines
8.5 KiB
ArmAsm
/*-
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* Copyright (c) 2010 Per Odlund <per.odlund@armagedon.se>
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* Copyright (C) 2011 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Developed by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of MARVELL nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <machine/asm.h>
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__FBSDID("$FreeBSD$");
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#include <machine/sysreg.h>
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.cpu cortex-a8
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.Lcoherency_level:
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.word _C_LABEL(arm_cache_loc)
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.Lcache_type:
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.word _C_LABEL(arm_cache_type)
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.Larmv7_dcache_line_size:
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.word _C_LABEL(arm_dcache_min_line_size)
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.Larmv7_icache_line_size:
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.word _C_LABEL(arm_icache_min_line_size)
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.Larmv7_idcache_line_size:
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.word _C_LABEL(arm_idcache_min_line_size)
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.Lway_mask:
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.word 0x3ff
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.Lmax_index:
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.word 0x7fff
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.Lpage_mask:
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.word 0xfff
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#define PT_NOS (1 << 5)
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#define PT_S (1 << 1)
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#define PT_INNER_NC 0
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#define PT_INNER_WT (1 << 0)
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#define PT_INNER_WB ((1 << 0) | (1 << 6))
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#define PT_INNER_WBWA (1 << 6)
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#define PT_OUTER_NC 0
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#define PT_OUTER_WT (2 << 3)
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#define PT_OUTER_WB (3 << 3)
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#define PT_OUTER_WBWA (1 << 3)
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#ifdef SMP
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#define PT_ATTR (PT_S|PT_INNER_WBWA|PT_OUTER_WBWA|PT_NOS)
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#else
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#define PT_ATTR (PT_INNER_WBWA|PT_OUTER_WBWA)
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#endif
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ENTRY(armv7_setttb)
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dsb
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orr r0, r0, #PT_ATTR
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mcr CP15_TTBR0(r0)
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isb
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#ifdef SMP
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mcr CP15_TLBIALLIS
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#else
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mcr CP15_TLBIALL
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#endif
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dsb
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isb
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RET
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END(armv7_setttb)
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ENTRY(armv7_tlb_flushID)
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dsb
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#ifdef SMP
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mcr CP15_TLBIALLIS
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mcr CP15_BPIALLIS
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#else
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mcr CP15_TLBIALL
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mcr CP15_BPIALL
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#endif
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dsb
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isb
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mov pc, lr
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END(armv7_tlb_flushID)
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ENTRY(armv7_tlb_flushID_SE)
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ldr r1, .Lpage_mask
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bic r0, r0, r1
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#ifdef SMP
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mcr CP15_TLBIMVAAIS(r0)
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mcr CP15_BPIALLIS
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#else
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mcr CP15_TLBIMVA(r0)
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mcr CP15_BPIALL
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#endif
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dsb
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isb
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mov pc, lr
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END(armv7_tlb_flushID_SE)
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/* Based on algorithm from ARM Architecture Reference Manual */
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ENTRY(armv7_dcache_wbinv_all)
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stmdb sp!, {r4, r5, r6, r7, r8, r9}
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/* Get cache level */
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ldr r0, .Lcoherency_level
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ldr r3, [r0]
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cmp r3, #0
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beq Finished
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/* For each cache level */
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mov r8, #0
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Loop1:
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/* Get cache type for given level */
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mov r2, r8, lsl #2
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add r2, r2, r2
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ldr r0, .Lcache_type
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ldr r1, [r0, r2]
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/* Get line size */
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and r2, r1, #7
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add r2, r2, #4
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/* Get number of ways */
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ldr r4, .Lway_mask
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ands r4, r4, r1, lsr #3
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clz r5, r4
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/* Get max index */
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ldr r7, .Lmax_index
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ands r7, r7, r1, lsr #13
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Loop2:
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mov r9, r4
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Loop3:
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mov r6, r8, lsl #1
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orr r6, r6, r9, lsl r5
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orr r6, r6, r7, lsl r2
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/* Clean and invalidate data cache by way/index */
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mcr CP15_DCCISW(r6)
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subs r9, r9, #1
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bge Loop3
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subs r7, r7, #1
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bge Loop2
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Skip:
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add r8, r8, #1
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cmp r3, r8
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bne Loop1
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Finished:
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dsb
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ldmia sp!, {r4, r5, r6, r7, r8, r9}
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RET
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END(armv7_dcache_wbinv_all)
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ENTRY(armv7_idcache_wbinv_all)
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stmdb sp!, {lr}
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bl armv7_dcache_wbinv_all
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#ifdef SMP
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mcr CP15_ICIALLUIS
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#else
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mcr CP15_ICIALLU
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#endif
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dsb
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isb
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ldmia sp!, {lr}
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RET
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END(armv7_idcache_wbinv_all)
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ENTRY(armv7_dcache_wb_range)
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ldr ip, .Larmv7_dcache_line_size
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ldr ip, [ip]
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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.Larmv7_wb_next:
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mcr CP15_DCCMVAC(r0)
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add r0, r0, ip
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subs r1, r1, ip
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bhi .Larmv7_wb_next
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dsb /* data synchronization barrier */
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RET
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END(armv7_dcache_wb_range)
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ENTRY(armv7_dcache_wbinv_range)
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ldr ip, .Larmv7_dcache_line_size
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ldr ip, [ip]
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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.Larmv7_wbinv_next:
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mcr CP15_DCCIMVAC(r0)
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add r0, r0, ip
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subs r1, r1, ip
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bhi .Larmv7_wbinv_next
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dsb /* data synchronization barrier */
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RET
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END(armv7_dcache_wbinv_range)
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/*
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* Note, we must not invalidate everything. If the range is too big we
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* must use wb-inv of the entire cache.
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*/
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ENTRY(armv7_dcache_inv_range)
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ldr ip, .Larmv7_dcache_line_size
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ldr ip, [ip]
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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.Larmv7_inv_next:
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mcr CP15_DCIMVAC(r0)
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add r0, r0, ip
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subs r1, r1, ip
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bhi .Larmv7_inv_next
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dsb /* data synchronization barrier */
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RET
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END(armv7_dcache_inv_range)
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ENTRY(armv7_idcache_wbinv_range)
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ldr ip, .Larmv7_idcache_line_size
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ldr ip, [ip]
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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bic r0, r0, r3
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.Larmv7_id_wbinv_next:
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mcr CP15_ICIMVAU(r0)
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mcr CP15_DCCIMVAC(r0)
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add r0, r0, ip
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subs r1, r1, ip
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bhi .Larmv7_id_wbinv_next
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dsb /* data synchronization barrier */
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isb /* instruction synchronization barrier */
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RET
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END(armv7_idcache_wbinv_range)
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ENTRY_NP(armv7_icache_sync_range)
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ldr ip, .Larmv7_icache_line_size
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ldr ip, [ip]
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sub r3, ip, #1 /* Address need not be aligned, but */
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and r2, r0, r3 /* round length up if op spans line */
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add r1, r1, r2 /* boundary: len += addr & linemask; */
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.Larmv7_sync_next:
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mcr CP15_DCCMVAC(r0)
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mcr CP15_ICIMVAU(r0)
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add r0, r0, ip
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subs r1, r1, ip
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bhi .Larmv7_sync_next
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dsb /* data synchronization barrier */
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isb /* instruction synchronization barrier */
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RET
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END(armv7_icache_sync_range)
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ENTRY(armv7_cpu_sleep)
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dsb /* data synchronization barrier */
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wfi /* wait for interrupt */
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RET
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END(armv7_cpu_sleep)
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ENTRY(armv7_context_switch)
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dsb
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orr r0, r0, #PT_ATTR
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mcr CP15_TTBR0(r0)
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isb
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#ifdef SMP
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mcr CP15_TLBIALLIS
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#else
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mcr CP15_TLBIALL
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#endif
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dsb
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isb
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RET
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END(armv7_context_switch)
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ENTRY(armv7_drain_writebuf)
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dsb
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RET
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END(armv7_drain_writebuf)
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ENTRY(armv7_sev)
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dsb
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sev
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nop
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RET
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END(armv7_sev)
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ENTRY(armv7_auxctrl)
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mrc CP15_ACTLR(r2)
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bic r3, r2, r0 /* Clear bits */
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eor r3, r3, r1 /* XOR bits */
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teq r2, r3
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mcrne CP15_ACTLR(r3)
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mov r0, r2
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RET
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END(armv7_auxctrl)
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/*
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* Invalidate all I+D+branch cache. Used by startup code, which counts
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* on the fact that only r0-r3,ip are modified and no stack space is used.
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*/
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ENTRY(armv7_idcache_inv_all)
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mov r0, #0
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mcr CP15_CSSELR(r0) @ set cache level to L1
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mrc CP15_CCSIDR(r0)
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ubfx r2, r0, #13, #15 @ get num sets - 1 from CCSIDR
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ubfx r3, r0, #3, #10 @ get numways - 1 from CCSIDR
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clz r1, r3 @ number of bits to MSB of way
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lsl r3, r3, r1 @ shift into position
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mov ip, #1 @
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lsl ip, ip, r1 @ ip now contains the way decr
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ubfx r0, r0, #0, #3 @ get linesize from CCSIDR
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add r0, r0, #4 @ apply bias
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lsl r2, r2, r0 @ shift sets by log2(linesize)
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add r3, r3, r2 @ merge numsets - 1 with numways - 1
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sub ip, ip, r2 @ subtract numsets - 1 from way decr
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mov r1, #1
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lsl r1, r1, r0 @ r1 now contains the set decr
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mov r2, ip @ r2 now contains set way decr
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/* r3 = ways/sets, r2 = way decr, r1 = set decr, r0 and ip are free */
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1: mcr CP15_DCISW(r3) @ invalidate line
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movs r0, r3 @ get current way/set
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beq 2f @ at 0 means we are done.
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movs r0, r0, lsl #10 @ clear way bits leaving only set bits
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subne r3, r3, r1 @ non-zero?, decrement set #
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subeq r3, r3, r2 @ zero?, decrement way # and restore set count
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b 1b
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2: dsb @ wait for stores to finish
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mov r0, #0 @ and ...
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mcr CP15_ICIALLU @ invalidate instruction+branch cache
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isb @ instruction sync barrier
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bx lr @ return
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END(armv7_idcache_inv_all)
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