mirror of https://github.com/F-Stack/f-stack.git
393 lines
11 KiB
C
393 lines
11 KiB
C
/*-
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* Copyright (c) 2013 Ed Schouten <ed@FreeBSD.org>
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* All rights reserved.
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*
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/stdatomic.h>
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#include <sys/types.h>
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#if defined(__SYNC_ATOMICS)
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/*
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* Memory barriers.
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*
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* It turns out __sync_synchronize() does not emit any code when used
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* with GCC 4.2. Implement our own version that does work reliably.
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*
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* Although __sync_lock_test_and_set() should only perform an acquire
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* barrier, make it do a full barrier like the other functions. This
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* should make <stdatomic.h>'s atomic_exchange_explicit() work reliably.
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*/
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static inline void
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do_sync(void)
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{
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__asm volatile (
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#if !defined(_KERNEL) || defined(SMP)
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".set noreorder\n"
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"\tsync\n"
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"\tnop\n"
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"\tnop\n"
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"\tnop\n"
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"\tnop\n"
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"\tnop\n"
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"\tnop\n"
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"\tnop\n"
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"\tnop\n"
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".set reorder\n"
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#else /* _KERNEL && !SMP */
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""
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#endif /* !KERNEL || SMP */
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: : : "memory");
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}
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typedef union {
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uint8_t v8[4];
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uint32_t v32;
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} reg_t;
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/*
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* Given a memory address pointing to an 8-bit or 16-bit integer, return
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* the address of the 32-bit word containing it.
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*/
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static inline uint32_t *
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round_to_word(void *ptr)
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{
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return ((uint32_t *)((intptr_t)ptr & ~3));
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}
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/*
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* Utility functions for loading and storing 8-bit and 16-bit integers
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* in 32-bit words at an offset corresponding with the location of the
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* atomic variable.
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*/
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static inline void
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put_1(reg_t *r, const uint8_t *offset_ptr, uint8_t val)
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{
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size_t offset;
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offset = (intptr_t)offset_ptr & 3;
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r->v8[offset] = val;
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}
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static inline uint8_t
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get_1(const reg_t *r, const uint8_t *offset_ptr)
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{
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size_t offset;
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offset = (intptr_t)offset_ptr & 3;
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return (r->v8[offset]);
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}
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static inline void
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put_2(reg_t *r, const uint16_t *offset_ptr, uint16_t val)
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{
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size_t offset;
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union {
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uint16_t in;
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uint8_t out[2];
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} bytes;
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offset = (intptr_t)offset_ptr & 3;
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bytes.in = val;
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r->v8[offset] = bytes.out[0];
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r->v8[offset + 1] = bytes.out[1];
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}
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static inline uint16_t
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get_2(const reg_t *r, const uint16_t *offset_ptr)
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{
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size_t offset;
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union {
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uint8_t in[2];
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uint16_t out;
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} bytes;
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offset = (intptr_t)offset_ptr & 3;
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bytes.in[0] = r->v8[offset];
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bytes.in[1] = r->v8[offset + 1];
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return (bytes.out);
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}
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/*
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* 8-bit and 16-bit routines.
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*
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* These operations are not natively supported by the CPU, so we use
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* some shifting and bitmasking on top of the 32-bit instructions.
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*/
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#define EMIT_LOCK_TEST_AND_SET_N(N, uintN_t) \
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uintN_t \
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__sync_lock_test_and_set_##N(uintN_t *mem, uintN_t val) \
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{ \
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uint32_t *mem32; \
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reg_t val32, negmask, old; \
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uint32_t temp; \
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\
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mem32 = round_to_word(mem); \
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val32.v32 = 0x00000000; \
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put_##N(&val32, mem, val); \
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negmask.v32 = 0xffffffff; \
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put_##N(&negmask, mem, 0); \
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\
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do_sync(); \
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__asm volatile ( \
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"1:" \
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"\tll %0, %5\n" /* Load old value. */ \
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"\tand %2, %4, %0\n" /* Remove the old value. */ \
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"\tor %2, %3\n" /* Put in the new value. */ \
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"\tsc %2, %1\n" /* Attempt to store. */ \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp) \
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: "r" (val32.v32), "r" (negmask.v32), "m" (*mem32)); \
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return (get_##N(&old, mem)); \
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}
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EMIT_LOCK_TEST_AND_SET_N(1, uint8_t)
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EMIT_LOCK_TEST_AND_SET_N(2, uint16_t)
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#define EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t) \
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uintN_t \
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__sync_val_compare_and_swap_##N(uintN_t *mem, uintN_t expected, \
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uintN_t desired) \
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{ \
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uint32_t *mem32; \
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reg_t expected32, desired32, posmask, old; \
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uint32_t negmask, temp; \
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\
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mem32 = round_to_word(mem); \
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expected32.v32 = 0x00000000; \
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put_##N(&expected32, mem, expected); \
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desired32.v32 = 0x00000000; \
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put_##N(&desired32, mem, desired); \
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posmask.v32 = 0x00000000; \
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put_##N(&posmask, mem, ~0); \
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negmask = ~posmask.v32; \
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\
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do_sync(); \
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__asm volatile ( \
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"1:" \
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"\tll %0, %7\n" /* Load old value. */ \
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"\tand %2, %5, %0\n" /* Isolate the old value. */ \
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"\tbne %2, %3, 2f\n" /* Compare to expected value. */\
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"\tand %2, %6, %0\n" /* Remove the old value. */ \
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"\tor %2, %4\n" /* Put in the new value. */ \
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"\tsc %2, %1\n" /* Attempt to store. */ \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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"2:" \
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: "=&r" (old), "=m" (*mem32), "=&r" (temp) \
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: "r" (expected32.v32), "r" (desired32.v32), \
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"r" (posmask.v32), "r" (negmask), "m" (*mem32)); \
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return (get_##N(&old, mem)); \
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}
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EMIT_VAL_COMPARE_AND_SWAP_N(1, uint8_t)
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EMIT_VAL_COMPARE_AND_SWAP_N(2, uint16_t)
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#define EMIT_ARITHMETIC_FETCH_AND_OP_N(N, uintN_t, name, op) \
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uintN_t \
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__sync_##name##_##N(uintN_t *mem, uintN_t val) \
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{ \
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uint32_t *mem32; \
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reg_t val32, posmask, old; \
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uint32_t negmask, temp1, temp2; \
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\
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mem32 = round_to_word(mem); \
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val32.v32 = 0x00000000; \
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put_##N(&val32, mem, val); \
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posmask.v32 = 0x00000000; \
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put_##N(&posmask, mem, ~0); \
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negmask = ~posmask.v32; \
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\
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do_sync(); \
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__asm volatile ( \
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"1:" \
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"\tll %0, %7\n" /* Load old value. */ \
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"\t"op" %2, %0, %4\n" /* Calculate new value. */ \
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"\tand %2, %5\n" /* Isolate the new value. */ \
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"\tand %3, %6, %0\n" /* Remove the old value. */ \
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"\tor %2, %3\n" /* Put in the new value. */ \
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"\tsc %2, %1\n" /* Attempt to store. */ \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp1), \
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"=&r" (temp2) \
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: "r" (val32.v32), "r" (posmask.v32), "r" (negmask), \
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"m" (*mem32)); \
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return (get_##N(&old, mem)); \
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}
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EMIT_ARITHMETIC_FETCH_AND_OP_N(1, uint8_t, fetch_and_add, "addu")
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EMIT_ARITHMETIC_FETCH_AND_OP_N(1, uint8_t, fetch_and_sub, "subu")
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EMIT_ARITHMETIC_FETCH_AND_OP_N(2, uint16_t, fetch_and_add, "addu")
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EMIT_ARITHMETIC_FETCH_AND_OP_N(2, uint16_t, fetch_and_sub, "subu")
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#define EMIT_BITWISE_FETCH_AND_OP_N(N, uintN_t, name, op, idempotence) \
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uintN_t \
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__sync_##name##_##N(uintN_t *mem, uintN_t val) \
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{ \
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uint32_t *mem32; \
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reg_t val32, old; \
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uint32_t temp; \
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\
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mem32 = round_to_word(mem); \
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val32.v32 = idempotence ? 0xffffffff : 0x00000000; \
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put_##N(&val32, mem, val); \
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\
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do_sync(); \
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__asm volatile ( \
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"1:" \
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"\tll %0, %4\n" /* Load old value. */ \
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"\t"op" %2, %3, %0\n" /* Calculate new value. */ \
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"\tsc %2, %1\n" /* Attempt to store. */ \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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: "=&r" (old.v32), "=m" (*mem32), "=&r" (temp) \
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: "r" (val32.v32), "m" (*mem32)); \
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return (get_##N(&old, mem)); \
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}
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EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_and, "and", 1)
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EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_or, "or", 0)
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EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_xor, "xor", 0)
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EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_and, "and", 1)
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EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_or, "or", 0)
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EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_xor, "xor", 0)
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/*
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* 32-bit routines.
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*/
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uint32_t
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__sync_val_compare_and_swap_4(uint32_t *mem, uint32_t expected,
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uint32_t desired)
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{
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uint32_t old, temp;
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do_sync();
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__asm volatile (
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"1:"
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"\tll %0, %5\n" /* Load old value. */
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"\tbne %0, %3, 2f\n" /* Compare to expected value. */
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"\tmove %2, %4\n" /* Value to store. */
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"\tsc %2, %1\n" /* Attempt to store. */
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"\tbeqz %2, 1b\n" /* Spin if failed. */
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"2:"
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: "=&r" (old), "=m" (*mem), "=&r" (temp)
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: "r" (expected), "r" (desired), "m" (*mem));
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return (old);
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}
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#define EMIT_FETCH_AND_OP_4(name, op) \
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uint32_t \
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__sync_##name##_4(uint32_t *mem, uint32_t val) \
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{ \
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uint32_t old, temp; \
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\
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do_sync(); \
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__asm volatile ( \
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"1:" \
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"\tll %0, %4\n" /* Load old value. */ \
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"\t"op"\n" /* Calculate new value. */ \
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"\tsc %2, %1\n" /* Attempt to store. */ \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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: "=&r" (old), "=m" (*mem), "=&r" (temp) \
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: "r" (val), "m" (*mem)); \
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return (old); \
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}
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EMIT_FETCH_AND_OP_4(lock_test_and_set, "move %2, %3")
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EMIT_FETCH_AND_OP_4(fetch_and_add, "addu %2, %0, %3")
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EMIT_FETCH_AND_OP_4(fetch_and_and, "and %2, %0, %3")
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EMIT_FETCH_AND_OP_4(fetch_and_or, "or %2, %0, %3")
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EMIT_FETCH_AND_OP_4(fetch_and_sub, "subu %2, %0, %3")
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EMIT_FETCH_AND_OP_4(fetch_and_xor, "xor %2, %0, %3")
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/*
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* 64-bit routines.
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*
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* Note: All the 64-bit atomic operations are only atomic when running
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* in 64-bit mode. It is assumed that code compiled for n32 and n64 fits
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* into this definition and no further safeties are needed.
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*/
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#if defined(__mips_n32) || defined(__mips_n64)
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uint64_t
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__sync_val_compare_and_swap_8(uint64_t *mem, uint64_t expected,
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uint64_t desired)
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{
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uint64_t old, temp;
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do_sync();
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__asm volatile (
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"1:"
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"\tlld %0, %5\n" /* Load old value. */
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"\tbne %0, %3, 2f\n" /* Compare to expected value. */
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"\tmove %2, %4\n" /* Value to store. */
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"\tscd %2, %1\n" /* Attempt to store. */
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"\tbeqz %2, 1b\n" /* Spin if failed. */
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"2:"
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: "=&r" (old), "=m" (*mem), "=&r" (temp)
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: "r" (expected), "r" (desired), "m" (*mem));
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return (old);
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}
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#define EMIT_FETCH_AND_OP_8(name, op) \
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uint64_t \
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__sync_##name##_8(uint64_t *mem, uint64_t val) \
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{ \
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uint64_t old, temp; \
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\
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do_sync(); \
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__asm volatile ( \
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"1:" \
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"\tlld %0, %4\n" /* Load old value. */ \
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"\t"op"\n" /* Calculate new value. */ \
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"\tscd %2, %1\n" /* Attempt to store. */ \
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"\tbeqz %2, 1b\n" /* Spin if failed. */ \
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: "=&r" (old), "=m" (*mem), "=&r" (temp) \
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: "r" (val), "m" (*mem)); \
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return (old); \
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}
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EMIT_FETCH_AND_OP_8(lock_test_and_set, "move %2, %3")
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EMIT_FETCH_AND_OP_8(fetch_and_add, "daddu %2, %0, %3")
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EMIT_FETCH_AND_OP_8(fetch_and_and, "and %2, %0, %3")
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EMIT_FETCH_AND_OP_8(fetch_and_or, "or %2, %0, %3")
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EMIT_FETCH_AND_OP_8(fetch_and_sub, "dsubu %2, %0, %3")
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EMIT_FETCH_AND_OP_8(fetch_and_xor, "xor %2, %0, %3")
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#endif /* __mips_n32 || __mips_n64 */
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#endif /* __SYNC_ATOMICS */
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