mirror of https://github.com/F-Stack/f-stack.git
843 lines
37 KiB
C
843 lines
37 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-gpio-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon gpio.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_GPIO_DEFS_H__
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#define __CVMX_GPIO_DEFS_H__
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_GPIO_BIT_CFGX(unsigned long offset)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
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(OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
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(OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
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(OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
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(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
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(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
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(OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
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(OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) ||
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(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) ||
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(OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) ||
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(OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 15))) ||
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(OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15)))))
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cvmx_warn("CVMX_GPIO_BIT_CFGX(%lu) is invalid on this chip\n", offset);
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return CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8;
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}
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#else
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#define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_GPIO_BOOT_ENA CVMX_GPIO_BOOT_ENA_FUNC()
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static inline uint64_t CVMX_GPIO_BOOT_ENA_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
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cvmx_warn("CVMX_GPIO_BOOT_ENA not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x00010700000008A8ull);
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}
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#else
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#define CVMX_GPIO_BOOT_ENA (CVMX_ADD_IO_SEG(0x00010700000008A8ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_GPIO_CLK_GENX(unsigned long offset)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
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(OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
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(OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
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(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))) ||
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(OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
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(OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
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(OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
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cvmx_warn("CVMX_GPIO_CLK_GENX(%lu) is invalid on this chip\n", offset);
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return CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8;
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}
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#else
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#define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_GPIO_CLK_QLMX(unsigned long offset)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
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(OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
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cvmx_warn("CVMX_GPIO_CLK_QLMX(%lu) is invalid on this chip\n", offset);
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return CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8;
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}
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#else
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#define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_GPIO_DBG_ENA CVMX_GPIO_DBG_ENA_FUNC()
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static inline uint64_t CVMX_GPIO_DBG_ENA_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)))
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cvmx_warn("CVMX_GPIO_DBG_ENA not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x00010700000008A0ull);
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}
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#else
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#define CVMX_GPIO_DBG_ENA (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
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#endif
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#define CVMX_GPIO_INT_CLR (CVMX_ADD_IO_SEG(0x0001070000000898ull))
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_GPIO_MULTI_CAST CVMX_GPIO_MULTI_CAST_FUNC()
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static inline uint64_t CVMX_GPIO_MULTI_CAST_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
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cvmx_warn("CVMX_GPIO_MULTI_CAST not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x00010700000008B0ull);
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}
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#else
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#define CVMX_GPIO_MULTI_CAST (CVMX_ADD_IO_SEG(0x00010700000008B0ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_GPIO_PIN_ENA CVMX_GPIO_PIN_ENA_FUNC()
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static inline uint64_t CVMX_GPIO_PIN_ENA_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN66XX)))
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cvmx_warn("CVMX_GPIO_PIN_ENA not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x00010700000008B8ull);
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}
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#else
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#define CVMX_GPIO_PIN_ENA (CVMX_ADD_IO_SEG(0x00010700000008B8ull))
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#endif
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#define CVMX_GPIO_RX_DAT (CVMX_ADD_IO_SEG(0x0001070000000880ull))
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_GPIO_TIM_CTL CVMX_GPIO_TIM_CTL_FUNC()
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static inline uint64_t CVMX_GPIO_TIM_CTL_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN68XX)))
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cvmx_warn("CVMX_GPIO_TIM_CTL not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x00010700000008A0ull);
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}
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#else
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#define CVMX_GPIO_TIM_CTL (CVMX_ADD_IO_SEG(0x00010700000008A0ull))
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#endif
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#define CVMX_GPIO_TX_CLR (CVMX_ADD_IO_SEG(0x0001070000000890ull))
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#define CVMX_GPIO_TX_SET (CVMX_ADD_IO_SEG(0x0001070000000888ull))
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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static inline uint64_t CVMX_GPIO_XBIT_CFGX(unsigned long offset)
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{
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if (!(
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(OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 16) && (offset <= 23)))) ||
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(OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 16) && (offset <= 23)))) ||
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(OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 16) && (offset <= 23)))) ||
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(OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 16) && (offset <= 19)))) ||
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(OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 16) && (offset <= 19)))) ||
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(OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 16) && (offset <= 19))))))
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cvmx_warn("CVMX_GPIO_XBIT_CFGX(%lu) is invalid on this chip\n", offset);
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return CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16;
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}
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#else
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#define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)
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#endif
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/**
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* cvmx_gpio_bit_cfg#
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*
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* Notes:
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* Only first 16 GPIO pins can introduce interrupts, GPIO_XBIT_CFG16(17,18,19)[INT_EN] and [INT_TYPE]
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* will not be used, read out always zero.
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*/
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union cvmx_gpio_bit_cfgx {
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uint64_t u64;
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struct cvmx_gpio_bit_cfgx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_17_63 : 47;
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uint64_t synce_sel : 2; /**< Selects the QLM clock output
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x0=Normal GPIO output
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01=GPIO QLM clock selected by CSR GPIO_CLK_QLM0
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11=GPIO QLM clock selected by CSR GPIO_CLK_QLM1 */
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uint64_t clk_gen : 1; /**< When TX_OE is set, GPIO pin becomes a clock */
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uint64_t clk_sel : 2; /**< Selects which of the 4 GPIO clock generators */
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uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */
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uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */
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uint64_t int_type : 1; /**< Type of interrupt
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0 = level (default)
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1 = rising edge */
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uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */
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uint64_t rx_xor : 1; /**< Invert the GPIO pin */
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uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */
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#else
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uint64_t tx_oe : 1;
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uint64_t rx_xor : 1;
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uint64_t int_en : 1;
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uint64_t int_type : 1;
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uint64_t fil_cnt : 4;
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uint64_t fil_sel : 4;
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uint64_t clk_sel : 2;
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uint64_t clk_gen : 1;
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uint64_t synce_sel : 2;
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uint64_t reserved_17_63 : 47;
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#endif
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} s;
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struct cvmx_gpio_bit_cfgx_cn30xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_12_63 : 52;
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uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */
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uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */
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uint64_t int_type : 1; /**< Type of interrupt
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0 = level (default)
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1 = rising edge */
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uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */
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uint64_t rx_xor : 1; /**< Invert the GPIO pin */
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uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */
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#else
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uint64_t tx_oe : 1;
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uint64_t rx_xor : 1;
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uint64_t int_en : 1;
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uint64_t int_type : 1;
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uint64_t fil_cnt : 4;
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uint64_t fil_sel : 4;
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uint64_t reserved_12_63 : 52;
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#endif
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} cn30xx;
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struct cvmx_gpio_bit_cfgx_cn30xx cn31xx;
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struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
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struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
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struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
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struct cvmx_gpio_bit_cfgx_cn52xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_15_63 : 49;
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uint64_t clk_gen : 1; /**< When TX_OE is set, GPIO pin becomes a clock */
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uint64_t clk_sel : 2; /**< Selects which of the 4 GPIO clock generators */
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uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */
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uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */
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uint64_t int_type : 1; /**< Type of interrupt
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0 = level (default)
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1 = rising edge */
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uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */
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uint64_t rx_xor : 1; /**< Invert the GPIO pin */
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uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */
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#else
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uint64_t tx_oe : 1;
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uint64_t rx_xor : 1;
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uint64_t int_en : 1;
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uint64_t int_type : 1;
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uint64_t fil_cnt : 4;
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uint64_t fil_sel : 4;
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uint64_t clk_sel : 2;
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uint64_t clk_gen : 1;
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uint64_t reserved_15_63 : 49;
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#endif
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} cn52xx;
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struct cvmx_gpio_bit_cfgx_cn52xx cn52xxp1;
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struct cvmx_gpio_bit_cfgx_cn52xx cn56xx;
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struct cvmx_gpio_bit_cfgx_cn52xx cn56xxp1;
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struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
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struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
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struct cvmx_gpio_bit_cfgx_s cn61xx;
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struct cvmx_gpio_bit_cfgx_s cn63xx;
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struct cvmx_gpio_bit_cfgx_s cn63xxp1;
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struct cvmx_gpio_bit_cfgx_s cn66xx;
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struct cvmx_gpio_bit_cfgx_s cn68xx;
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struct cvmx_gpio_bit_cfgx_s cn68xxp1;
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struct cvmx_gpio_bit_cfgx_s cnf71xx;
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};
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typedef union cvmx_gpio_bit_cfgx cvmx_gpio_bit_cfgx_t;
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/**
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* cvmx_gpio_boot_ena
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*/
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union cvmx_gpio_boot_ena {
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uint64_t u64;
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struct cvmx_gpio_boot_ena_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_12_63 : 52;
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uint64_t boot_ena : 4; /**< Drive boot bus chip enables [7:4] on gpio [11:8] */
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uint64_t reserved_0_7 : 8;
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#else
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uint64_t reserved_0_7 : 8;
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uint64_t boot_ena : 4;
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uint64_t reserved_12_63 : 52;
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#endif
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} s;
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struct cvmx_gpio_boot_ena_s cn30xx;
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struct cvmx_gpio_boot_ena_s cn31xx;
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struct cvmx_gpio_boot_ena_s cn50xx;
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};
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typedef union cvmx_gpio_boot_ena cvmx_gpio_boot_ena_t;
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/**
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* cvmx_gpio_clk_gen#
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*/
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union cvmx_gpio_clk_genx {
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uint64_t u64;
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struct cvmx_gpio_clk_genx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_32_63 : 32;
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uint64_t n : 32; /**< Determines the frequency of the GPIO clk generator
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NOTE: Fgpio_clk = Feclk * N / 2^32
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N = (Fgpio_clk / Feclk) * 2^32
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NOTE: writing N == 0 stops the clock generator
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N should be <= 2^31-1. */
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#else
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uint64_t n : 32;
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uint64_t reserved_32_63 : 32;
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#endif
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} s;
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struct cvmx_gpio_clk_genx_s cn52xx;
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struct cvmx_gpio_clk_genx_s cn52xxp1;
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struct cvmx_gpio_clk_genx_s cn56xx;
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struct cvmx_gpio_clk_genx_s cn56xxp1;
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struct cvmx_gpio_clk_genx_s cn61xx;
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struct cvmx_gpio_clk_genx_s cn63xx;
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struct cvmx_gpio_clk_genx_s cn63xxp1;
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struct cvmx_gpio_clk_genx_s cn66xx;
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struct cvmx_gpio_clk_genx_s cn68xx;
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struct cvmx_gpio_clk_genx_s cn68xxp1;
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struct cvmx_gpio_clk_genx_s cnf71xx;
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};
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typedef union cvmx_gpio_clk_genx cvmx_gpio_clk_genx_t;
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/**
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* cvmx_gpio_clk_qlm#
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*
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* Notes:
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* QLM0(A) and QLM1(B) can configured to source any of QLM0 or QLM2 as clock source.
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* Clock speed output for different modes ...
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*
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* Speed With Speed with
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* SERDES speed (Gbaud) DIV=0 (MHz) DIV=1 (MHz)
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* **********************************************************
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* 1.25 62.5 31.25
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* 2.5 125 62.5
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* 3.125 156.25 78.125
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* 5.0 250 125
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* 6.25 312.5 156.25
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*/
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union cvmx_gpio_clk_qlmx {
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uint64_t u64;
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struct cvmx_gpio_clk_qlmx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_11_63 : 53;
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uint64_t qlm_sel : 3; /**< Selects which DLM to select from
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x0 = select DLM0 as clock source
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x1 = Disabled */
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uint64_t reserved_3_7 : 5;
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uint64_t div : 1; /**< Internal clock divider
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0=DIV2
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1=DIV4 */
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uint64_t lane_sel : 2; /**< Selects which RX lane clock from QLMx to use as
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the GPIO internal QLMx clock. The GPIO block can
|
|
support upto two unique clocks to send out any
|
|
GPIO pin as configured by $GPIO_BIT_CFG[SYNCE_SEL]
|
|
The clock can either be a divided by 2 or divide
|
|
by 4 of the selected RX lane clock. */
|
|
#else
|
|
uint64_t lane_sel : 2;
|
|
uint64_t div : 1;
|
|
uint64_t reserved_3_7 : 5;
|
|
uint64_t qlm_sel : 3;
|
|
uint64_t reserved_11_63 : 53;
|
|
#endif
|
|
} s;
|
|
struct cvmx_gpio_clk_qlmx_cn61xx {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_10_63 : 54;
|
|
uint64_t qlm_sel : 2; /**< Selects which QLM to select from
|
|
01 = select QLM0 as clock source
|
|
1x = select QLM2 as clock source
|
|
0 = Disabled */
|
|
uint64_t reserved_3_7 : 5;
|
|
uint64_t div : 1; /**< Internal clock divider
|
|
0=DIV2
|
|
1=DIV4 */
|
|
uint64_t lane_sel : 2; /**< Selects which RX lane clock from QLMx to use as
|
|
the GPIO internal QLMx clock. The GPIO block can
|
|
support upto two unique clocks to send out any
|
|
GPIO pin as configured by $GPIO_BIT_CFG[SYNCE_SEL]
|
|
The clock can either be a divided by 2 or divide
|
|
by 4 of the selected RX lane clock. */
|
|
#else
|
|
uint64_t lane_sel : 2;
|
|
uint64_t div : 1;
|
|
uint64_t reserved_3_7 : 5;
|
|
uint64_t qlm_sel : 2;
|
|
uint64_t reserved_10_63 : 54;
|
|
#endif
|
|
} cn61xx;
|
|
struct cvmx_gpio_clk_qlmx_cn63xx {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_3_63 : 61;
|
|
uint64_t div : 1; /**< Internal clock divider
|
|
0=DIV2
|
|
1=DIV4 */
|
|
uint64_t lane_sel : 2; /**< Selects which RX lane clock from QLM2 to use as
|
|
the GPIO internal QLMx clock. The GPIO block can
|
|
support upto two unique clocks to send out any
|
|
GPIO pin as configured by $GPIO_BIT_CFG[SYNCE_SEL]
|
|
The clock can either be a divided by 2 or divide
|
|
by 4 of the selected RX lane clock. */
|
|
#else
|
|
uint64_t lane_sel : 2;
|
|
uint64_t div : 1;
|
|
uint64_t reserved_3_63 : 61;
|
|
#endif
|
|
} cn63xx;
|
|
struct cvmx_gpio_clk_qlmx_cn63xx cn63xxp1;
|
|
struct cvmx_gpio_clk_qlmx_cn61xx cn66xx;
|
|
struct cvmx_gpio_clk_qlmx_s cn68xx;
|
|
struct cvmx_gpio_clk_qlmx_s cn68xxp1;
|
|
struct cvmx_gpio_clk_qlmx_cn61xx cnf71xx;
|
|
};
|
|
typedef union cvmx_gpio_clk_qlmx cvmx_gpio_clk_qlmx_t;
|
|
|
|
/**
|
|
* cvmx_gpio_dbg_ena
|
|
*/
|
|
union cvmx_gpio_dbg_ena {
|
|
uint64_t u64;
|
|
struct cvmx_gpio_dbg_ena_s {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_21_63 : 43;
|
|
uint64_t dbg_ena : 21; /**< Enable the debug port to be driven on the gpio */
|
|
#else
|
|
uint64_t dbg_ena : 21;
|
|
uint64_t reserved_21_63 : 43;
|
|
#endif
|
|
} s;
|
|
struct cvmx_gpio_dbg_ena_s cn30xx;
|
|
struct cvmx_gpio_dbg_ena_s cn31xx;
|
|
struct cvmx_gpio_dbg_ena_s cn50xx;
|
|
};
|
|
typedef union cvmx_gpio_dbg_ena cvmx_gpio_dbg_ena_t;
|
|
|
|
/**
|
|
* cvmx_gpio_int_clr
|
|
*
|
|
* Notes:
|
|
* Only 16 out of 20 GPIOs support interrupt.GPIO_INT_CLR only apply to GPIO0-GPIO15.
|
|
*
|
|
*/
|
|
union cvmx_gpio_int_clr {
|
|
uint64_t u64;
|
|
struct cvmx_gpio_int_clr_s {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_16_63 : 48;
|
|
uint64_t type : 16; /**< Clear the interrupt rising edge detector */
|
|
#else
|
|
uint64_t type : 16;
|
|
uint64_t reserved_16_63 : 48;
|
|
#endif
|
|
} s;
|
|
struct cvmx_gpio_int_clr_s cn30xx;
|
|
struct cvmx_gpio_int_clr_s cn31xx;
|
|
struct cvmx_gpio_int_clr_s cn38xx;
|
|
struct cvmx_gpio_int_clr_s cn38xxp2;
|
|
struct cvmx_gpio_int_clr_s cn50xx;
|
|
struct cvmx_gpio_int_clr_s cn52xx;
|
|
struct cvmx_gpio_int_clr_s cn52xxp1;
|
|
struct cvmx_gpio_int_clr_s cn56xx;
|
|
struct cvmx_gpio_int_clr_s cn56xxp1;
|
|
struct cvmx_gpio_int_clr_s cn58xx;
|
|
struct cvmx_gpio_int_clr_s cn58xxp1;
|
|
struct cvmx_gpio_int_clr_s cn61xx;
|
|
struct cvmx_gpio_int_clr_s cn63xx;
|
|
struct cvmx_gpio_int_clr_s cn63xxp1;
|
|
struct cvmx_gpio_int_clr_s cn66xx;
|
|
struct cvmx_gpio_int_clr_s cn68xx;
|
|
struct cvmx_gpio_int_clr_s cn68xxp1;
|
|
struct cvmx_gpio_int_clr_s cnf71xx;
|
|
};
|
|
typedef union cvmx_gpio_int_clr cvmx_gpio_int_clr_t;
|
|
|
|
/**
|
|
* cvmx_gpio_multi_cast
|
|
*
|
|
* Notes:
|
|
* GPIO<7:4> have the option of operating in GPIO Interrupt Multicast mode. In
|
|
* this mode, the PP GPIO interrupts (CIU_INT<0-7>_SUM0/CIU_INT<0-3>_SUM4[GPIO<7:4>] values are
|
|
* stored per cnMIPS core.
|
|
* For GPIO<7:4> (x=4-7):
|
|
* When GPIO_MULTI_CAST[EN] = 1:
|
|
* When GPIO_BIT_CFGx[INT_EN]==1 & GPIO_BIT_CFGx[INT_TYPE]==1 (edge detection and interrupt enabled):
|
|
* * Reads to CIU_INT<0-7>_SUM0/<0-3>_SUM4[GPIO<x>] will return a unique interrupt state per
|
|
* cnMIPS core.
|
|
* * Reads to CIU_INT32/33_SUM0/4[GPIO<x>] will return the common GPIO<x>
|
|
* interrupt state.
|
|
* * Write of '1' to CIU_INT<0-7>_SUM0/<0-3>_SUM4[GPIO<x>] will clear the individual
|
|
* interrupt associated with the cnMIPS core.
|
|
* * Write of '1' to CIU_INT32/33_SUM0/4[GPIO<x>] will clear the common GPIO<x>
|
|
* interrupt state.
|
|
* * Write of '1' to GPIO_INT_CLR[TYPE<x>] will clear all
|
|
* CIU_INT*_SUM0/4[GPIO<x>] state across all cnMIPS cores and common GPIO<x> interrupt states.
|
|
* When GPIO_BIT_CFGx[INT_EN]==0 or GPIO_BIT_CFGx[INT_TYPE]==0,
|
|
* * either leveled interrupt or interrupt not enabled, write of '1' to CIU_INT*_SUM0/4[GPIO<x>]
|
|
* will have no effects.
|
|
* When GPIO_MULTI_CAST[EN] = 0:
|
|
* * Write of '1' to CIU_INT_SUM0/4[GPIO<x>] will have no effects, as this field is RO,
|
|
* backward compatible with o63.
|
|
* When GPIO_BIT_CFGx[INT_EN]==1 & GPIO_BIT_CFGx[INT_TYPE]==1 (edge detection and interrupt enabled):
|
|
* * Reads to CIU_INT*_SUM0/4[GPIO<x>] will return the common GPIO<X> interrupt state.
|
|
* * Write of '1' to GPIO_INT_CLR[TYPE<x>] will clear all
|
|
* CIU_INT*_SUM0/4[GPIO<x>] state across all cnMIPS cores and common GPIO<x> interrupt states.
|
|
* When GPIO_BIT_CFGx[INT_EN]==0 or GPIO_BIT_CFGx[INT_TYPE]==0,
|
|
* * either leveled interrupt or interrupt not enabled, write of '1' to CIU_INT*_SUM0/4[GPIO<x>]
|
|
* will have no effects.
|
|
*
|
|
* GPIO<15:8> and GPIO<3:0> will never be in multicast mode as those don't have per cnMIPS capabilities.
|
|
* For GPIO<y> (y=0-3,8-15):
|
|
* When GPIO_BIT_CFGx[INT_EN]==1 & GPIO_BIT_CFGx[INT_TYPE]==1 (edge detection and interrupt enabled):
|
|
* * Reads to CIU_INT*_SUM0/4[GPIO<y>] will return the common GPIO<y> interrupt state.
|
|
* * Write of '1' to GPIO_INT_CLR[TYPE<y>] will clear all CIU_INT*_SUM0/4[GPIO<y>] common GPIO<y>
|
|
* interrupt states.
|
|
* When GPIO_MULTI_CAST[EN] = 1:
|
|
* * Write of '1' to CIU_INT*_SUM0/4[GPIO<y>] will clear the common GPIO<y> interrupt state.
|
|
* When GPIO_MULTI_CAST[EN] = 0:
|
|
* * Write of '1' to CIU_INT*_SUM0/4[GPIO<y>] has no effect, as this field is RO,
|
|
* backward compatible to o63.
|
|
* When GPIO_BIT_CFGx[INT_EN]==0 or GPIO_BIT_CFGx[INT_TYPE]==0,
|
|
* * either leveled interrupt or interrupt not enabled, write of '1' to CIU_INT*_SUM0/4[GPIO<y>]
|
|
* will have no effects.
|
|
*
|
|
* Whenever there is mode change, (GPIO_BIT_CFGx[INT_EN] or GPIO_BIT_CFGx[INT_TYPE] or GPIO_MULTI_CAST[EN])
|
|
* software needs to write to $GPIO_INT_CLR to clear up all pending/stale interrupts.
|
|
*/
|
|
union cvmx_gpio_multi_cast {
|
|
uint64_t u64;
|
|
struct cvmx_gpio_multi_cast_s {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_1_63 : 63;
|
|
uint64_t en : 1; /**< Enable GPIO Interrupt Multicast mode
|
|
When EN is set, GPIO<7:4> will function in
|
|
multicast mode allowing these four GPIOs to
|
|
interrupt multi-cores.
|
|
Multicast functionality allows the GPIO to exist
|
|
as per cnMIPS interrupts as opposed to a global
|
|
interrupt. */
|
|
#else
|
|
uint64_t en : 1;
|
|
uint64_t reserved_1_63 : 63;
|
|
#endif
|
|
} s;
|
|
struct cvmx_gpio_multi_cast_s cn61xx;
|
|
struct cvmx_gpio_multi_cast_s cnf71xx;
|
|
};
|
|
typedef union cvmx_gpio_multi_cast cvmx_gpio_multi_cast_t;
|
|
|
|
/**
|
|
* cvmx_gpio_pin_ena
|
|
*
|
|
* Notes:
|
|
* GPIO0-GPIO17 has dedicated pins.
|
|
* GPIO18 share pin with UART (UART0_CTS_L/GPIO_18), GPIO18 enabled when $GPIO_PIN_ENA[ENA18]=1
|
|
* GPIO19 share pin with UART (UART1_CTS_L/GPIO_19), GPIO18 enabled when $GPIO_PIN_ENA[ENA19]=1
|
|
*/
|
|
union cvmx_gpio_pin_ena {
|
|
uint64_t u64;
|
|
struct cvmx_gpio_pin_ena_s {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_20_63 : 44;
|
|
uint64_t ena19 : 1; /**< If 0, UART1_CTS_L/GPIO_19 pin is UART pin
|
|
If 1, UART1_CTS_L/GPIO_19 pin is GPIO19 pin */
|
|
uint64_t ena18 : 1; /**< If 0, UART0_CTS_L/GPIO_18 pin is UART pin
|
|
If 1, UART0_CTS_L/GPIO_18 pin is GPIO18 pin */
|
|
uint64_t reserved_0_17 : 18;
|
|
#else
|
|
uint64_t reserved_0_17 : 18;
|
|
uint64_t ena18 : 1;
|
|
uint64_t ena19 : 1;
|
|
uint64_t reserved_20_63 : 44;
|
|
#endif
|
|
} s;
|
|
struct cvmx_gpio_pin_ena_s cn66xx;
|
|
};
|
|
typedef union cvmx_gpio_pin_ena cvmx_gpio_pin_ena_t;
|
|
|
|
/**
|
|
* cvmx_gpio_rx_dat
|
|
*/
|
|
union cvmx_gpio_rx_dat {
|
|
uint64_t u64;
|
|
struct cvmx_gpio_rx_dat_s {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_24_63 : 40;
|
|
uint64_t dat : 24; /**< GPIO Read Data */
|
|
#else
|
|
uint64_t dat : 24;
|
|
uint64_t reserved_24_63 : 40;
|
|
#endif
|
|
} s;
|
|
struct cvmx_gpio_rx_dat_s cn30xx;
|
|
struct cvmx_gpio_rx_dat_s cn31xx;
|
|
struct cvmx_gpio_rx_dat_cn38xx {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_16_63 : 48;
|
|
uint64_t dat : 16; /**< GPIO Read Data */
|
|
#else
|
|
uint64_t dat : 16;
|
|
uint64_t reserved_16_63 : 48;
|
|
#endif
|
|
} cn38xx;
|
|
struct cvmx_gpio_rx_dat_cn38xx cn38xxp2;
|
|
struct cvmx_gpio_rx_dat_s cn50xx;
|
|
struct cvmx_gpio_rx_dat_cn38xx cn52xx;
|
|
struct cvmx_gpio_rx_dat_cn38xx cn52xxp1;
|
|
struct cvmx_gpio_rx_dat_cn38xx cn56xx;
|
|
struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
|
|
struct cvmx_gpio_rx_dat_cn38xx cn58xx;
|
|
struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
|
|
struct cvmx_gpio_rx_dat_cn61xx {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_20_63 : 44;
|
|
uint64_t dat : 20; /**< GPIO Read Data */
|
|
#else
|
|
uint64_t dat : 20;
|
|
uint64_t reserved_20_63 : 44;
|
|
#endif
|
|
} cn61xx;
|
|
struct cvmx_gpio_rx_dat_cn38xx cn63xx;
|
|
struct cvmx_gpio_rx_dat_cn38xx cn63xxp1;
|
|
struct cvmx_gpio_rx_dat_cn61xx cn66xx;
|
|
struct cvmx_gpio_rx_dat_cn38xx cn68xx;
|
|
struct cvmx_gpio_rx_dat_cn38xx cn68xxp1;
|
|
struct cvmx_gpio_rx_dat_cn61xx cnf71xx;
|
|
};
|
|
typedef union cvmx_gpio_rx_dat cvmx_gpio_rx_dat_t;
|
|
|
|
/**
|
|
* cvmx_gpio_tim_ctl
|
|
*/
|
|
union cvmx_gpio_tim_ctl {
|
|
uint64_t u64;
|
|
struct cvmx_gpio_tim_ctl_s {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_4_63 : 60;
|
|
uint64_t sel : 4; /**< Selects the GPIO pin to route to TIM */
|
|
#else
|
|
uint64_t sel : 4;
|
|
uint64_t reserved_4_63 : 60;
|
|
#endif
|
|
} s;
|
|
struct cvmx_gpio_tim_ctl_s cn68xx;
|
|
struct cvmx_gpio_tim_ctl_s cn68xxp1;
|
|
};
|
|
typedef union cvmx_gpio_tim_ctl cvmx_gpio_tim_ctl_t;
|
|
|
|
/**
|
|
* cvmx_gpio_tx_clr
|
|
*/
|
|
union cvmx_gpio_tx_clr {
|
|
uint64_t u64;
|
|
struct cvmx_gpio_tx_clr_s {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_24_63 : 40;
|
|
uint64_t clr : 24; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
|
|
to '0'. When read, CLR returns the GPIO_TX_DAT
|
|
storage. */
|
|
#else
|
|
uint64_t clr : 24;
|
|
uint64_t reserved_24_63 : 40;
|
|
#endif
|
|
} s;
|
|
struct cvmx_gpio_tx_clr_s cn30xx;
|
|
struct cvmx_gpio_tx_clr_s cn31xx;
|
|
struct cvmx_gpio_tx_clr_cn38xx {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_16_63 : 48;
|
|
uint64_t clr : 16; /**< Bit mask to indicate which bits to drive to '0'. */
|
|
#else
|
|
uint64_t clr : 16;
|
|
uint64_t reserved_16_63 : 48;
|
|
#endif
|
|
} cn38xx;
|
|
struct cvmx_gpio_tx_clr_cn38xx cn38xxp2;
|
|
struct cvmx_gpio_tx_clr_s cn50xx;
|
|
struct cvmx_gpio_tx_clr_cn38xx cn52xx;
|
|
struct cvmx_gpio_tx_clr_cn38xx cn52xxp1;
|
|
struct cvmx_gpio_tx_clr_cn38xx cn56xx;
|
|
struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
|
|
struct cvmx_gpio_tx_clr_cn38xx cn58xx;
|
|
struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
|
|
struct cvmx_gpio_tx_clr_cn61xx {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_20_63 : 44;
|
|
uint64_t clr : 20; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
|
|
to '0'. When read, CLR returns the GPIO_TX_DAT
|
|
storage. */
|
|
#else
|
|
uint64_t clr : 20;
|
|
uint64_t reserved_20_63 : 44;
|
|
#endif
|
|
} cn61xx;
|
|
struct cvmx_gpio_tx_clr_cn38xx cn63xx;
|
|
struct cvmx_gpio_tx_clr_cn38xx cn63xxp1;
|
|
struct cvmx_gpio_tx_clr_cn61xx cn66xx;
|
|
struct cvmx_gpio_tx_clr_cn38xx cn68xx;
|
|
struct cvmx_gpio_tx_clr_cn38xx cn68xxp1;
|
|
struct cvmx_gpio_tx_clr_cn61xx cnf71xx;
|
|
};
|
|
typedef union cvmx_gpio_tx_clr cvmx_gpio_tx_clr_t;
|
|
|
|
/**
|
|
* cvmx_gpio_tx_set
|
|
*/
|
|
union cvmx_gpio_tx_set {
|
|
uint64_t u64;
|
|
struct cvmx_gpio_tx_set_s {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_24_63 : 40;
|
|
uint64_t set : 24; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
|
|
to '1'. When read, SET returns the GPIO_TX_DAT
|
|
storage. */
|
|
#else
|
|
uint64_t set : 24;
|
|
uint64_t reserved_24_63 : 40;
|
|
#endif
|
|
} s;
|
|
struct cvmx_gpio_tx_set_s cn30xx;
|
|
struct cvmx_gpio_tx_set_s cn31xx;
|
|
struct cvmx_gpio_tx_set_cn38xx {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_16_63 : 48;
|
|
uint64_t set : 16; /**< Bit mask to indicate which bits to drive to '1'. */
|
|
#else
|
|
uint64_t set : 16;
|
|
uint64_t reserved_16_63 : 48;
|
|
#endif
|
|
} cn38xx;
|
|
struct cvmx_gpio_tx_set_cn38xx cn38xxp2;
|
|
struct cvmx_gpio_tx_set_s cn50xx;
|
|
struct cvmx_gpio_tx_set_cn38xx cn52xx;
|
|
struct cvmx_gpio_tx_set_cn38xx cn52xxp1;
|
|
struct cvmx_gpio_tx_set_cn38xx cn56xx;
|
|
struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
|
|
struct cvmx_gpio_tx_set_cn38xx cn58xx;
|
|
struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
|
|
struct cvmx_gpio_tx_set_cn61xx {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
|
uint64_t reserved_20_63 : 44;
|
|
uint64_t set : 20; /**< Bit mask to indicate which GPIO_TX_DAT bits to set
|
|
to '1'. When read, SET returns the GPIO_TX_DAT
|
|
storage. */
|
|
#else
|
|
uint64_t set : 20;
|
|
uint64_t reserved_20_63 : 44;
|
|
#endif
|
|
} cn61xx;
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struct cvmx_gpio_tx_set_cn38xx cn63xx;
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struct cvmx_gpio_tx_set_cn38xx cn63xxp1;
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struct cvmx_gpio_tx_set_cn61xx cn66xx;
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struct cvmx_gpio_tx_set_cn38xx cn68xx;
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struct cvmx_gpio_tx_set_cn38xx cn68xxp1;
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struct cvmx_gpio_tx_set_cn61xx cnf71xx;
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};
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typedef union cvmx_gpio_tx_set cvmx_gpio_tx_set_t;
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/**
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* cvmx_gpio_xbit_cfg#
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*
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* Notes:
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* Only first 16 GPIO pins can introduce interrupts, GPIO_XBIT_CFG16(17,18,19)[INT_EN] and [INT_TYPE]
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* will not be used, read out always zero.
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*/
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union cvmx_gpio_xbit_cfgx {
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uint64_t u64;
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struct cvmx_gpio_xbit_cfgx_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_17_63 : 47;
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uint64_t synce_sel : 2; /**< Selects the QLM clock output
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x0=Normal GPIO output
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|
01=GPIO QLM clock selected by CSR GPIO_CLK_QLM0
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|
11=GPIO QLM clock selected by CSR GPIO_CLK_QLM1 */
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uint64_t clk_gen : 1; /**< When TX_OE is set, GPIO pin becomes a clock */
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uint64_t clk_sel : 2; /**< Selects which of the 4 GPIO clock generators */
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uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */
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|
uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */
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|
uint64_t int_type : 1; /**< Type of interrupt
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|
0 = level (default)
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|
1 = rising edge */
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uint64_t int_en : 1; /**< Bit mask to indicate which bits to raise interrupt */
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uint64_t rx_xor : 1; /**< Invert the GPIO pin */
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|
uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */
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|
#else
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uint64_t tx_oe : 1;
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uint64_t rx_xor : 1;
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uint64_t int_en : 1;
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|
uint64_t int_type : 1;
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|
uint64_t fil_cnt : 4;
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|
uint64_t fil_sel : 4;
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|
uint64_t clk_sel : 2;
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|
uint64_t clk_gen : 1;
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|
uint64_t synce_sel : 2;
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|
uint64_t reserved_17_63 : 47;
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|
#endif
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|
} s;
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struct cvmx_gpio_xbit_cfgx_cn30xx {
|
|
#ifdef __BIG_ENDIAN_BITFIELD
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|
uint64_t reserved_12_63 : 52;
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|
uint64_t fil_sel : 4; /**< Global counter bit-select (controls sample rate) */
|
|
uint64_t fil_cnt : 4; /**< Number of consecutive samples to change state */
|
|
uint64_t reserved_2_3 : 2;
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|
uint64_t rx_xor : 1; /**< Invert the GPIO pin */
|
|
uint64_t tx_oe : 1; /**< Drive the GPIO pin as an output pin */
|
|
#else
|
|
uint64_t tx_oe : 1;
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|
uint64_t rx_xor : 1;
|
|
uint64_t reserved_2_3 : 2;
|
|
uint64_t fil_cnt : 4;
|
|
uint64_t fil_sel : 4;
|
|
uint64_t reserved_12_63 : 52;
|
|
#endif
|
|
} cn30xx;
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|
struct cvmx_gpio_xbit_cfgx_cn30xx cn31xx;
|
|
struct cvmx_gpio_xbit_cfgx_cn30xx cn50xx;
|
|
struct cvmx_gpio_xbit_cfgx_s cn61xx;
|
|
struct cvmx_gpio_xbit_cfgx_s cn66xx;
|
|
struct cvmx_gpio_xbit_cfgx_s cnf71xx;
|
|
};
|
|
typedef union cvmx_gpio_xbit_cfgx cvmx_gpio_xbit_cfgx_t;
|
|
|
|
#endif
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