mirror of https://github.com/F-Stack/f-stack.git
578 lines
16 KiB
C
578 lines
16 KiB
C
/*
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* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2016 Intel Corporation.
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* Copyright 2017 Cavium, Inc.
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*/
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#include <stdlib.h>
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#include "pipeline_common.h"
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static __rte_always_inline int
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worker_generic(void *arg)
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{
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struct rte_event ev;
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struct worker_data *data = (struct worker_data *)arg;
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uint8_t dev_id = data->dev_id;
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uint8_t port_id = data->port_id;
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size_t sent = 0, received = 0;
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unsigned int lcore_id = rte_lcore_id();
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uint16_t nb_rx = 0, nb_tx = 0;
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while (!fdata->done) {
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if (fdata->cap.scheduler)
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fdata->cap.scheduler(lcore_id);
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if (!fdata->worker_core[lcore_id]) {
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rte_pause();
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continue;
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}
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nb_rx = rte_event_dequeue_burst(dev_id, port_id, &ev, 1, 0);
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if (nb_rx == 0) {
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rte_pause();
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continue;
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}
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received++;
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/* The first worker stage does classification */
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if (ev.queue_id == cdata.qid[0])
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ev.flow_id = ev.mbuf->hash.rss
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% cdata.num_fids;
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ev.queue_id = cdata.next_qid[ev.queue_id];
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ev.op = RTE_EVENT_OP_FORWARD;
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ev.sched_type = cdata.queue_type;
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work();
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do {
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nb_tx = rte_event_enqueue_burst(dev_id, port_id, &ev,
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1);
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} while (!nb_tx && !fdata->done);
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sent++;
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}
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worker_cleanup(dev_id, port_id, &ev, nb_tx, nb_rx);
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if (!cdata.quiet)
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printf(" worker %u thread done. RX=%zu TX=%zu\n",
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rte_lcore_id(), received, sent);
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return 0;
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}
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static int
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worker_generic_burst(void *arg)
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{
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struct rte_event events[BATCH_SIZE];
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struct worker_data *data = (struct worker_data *)arg;
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uint8_t dev_id = data->dev_id;
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uint8_t port_id = data->port_id;
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size_t sent = 0, received = 0;
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unsigned int lcore_id = rte_lcore_id();
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uint16_t i, nb_rx = 0, nb_tx = 0;
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while (!fdata->done) {
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if (fdata->cap.scheduler)
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fdata->cap.scheduler(lcore_id);
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if (!fdata->worker_core[lcore_id]) {
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rte_pause();
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continue;
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}
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nb_rx = rte_event_dequeue_burst(dev_id, port_id, events,
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RTE_DIM(events), 0);
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if (nb_rx == 0) {
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rte_pause();
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continue;
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}
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received += nb_rx;
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for (i = 0; i < nb_rx; i++) {
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/* The first worker stage does classification */
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if (events[i].queue_id == cdata.qid[0])
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events[i].flow_id = events[i].mbuf->hash.rss
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% cdata.num_fids;
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events[i].queue_id = cdata.next_qid[events[i].queue_id];
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events[i].op = RTE_EVENT_OP_FORWARD;
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events[i].sched_type = cdata.queue_type;
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work();
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}
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nb_tx = rte_event_enqueue_burst(dev_id, port_id, events, nb_rx);
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while (nb_tx < nb_rx && !fdata->done)
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nb_tx += rte_event_enqueue_burst(dev_id, port_id,
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events + nb_tx,
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nb_rx - nb_tx);
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sent += nb_tx;
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}
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worker_cleanup(dev_id, port_id, events, nb_tx, nb_rx);
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if (!cdata.quiet)
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printf(" worker %u thread done. RX=%zu TX=%zu\n",
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rte_lcore_id(), received, sent);
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return 0;
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}
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static int
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setup_eventdev_generic(struct worker_data *worker_data)
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{
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const uint8_t dev_id = 0;
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/* +1 stages is for a SINGLE_LINK TX stage */
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const uint8_t nb_queues = cdata.num_stages + 1;
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const uint8_t nb_ports = cdata.num_workers;
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struct rte_event_dev_config config = {
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.nb_event_queues = nb_queues,
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.nb_event_ports = nb_ports,
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.nb_single_link_event_port_queues = 1,
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.nb_events_limit = 4096,
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.nb_event_queue_flows = 1024,
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.nb_event_port_dequeue_depth = 128,
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.nb_event_port_enqueue_depth = 128,
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};
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struct rte_event_port_conf wkr_p_conf = {
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.dequeue_depth = cdata.worker_cq_depth,
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.enqueue_depth = 64,
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.new_event_threshold = 4096,
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.event_port_cfg = RTE_EVENT_PORT_CFG_HINT_WORKER,
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};
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struct rte_event_queue_conf wkr_q_conf = {
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.schedule_type = cdata.queue_type,
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.priority = RTE_EVENT_DEV_PRIORITY_NORMAL,
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.nb_atomic_flows = 1024,
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.nb_atomic_order_sequences = 1024,
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};
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struct rte_event_queue_conf tx_q_conf = {
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.priority = RTE_EVENT_DEV_PRIORITY_HIGHEST,
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.event_queue_cfg = RTE_EVENT_QUEUE_CFG_SINGLE_LINK,
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};
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struct port_link worker_queues[MAX_NUM_STAGES];
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uint8_t disable_implicit_release;
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unsigned int i;
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int ret, ndev = rte_event_dev_count();
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if (ndev < 1) {
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printf("%d: No Eventdev Devices Found\n", __LINE__);
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return -1;
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}
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struct rte_event_dev_info dev_info;
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ret = rte_event_dev_info_get(dev_id, &dev_info);
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printf("\tEventdev %d: %s\n", dev_id, dev_info.driver_name);
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disable_implicit_release = (dev_info.event_dev_cap &
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RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE);
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wkr_p_conf.event_port_cfg = disable_implicit_release ?
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RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL : 0;
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if (dev_info.max_num_events < config.nb_events_limit)
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config.nb_events_limit = dev_info.max_num_events;
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if (dev_info.max_event_port_dequeue_depth <
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config.nb_event_port_dequeue_depth)
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config.nb_event_port_dequeue_depth =
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dev_info.max_event_port_dequeue_depth;
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if (dev_info.max_event_port_enqueue_depth <
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config.nb_event_port_enqueue_depth)
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config.nb_event_port_enqueue_depth =
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dev_info.max_event_port_enqueue_depth;
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ret = rte_event_dev_configure(dev_id, &config);
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if (ret < 0) {
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printf("%d: Error configuring device\n", __LINE__);
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return -1;
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}
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/* Q creation - one load balanced per pipeline stage*/
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printf(" Stages:\n");
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for (i = 0; i < cdata.num_stages; i++) {
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if (rte_event_queue_setup(dev_id, i, &wkr_q_conf) < 0) {
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printf("%d: error creating qid %d\n", __LINE__, i);
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return -1;
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}
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cdata.qid[i] = i;
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cdata.next_qid[i] = i+1;
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worker_queues[i].queue_id = i;
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if (cdata.enable_queue_priorities) {
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/* calculate priority stepping for each stage, leaving
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* headroom of 1 for the SINGLE_LINK TX below
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*/
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const uint32_t prio_delta =
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(RTE_EVENT_DEV_PRIORITY_LOWEST-1) / nb_queues;
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/* higher priority for queues closer to tx */
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wkr_q_conf.priority =
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RTE_EVENT_DEV_PRIORITY_LOWEST - prio_delta * i;
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}
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const char *type_str = "Atomic";
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switch (wkr_q_conf.schedule_type) {
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case RTE_SCHED_TYPE_ORDERED:
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type_str = "Ordered";
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break;
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case RTE_SCHED_TYPE_PARALLEL:
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type_str = "Parallel";
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break;
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}
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printf("\tStage %d, Type %s\tPriority = %d\n", i, type_str,
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wkr_q_conf.priority);
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}
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printf("\n");
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/* final queue for sending to TX core */
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if (rte_event_queue_setup(dev_id, i, &tx_q_conf) < 0) {
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printf("%d: error creating qid %d\n", __LINE__, i);
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return -1;
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}
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cdata.tx_queue_id = i;
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if (wkr_p_conf.new_event_threshold > config.nb_events_limit)
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wkr_p_conf.new_event_threshold = config.nb_events_limit;
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if (wkr_p_conf.dequeue_depth > config.nb_event_port_dequeue_depth)
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wkr_p_conf.dequeue_depth = config.nb_event_port_dequeue_depth;
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if (wkr_p_conf.enqueue_depth > config.nb_event_port_enqueue_depth)
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wkr_p_conf.enqueue_depth = config.nb_event_port_enqueue_depth;
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/* set up one port per worker, linking to all stage queues */
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for (i = 0; i < cdata.num_workers; i++) {
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struct worker_data *w = &worker_data[i];
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w->dev_id = dev_id;
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if (rte_event_port_setup(dev_id, i, &wkr_p_conf) < 0) {
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printf("Error setting up port %d\n", i);
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return -1;
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}
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uint32_t s;
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for (s = 0; s < cdata.num_stages; s++) {
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if (rte_event_port_link(dev_id, i,
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&worker_queues[s].queue_id,
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&worker_queues[s].priority,
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1) != 1) {
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printf("%d: error creating link for port %d\n",
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__LINE__, i);
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return -1;
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}
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}
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w->port_id = i;
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}
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ret = rte_event_dev_service_id_get(dev_id,
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&fdata->evdev_service_id);
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if (ret != -ESRCH && ret != 0) {
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printf("Error getting the service ID for sw eventdev\n");
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return -1;
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}
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rte_service_runstate_set(fdata->evdev_service_id, 1);
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rte_service_set_runstate_mapped_check(fdata->evdev_service_id, 0);
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return dev_id;
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}
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/*
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* Initializes a given port using global settings and with the RX buffers
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* coming from the mbuf_pool passed as a parameter.
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*/
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static inline int
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port_init(uint8_t port, struct rte_mempool *mbuf_pool)
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{
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struct rte_eth_rxconf rx_conf;
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static const struct rte_eth_conf port_conf_default = {
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.rxmode = {
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.mq_mode = RTE_ETH_MQ_RX_RSS,
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},
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.rx_adv_conf = {
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.rss_conf = {
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.rss_hf = RTE_ETH_RSS_IP |
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RTE_ETH_RSS_TCP |
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RTE_ETH_RSS_UDP,
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}
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}
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};
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const uint16_t rx_rings = 1, tx_rings = 1;
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const uint16_t rx_ring_size = 512, tx_ring_size = 512;
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struct rte_eth_conf port_conf = port_conf_default;
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int retval;
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uint16_t q;
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struct rte_eth_dev_info dev_info;
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struct rte_eth_txconf txconf;
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if (!rte_eth_dev_is_valid_port(port))
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return -1;
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retval = rte_eth_dev_info_get(port, &dev_info);
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if (retval != 0) {
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printf("Error during getting device (port %u) info: %s\n",
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port, strerror(-retval));
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return retval;
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}
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if (dev_info.tx_offload_capa & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE)
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port_conf.txmode.offloads |=
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RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
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if (dev_info.rx_offload_capa & RTE_ETH_RX_OFFLOAD_RSS_HASH)
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port_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
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rx_conf = dev_info.default_rxconf;
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rx_conf.offloads = port_conf.rxmode.offloads;
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port_conf.rx_adv_conf.rss_conf.rss_hf &=
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dev_info.flow_type_rss_offloads;
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if (port_conf.rx_adv_conf.rss_conf.rss_hf !=
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port_conf_default.rx_adv_conf.rss_conf.rss_hf) {
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printf("Port %u modified RSS hash function based on hardware support,"
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"requested:%#"PRIx64" configured:%#"PRIx64"\n",
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port,
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port_conf_default.rx_adv_conf.rss_conf.rss_hf,
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port_conf.rx_adv_conf.rss_conf.rss_hf);
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}
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/* Configure the Ethernet device. */
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retval = rte_eth_dev_configure(port, rx_rings, tx_rings, &port_conf);
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if (retval != 0)
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return retval;
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/* Allocate and set up 1 RX queue per Ethernet port. */
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for (q = 0; q < rx_rings; q++) {
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retval = rte_eth_rx_queue_setup(port, q, rx_ring_size,
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rte_eth_dev_socket_id(port), &rx_conf,
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mbuf_pool);
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if (retval < 0)
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return retval;
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}
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txconf = dev_info.default_txconf;
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txconf.offloads = port_conf_default.txmode.offloads;
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/* Allocate and set up 1 TX queue per Ethernet port. */
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for (q = 0; q < tx_rings; q++) {
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retval = rte_eth_tx_queue_setup(port, q, tx_ring_size,
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rte_eth_dev_socket_id(port), &txconf);
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if (retval < 0)
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return retval;
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}
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/* Display the port MAC address. */
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struct rte_ether_addr addr;
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retval = rte_eth_macaddr_get(port, &addr);
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if (retval != 0) {
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printf("Failed to get MAC address (port %u): %s\n",
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port, rte_strerror(-retval));
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return retval;
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}
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printf("Port %u MAC: %02" PRIx8 " %02" PRIx8 " %02" PRIx8
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" %02" PRIx8 " %02" PRIx8 " %02" PRIx8 "\n",
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(unsigned int)port, RTE_ETHER_ADDR_BYTES(&addr));
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/* Enable RX in promiscuous mode for the Ethernet device. */
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retval = rte_eth_promiscuous_enable(port);
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if (retval != 0)
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return retval;
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return 0;
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}
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static int
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init_ports(uint16_t num_ports)
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{
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uint16_t portid;
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if (!cdata.num_mbuf)
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cdata.num_mbuf = 16384 * num_ports;
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struct rte_mempool *mp = rte_pktmbuf_pool_create("packet_pool",
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/* mbufs */ cdata.num_mbuf,
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/* cache_size */ 512,
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/* priv_size*/ 0,
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/* data_room_size */ RTE_MBUF_DEFAULT_BUF_SIZE,
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rte_socket_id());
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RTE_ETH_FOREACH_DEV(portid)
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if (port_init(portid, mp) != 0)
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rte_exit(EXIT_FAILURE, "Cannot init port %"PRIu16 "\n",
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portid);
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return 0;
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}
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static void
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init_adapters(uint16_t nb_ports)
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{
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int i;
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int ret;
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uint8_t tx_port_id = 0;
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uint8_t evdev_id = 0;
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struct rte_event_dev_info dev_info;
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ret = rte_event_dev_info_get(evdev_id, &dev_info);
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struct rte_event_port_conf adptr_p_conf = {
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.dequeue_depth = cdata.worker_cq_depth,
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.enqueue_depth = 64,
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.new_event_threshold = 4096,
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.event_port_cfg = RTE_EVENT_PORT_CFG_HINT_PRODUCER,
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};
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if (adptr_p_conf.new_event_threshold > dev_info.max_num_events)
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adptr_p_conf.new_event_threshold = dev_info.max_num_events;
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if (adptr_p_conf.dequeue_depth > dev_info.max_event_port_dequeue_depth)
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adptr_p_conf.dequeue_depth =
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dev_info.max_event_port_dequeue_depth;
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if (adptr_p_conf.enqueue_depth > dev_info.max_event_port_enqueue_depth)
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adptr_p_conf.enqueue_depth =
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dev_info.max_event_port_enqueue_depth;
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init_ports(nb_ports);
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/* Create one adapter for all the ethernet ports. */
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ret = rte_event_eth_rx_adapter_create(cdata.rx_adapter_id, evdev_id,
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&adptr_p_conf);
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if (ret)
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rte_exit(EXIT_FAILURE, "failed to create rx adapter[%d]",
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cdata.rx_adapter_id);
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ret = rte_event_eth_tx_adapter_create(cdata.tx_adapter_id, evdev_id,
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&adptr_p_conf);
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if (ret)
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rte_exit(EXIT_FAILURE, "failed to create tx adapter[%d]",
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cdata.tx_adapter_id);
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struct rte_event_eth_rx_adapter_queue_conf queue_conf;
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memset(&queue_conf, 0, sizeof(queue_conf));
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queue_conf.ev.sched_type = cdata.queue_type;
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queue_conf.ev.queue_id = cdata.qid[0];
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for (i = 0; i < nb_ports; i++) {
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ret = rte_event_eth_rx_adapter_queue_add(cdata.rx_adapter_id, i,
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-1, &queue_conf);
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if (ret)
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rte_exit(EXIT_FAILURE,
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"Failed to add queues to Rx adapter");
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ret = rte_event_eth_tx_adapter_queue_add(cdata.tx_adapter_id, i,
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-1);
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if (ret)
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rte_exit(EXIT_FAILURE,
|
|
"Failed to add queues to Tx adapter");
|
|
}
|
|
|
|
ret = rte_event_eth_tx_adapter_event_port_get(cdata.tx_adapter_id,
|
|
&tx_port_id);
|
|
if (ret)
|
|
rte_exit(EXIT_FAILURE,
|
|
"Failed to get Tx adapter port id");
|
|
ret = rte_event_port_link(evdev_id, tx_port_id, &cdata.tx_queue_id,
|
|
NULL, 1);
|
|
if (ret != 1)
|
|
rte_exit(EXIT_FAILURE,
|
|
"Unable to link Tx adapter port to Tx queue");
|
|
|
|
ret = rte_event_eth_rx_adapter_service_id_get(cdata.rx_adapter_id,
|
|
&fdata->rxadptr_service_id);
|
|
if (ret != -ESRCH && ret != 0) {
|
|
rte_exit(EXIT_FAILURE,
|
|
"Error getting the service ID for Rx adapter\n");
|
|
}
|
|
rte_service_runstate_set(fdata->rxadptr_service_id, 1);
|
|
rte_service_set_runstate_mapped_check(fdata->rxadptr_service_id, 0);
|
|
|
|
ret = rte_event_eth_tx_adapter_service_id_get(cdata.tx_adapter_id,
|
|
&fdata->txadptr_service_id);
|
|
if (ret != -ESRCH && ret != 0) {
|
|
rte_exit(EXIT_FAILURE,
|
|
"Error getting the service ID for Tx adapter\n");
|
|
}
|
|
rte_service_runstate_set(fdata->txadptr_service_id, 1);
|
|
rte_service_set_runstate_mapped_check(fdata->txadptr_service_id, 0);
|
|
|
|
ret = rte_event_eth_rx_adapter_start(cdata.rx_adapter_id);
|
|
if (ret)
|
|
rte_exit(EXIT_FAILURE, "Rx adapter[%d] start failed",
|
|
cdata.rx_adapter_id);
|
|
|
|
ret = rte_event_eth_tx_adapter_start(cdata.tx_adapter_id);
|
|
if (ret)
|
|
rte_exit(EXIT_FAILURE, "Tx adapter[%d] start failed",
|
|
cdata.tx_adapter_id);
|
|
|
|
if (rte_event_dev_start(evdev_id) < 0)
|
|
rte_exit(EXIT_FAILURE, "Error starting eventdev");
|
|
}
|
|
|
|
static void
|
|
generic_opt_check(void)
|
|
{
|
|
int i;
|
|
int ret;
|
|
uint32_t cap = 0;
|
|
uint8_t rx_needed = 0;
|
|
uint8_t sched_needed = 0;
|
|
struct rte_event_dev_info eventdev_info;
|
|
|
|
memset(&eventdev_info, 0, sizeof(struct rte_event_dev_info));
|
|
rte_event_dev_info_get(0, &eventdev_info);
|
|
|
|
if (cdata.all_type_queues && !(eventdev_info.event_dev_cap &
|
|
RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES))
|
|
rte_exit(EXIT_FAILURE,
|
|
"Event dev doesn't support all type queues\n");
|
|
sched_needed = !(eventdev_info.event_dev_cap &
|
|
RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED);
|
|
|
|
RTE_ETH_FOREACH_DEV(i) {
|
|
ret = rte_event_eth_rx_adapter_caps_get(0, i, &cap);
|
|
if (ret)
|
|
rte_exit(EXIT_FAILURE,
|
|
"failed to get event rx adapter capabilities");
|
|
rx_needed |=
|
|
!(cap & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT);
|
|
}
|
|
|
|
if (cdata.worker_lcore_mask == 0 ||
|
|
(rx_needed && cdata.rx_lcore_mask == 0) ||
|
|
(cdata.tx_lcore_mask == 0) ||
|
|
(sched_needed && cdata.sched_lcore_mask == 0)) {
|
|
printf("Core part of pipeline was not assigned any cores. "
|
|
"This will stall the pipeline, please check core masks "
|
|
"(use -h for details on setting core masks):\n"
|
|
"\trx: %"PRIu64"\n\ttx: %"PRIu64"\n\tsched: %"PRIu64
|
|
"\n\tworkers: %"PRIu64"\n",
|
|
cdata.rx_lcore_mask, cdata.tx_lcore_mask,
|
|
cdata.sched_lcore_mask,
|
|
cdata.worker_lcore_mask);
|
|
rte_exit(-1, "Fix core masks\n");
|
|
}
|
|
|
|
if (!sched_needed)
|
|
memset(fdata->sched_core, 0,
|
|
sizeof(unsigned int) * MAX_NUM_CORE);
|
|
if (!rx_needed)
|
|
memset(fdata->rx_core, 0,
|
|
sizeof(unsigned int) * MAX_NUM_CORE);
|
|
}
|
|
|
|
void
|
|
set_worker_generic_setup_data(struct setup_data *caps, bool burst)
|
|
{
|
|
if (burst) {
|
|
caps->worker = worker_generic_burst;
|
|
} else {
|
|
caps->worker = worker_generic;
|
|
}
|
|
|
|
caps->adptr_setup = init_adapters;
|
|
caps->scheduler = schedule_devices;
|
|
caps->evdev_setup = setup_eventdev_generic;
|
|
caps->check_opt = generic_opt_check;
|
|
}
|