mirror of https://github.com/F-Stack/f-stack.git
122 lines
5.1 KiB
C
122 lines
5.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2001-2022 Intel Corporation
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*/
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#ifndef _IDPF_LAN_VF_REGS_H_
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#define _IDPF_LAN_VF_REGS_H_
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/* Reset */
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#define VFGEN_RSTAT 0x00008800
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#define VFGEN_RSTAT_VFR_STATE_S 0
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#define VFGEN_RSTAT_VFR_STATE_M MAKEMASK(0x3, VFGEN_RSTAT_VFR_STATE_S)
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/* Control(VF Mailbox) Queue */
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#define VF_BASE 0x00006000
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#define VF_ATQBAL (VF_BASE + 0x1C00)
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#define VF_ATQBAH (VF_BASE + 0x1800)
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#define VF_ATQLEN (VF_BASE + 0x0800)
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#define VF_ATQLEN_ATQLEN_S 0
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#define VF_ATQLEN_ATQLEN_M MAKEMASK(0x3FF, VF_ATQLEN_ATQLEN_S)
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#define VF_ATQLEN_ATQVFE_S 28
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#define VF_ATQLEN_ATQVFE_M BIT(VF_ATQLEN_ATQVFE_S)
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#define VF_ATQLEN_ATQOVFL_S 29
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#define VF_ATQLEN_ATQOVFL_M BIT(VF_ATQLEN_ATQOVFL_S)
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#define VF_ATQLEN_ATQCRIT_S 30
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#define VF_ATQLEN_ATQCRIT_M BIT(VF_ATQLEN_ATQCRIT_S)
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#define VF_ATQLEN_ATQENABLE_S 31
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#define VF_ATQLEN_ATQENABLE_M BIT(VF_ATQLEN_ATQENABLE_S)
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#define VF_ATQH (VF_BASE + 0x0400)
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#define VF_ATQH_ATQH_S 0
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#define VF_ATQH_ATQH_M MAKEMASK(0x3FF, VF_ATQH_ATQH_S)
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#define VF_ATQT (VF_BASE + 0x2400)
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#define VF_ARQBAL (VF_BASE + 0x0C00)
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#define VF_ARQBAH (VF_BASE)
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#define VF_ARQLEN (VF_BASE + 0x2000)
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#define VF_ARQLEN_ARQLEN_S 0
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#define VF_ARQLEN_ARQLEN_M MAKEMASK(0x3FF, VF_ARQLEN_ARQLEN_S)
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#define VF_ARQLEN_ARQVFE_S 28
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#define VF_ARQLEN_ARQVFE_M BIT(VF_ARQLEN_ARQVFE_S)
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#define VF_ARQLEN_ARQOVFL_S 29
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#define VF_ARQLEN_ARQOVFL_M BIT(VF_ARQLEN_ARQOVFL_S)
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#define VF_ARQLEN_ARQCRIT_S 30
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#define VF_ARQLEN_ARQCRIT_M BIT(VF_ARQLEN_ARQCRIT_S)
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#define VF_ARQLEN_ARQENABLE_S 31
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#define VF_ARQLEN_ARQENABLE_M BIT(VF_ARQLEN_ARQENABLE_S)
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#define VF_ARQH (VF_BASE + 0x1400)
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#define VF_ARQH_ARQH_S 0
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#define VF_ARQH_ARQH_M MAKEMASK(0x1FFF, VF_ARQH_ARQH_S)
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#define VF_ARQT (VF_BASE + 0x1000)
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/* Transmit queues */
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#define VF_QTX_TAIL_BASE 0x00000000
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#define VF_QTX_TAIL(_QTX) (VF_QTX_TAIL_BASE + (_QTX) * 0x4)
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#define VF_QTX_TAIL_EXT_BASE 0x00040000
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#define VF_QTX_TAIL_EXT(_QTX) (VF_QTX_TAIL_EXT_BASE + ((_QTX) * 4))
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/* Receive queues */
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#define VF_QRX_TAIL_BASE 0x00002000
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#define VF_QRX_TAIL(_QRX) (VF_QRX_TAIL_BASE + ((_QRX) * 4))
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#define VF_QRX_TAIL_EXT_BASE 0x00050000
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#define VF_QRX_TAIL_EXT(_QRX) (VF_QRX_TAIL_EXT_BASE + ((_QRX) * 4))
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#define VF_QRXB_TAIL_BASE 0x00060000
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#define VF_QRXB_TAIL(_QRX) (VF_QRXB_TAIL_BASE + ((_QRX) * 4))
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/* Interrupts */
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#define VF_INT_DYN_CTL0 0x00005C00
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#define VF_INT_DYN_CTL0_INTENA_S 0
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#define VF_INT_DYN_CTL0_INTENA_M BIT(VF_INT_DYN_CTL0_INTENA_S)
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#define VF_INT_DYN_CTL0_ITR_INDX_S 3
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#define VF_INT_DYN_CTL0_ITR_INDX_M MAKEMASK(0x3, VF_INT_DYN_CTL0_ITR_INDX_S)
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#define VF_INT_DYN_CTLN(_INT) (0x00003800 + ((_INT) * 4))
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#define VF_INT_DYN_CTLN_EXT(_INT) (0x00070000 + ((_INT) * 4))
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#define VF_INT_DYN_CTLN_INTENA_S 0
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#define VF_INT_DYN_CTLN_INTENA_M BIT(VF_INT_DYN_CTLN_INTENA_S)
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#define VF_INT_DYN_CTLN_CLEARPBA_S 1
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#define VF_INT_DYN_CTLN_CLEARPBA_M BIT(VF_INT_DYN_CTLN_CLEARPBA_S)
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#define VF_INT_DYN_CTLN_SWINT_TRIG_S 2
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#define VF_INT_DYN_CTLN_SWINT_TRIG_M BIT(VF_INT_DYN_CTLN_SWINT_TRIG_S)
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#define VF_INT_DYN_CTLN_ITR_INDX_S 3
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#define VF_INT_DYN_CTLN_ITR_INDX_M MAKEMASK(0x3, VF_INT_DYN_CTLN_ITR_INDX_S)
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#define VF_INT_DYN_CTLN_INTERVAL_S 5
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#define VF_INT_DYN_CTLN_INTERVAL_M BIT(VF_INT_DYN_CTLN_INTERVAL_S)
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#define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S 24
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#define VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_M BIT(VF_INT_DYN_CTLN_SW_ITR_INDX_ENA_S)
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#define VF_INT_DYN_CTLN_SW_ITR_INDX_S 25
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#define VF_INT_DYN_CTLN_SW_ITR_INDX_M BIT(VF_INT_DYN_CTLN_SW_ITR_INDX_S)
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#define VF_INT_DYN_CTLN_WB_ON_ITR_S 30
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#define VF_INT_DYN_CTLN_WB_ON_ITR_M BIT(VF_INT_DYN_CTLN_WB_ON_ITR_S)
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#define VF_INT_DYN_CTLN_INTENA_MSK_S 31
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#define VF_INT_DYN_CTLN_INTENA_MSK_M BIT(VF_INT_DYN_CTLN_INTENA_MSK_S)
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/* _ITR is ITR index, _INT is interrupt index, _itrn_indx_spacing is spacing
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* b/w itrn registers of the same vector
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*/
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#define VF_INT_ITR0(_ITR) (0x00004C00 + ((_ITR) * 4))
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#define VF_INT_ITRN_ADDR(_ITR, _reg_start, _itrn_indx_spacing) \
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((_reg_start) + (((_ITR)) * (_itrn_indx_spacing)))
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/* For VF with 16 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x40 */
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#define VF_INT_ITRN(_INT, _ITR) (0x00002800 + ((_INT) * 4) + ((_ITR) * 0x40))
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/* For VF with 64 vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x100 */
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#define VF_INT_ITRN_64(_INT, _ITR) (0x00002C00 + ((_INT) * 4) + ((_ITR) * 0x100))
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/* For VF with 2k vector support, itrn_reg_spacing is 0x4 and itrn_indx_spacing is 0x2000 */
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#define VF_INT_ITRN_2K(_INT, _ITR) (0x00072000 + ((_INT) * 4) + ((_ITR) * 0x2000))
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#define VF_INT_ITRN_MAX_INDEX 2
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#define VF_INT_ITRN_INTERVAL_S 0
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#define VF_INT_ITRN_INTERVAL_M MAKEMASK(0xFFF, VF_INT_ITRN_INTERVAL_S)
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#define VF_INT_PBA_CLEAR 0x00008900
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#define VF_INT_ICR0_ENA1 0x00005000
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#define VF_INT_ICR0_ENA1_ADMINQ_S 30
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#define VF_INT_ICR0_ENA1_ADMINQ_M BIT(VF_INT_ICR0_ENA1_ADMINQ_S)
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#define VF_INT_ICR0_ENA1_RSVD_S 31
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#define VF_INT_ICR01 0x00004800
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#define VF_QF_HENA(_i) (0x0000C400 + ((_i) * 4))
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#define VF_QF_HENA_MAX_INDX 1
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#define VF_QF_HKEY(_i) (0x0000CC00 + ((_i) * 4))
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#define VF_QF_HKEY_MAX_INDX 12
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#define VF_QF_HLUT(_i) (0x0000D000 + ((_i) * 4))
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#define VF_QF_HLUT_MAX_INDX 15
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#endif
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